Digital Integrated Circuits Lecture 5: Logical Effort and Delay Estimation

Digital Integrated Circuits
Lecture 5: Logical Effort
Chih-Wei Liu
VLSI Signal Processing LAB
National Chiao Tung University
cwliu@twins.ee.nctu.edu.tw
DIC-Lec5 cwliu@twins.ee.nctu.edu.tw 1
Outline
RC Delay Estimation
Logical Effort
Delay in a Logic Gate
Multistage Logic Networks
Choosing the Best Number of Stages
Example
Summary
RC Delay Model
Use equivalent circuits for MOS transistors

Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R (mobility較小), capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
RC Values
Capacitance 假設nMOS/pMOS寄生電容與閘極電容相同
C = Cg = Cs = Cd = 2 fF/μm of gate width
Values similar across many processes
Resistance
R ≈ 6 KΩ*μm in 0.6um process
Improves with shorter channel lengths
Unit transistors
May refer to minimum contacted device (4/2 λ)
Or maybe 1 μm wide device
Doesn’t matter as long as you are consistent
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter by using the basic RC

delay model of nMOS and pMOS
RC model
2 Y 2
A
1 1
s
kC
2R/k
kC
g
kC
Estimate the delay of a fanout-of-1 inverter

2C
2C
2C
2 Y 2
A Y
1 1
C
R C
假設A電位提昇
C

2C
2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C
output
C
A=1

2C
2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C
C tpd = 6RC
若沒有寄生電容的ideal Inverter則為tpd = 3RC
Example: 3-input NAND
Sketch a 3-input NAND with transistor widths chosen to

achieve effective rise and fall resistances equal to a unit
inverter (R).
Sketch a 3-input NAND with transistor widths chosen to

achieve effective rise and fall resistances equal to a unit
inverter (R).
Step 1
3-input NAND Caps
We still assume C=Cg=Cdiff
Annotate the 3-input NAND gate with gate and diffusion

capacitance.
2 2 2
3-input NAND Caps
We assume C=Cg=Cdiff

capacitance.
2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C
3C
Step 2 3
3C
3C
3
3C
3C
3
3C
3C
3-input NAND Caps

capacitance.
Final result 2 2 2
3 9C
5C
3 3C
5C
3 3C
5C
Elmore Delay Model
ON transistors look like resistors

Pullup or pulldown network modeled as RC ladder
Elmore delay of RC ladder
t pd ≈ ∑
nodes i
Ri −to− sourceCi
= R1C1 + ( R1 + R2 ) C2 + ... + ( R1 + R2 + ... + RN ) C N

R1 R2 R3 RN
RC ladder
C1 C2 C3 CN
Estimate rising and falling propagation delays of a 2-

input NAND driving h identical gates.
2 2 Y
h copies
A 2
B 2x
2-input NAND
Estimate rising and falling propagation delays of a 2-

2 2 Y
A 2 6C 4hC h copies
B 2x 2C
Estimate worst-case rising and falling propagation delays

of a 2-input NAND driving h identical gates.
2 2 Y
A 2 6C 4hC h copies
B 2x 2C
Worst case rising: 只有一個pMOS開啟
R
Y t pdr = ( 6 + 4h ) RC
(6+4h)C
Estimate worst-case rising and falling propagation delays of a 2-

2 2 Y
A 2 6C 4hC h copies
B 2x 2C
Worst case falling：A已經為”1”；B的電位開始上升
R R R
x R/2 Y t pdf = ( )2C + ( + )[(6 + 4h)C ]
R/2 2C (6+4h)C 2 2 2
= (7 + 4h) RC
Delay Components
Delay has two parts

Parasitic delay
6 or 7 RC
Independent of load
Effort delay
4h RC
Proportional to load capacitance
Contamination Delay
Best-case (contamination) delay can be substantially less than

worst-case propagation delay.
Ex: If both inputs fall simultaneously
2 2 Y
A 2 6C 4hC
B 2x 2C
R
tcdr = ( )[(6 + 4h)C ]
R R 2
Y
(6+4h)C = (3 + 2h) RC
Contamination Delay
Best-case (contamination) falling delay can be substantially less

than worst-case propagation delay.
Ex: B已經為”1”；A的電位開始上升
2 2 Y
A 2 6C 4hC
B 2x 2C
R R
tcdf = ( + )[(6 + 4h)C ]
2 2
= (6 + 4h) RC
Delay Components
Again, Delay has two parts

Parasitic delay
3 or 6 RC
Independent of load
Effort delay
4h or 2h RC
Proportional to load capacitance
Diffusion Capacitance 2 2 2
3 9C
5C
3 3C
5C
3 3C
5C
We assumed contacted diffusion on every s / d.
Good layout minimizes diffusion area Recall 3-input NAND
Ex: NAND3 layout shares one diffusion contact
Reduces output capacitance by 2C
Merged un-contacted diffusion might help too
Gate capacitance: 由電晶體的寬度決定
Diffusion capacitance: 與佈局有關
2C 2C
Shared
Contacted
Diffusion Isolated
Contacted 2 2 2
Merged Diffusion
Uncontacted 3 7C
Diffusion 3 3C
3C 3C 3C 3 3C
Layout Comparison
Which layout is better?

VDD VDD
A B A B
Y Y
GND GND
Introduction
Chip designers face a bewildering array of choices

What is the best circuit topology for a function? ???
How many stages of logic give least delay?
How wide should the transistors be?
Logical effort is a method to make these decisions

Uses a simple model of delay
Allows back-of-the-envelope calculations
Helps make rapid comparisons between alternatives
Emphasizes remarkable symmetries
Example
Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded
automotive processor. Help Ben design the decoder for a register file.
A[3:0] A[3:0]
32 bits
Decoder specifications:
4:16 Decoder
16 word register file
16 words
16
Each word is 32 bits wide Register File
Each bit presents load of 3 unit-sized transistors

True and complementary address inputs A[3:0]
Each input may drive 10 unit-sized transistors
Ben needs to decide:
How many stages to use?
How large should each gate be?
How fast can decoder operate?
Express delays in process-independent unit

d abs τ = 3RC 沒有寄生電容的理想反向器
d=
τ ≈ 12 ps in 180 nm process
Normalized delay representation 40 ps in 0.6 μm process

d abs 無關於製程型態的方式來表示Delay，可使電路能
d= 依照佈局來做Delay的比較，而不必考慮不同製程
τ 對電路速度的影響
Delay has two components Linear delay model
d= f +p

d abs
d=
τ
Delay has two components
d= f +p
Effort delay: f = gh (a.k.a. stage effort)
Again has two components

d abs
d=
τ
d= f +p
Effort delay f = gh (a.k.a. stage effort)
i.e. 會耗費較多的時間去驅
g: logical effort Gate Complexity ↑, g ↑ 動相同fanout數的電晶體
Measures relative ability of gate to deliver current
g ≡ 1 for inverter

d abs
d=
τ
d= f +p
Effort delay f = gh (a.k.a. stage effort)
h: electrical effort = Cout / Cin Fan-out ↑, h ↑
Ratio of output to input capacitance
Sometimes called fanout

d abs
d=
τ
d= f +p
Parasitic delay p
Represents delay of gate driving no load
Set by internal parasitic capacitance
Delay in NAND2
Effort delay: 4hC (與外部電容

有關) 2 2 Y
Delay in 2-input NAND A 2 6C 4hC
2x 2C
d= f+p B
Normalized delay representation
4hC
= +2
3C
註：Ideal Inverter (無寄生電容、
4 Single Fanout) τ = 3RC；g = 1
= ( ) h + 2 = gh + p
3
How to calculate the logical effort g ?
Delay Plots
d =f+p 2-input
6
NAND Inverter
= gh + p g=
Normalized Delay: d
5 p=
d=
4 g=
p=
3 d=
0
0 1 2 3 4 5
Electrical Effort:
h = Cout / Cin
Delay Plots
d =f+p 2-input
6
NAND Inverter
= gh + p g = 4/3
Normalized Delay: d
5 p=2
d = (4/3)h + 2
4 g=1
What about p=1
NOR2? 3 d=h+1
2 Effort Delay: f
1
Parasitic Delay: p
0
0 1 2 3 4 5
Electrical Effort:
h = Cout / Cin
Computing Logical Effort
DEF: Logical effort is the ratio of the input capacitance of

a gate to the input capacitance of an inverter delivering
the same output current.
Measure from delay vs. fanout plots
Or estimate by counting transistor widths
2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1
Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3
Catalog of Gates
Logical effort of common gates
Gate type Number of inputs

1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8
Recall: 4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects

S1S0 S1S0 S1S0 S1S0
D0
Logical Effort =2；與輸入的

D1
數目無關
D2
大型多工器的速度與小型多工器
D3
的速度相當？
Computing Parasitic Delay
DEF:
Represents delay of gate driving no load
Set by internal parasitic capacitance
Measure from delay vs. fanout plots
Or estimate by counting total diffusion capacitances at
output
2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1
C=3 C=6 C=6

p = 3/3 = 1 p = 6/3 = 2 p = 6/3 =2
增加電晶體大小會降低電阻，但卻會增加寄生電容，但較
寬的電晶體可以摺疊，使內部的寄生電容可能變小
Catalog of Gates
Parasitic delay of common gates

In multiples of pinv (≈1)
Gate type Number of inputs

1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8
Example: FO4 Inverter
Estimate the delay of a fanout-of-4 (FO4) inverter

d
Logical Effort: g=
Electrical Effort: h=
Parasitic Delay: p=
Stage Delay: d=
Example1: FO4 Inverter
Estimate the delay of a fanout-of-4 (FO4) inverter

d
Logical Effort: g=1

Electrical Effort: h=4
Parasitic Delay: p=1 The FO4 delay is about
Stage Delay: d = gh + p = 5 200 ps in 0.6 μm process
60 ps in a 180 nm process
f/3 ns in an f μm process
經驗法則
Example2: Ring Oscillator
Estimate the frequency of an N-stage ring oscillator

Odd-number stages
Logical Effort: g=1

Electrical Effort: h=1 31 stage ring oscillator in
0.6 μm process has
Parasitic Delay: p=1 frequency of ~ 200 MHz
Stage Delay: d=2
Frequency: fosc = 1/(2*N*d) = 1/4N
如果g ≠ 1，那如何計算多級邏輯網路的延遲呢？
Logical effort generalizes to multistage networks

Path Logical Effort G= gi ∏
與電晶體大小無關
Cout-path
Path Electrical Effort H= 與電晶體大小有關
Cin-path
Path Effort F = ∏ f i = ∏ gi hi
10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z
F=GH=(5/3)(4/3)(x/10)(y/x)(z/y)(20/z)=G(20/10)
Logical effort generalizes to multistage networks

Path Logical Effort G= gi ∏
Cout-path
Path Electrical Effort H=
Cin-path
Path Effort F = ∏ f i = ∏ gi hi
Can we always write F = GH?
Branch Paths
No! Consider paths that branch:

15
90
G =
5
H =
GH = 15
90
h1 =
h2 =
F = GH?
Paths that Branch
No! Consider paths that branch:

15
90
G =1
5
H = 90 / 5 = 18
GH = 18 15
90
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6
F = g1g2h1h2 = 36 = 2GH
Branching Effort
Branching effort
Accounts for branching between stages in path
Con path + Coff path

b=
Con path
B = ∏ bi
Note:
∏h
Path branching effort
i = BH
Now we compute the path effort
F = GBH
Multistage Delays
Path Effort Delay DF = ∑ f i

Path Parasitic Delay P = ∑ pi
Path Delay
D = ∑ d i = DF + P
Recall that F = GBH
各級path effort的乘積為F；path delay則為各級path effort delay的總和

Î最小值發生在各級的path effort delay相同，亦即 fi = F1/N
Designing Fast Circuits
D = ∑ d i = DF + P
Delay is smallest when each stage bears same effort
1
fˆ = gi hi = F N
Thus minimum delay of N stage path is

1
D = NF + P N
This is a key result of logical effort

Find fastest possible delay 這種方式優於模擬
Doesn’t require calculating gate sizes
Choose Gate Sizes to Meet the Least
Delay Design
How wide should the gates be for least delay?
ˆf = gh = g Cout
Cin
gi Couti
⇒ Cini =
fˆ
Working backward, apply capacitance transformation to
find input capacitance of each gate given load it drives.
Check work by verifying input cap spec is met.
Example: 3-stage path
Select gate sizes x and y for least delay from A to B
y
x
45
A 8
x
y B
45
x
y
x
45
A 8
x
y B
45
Logical Effort G=
Electrical Effort H=
Branching Effort B=
Path Effort F=
Best Stage Effort fˆ =
Parasitic Delay P=
Delay D=
x
y
x
45
A 8
x
y B
45
Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F = GBH = 125
Best Stage Effort fˆ = 3 F = 5
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22 = 4.4 FO4
Work backward for sizes

y=
x=
x
y
x
45
A 8
x
y B
45
Example: 3-stage path fˆ = gh = g CCoutin
gi Couti
⇒ Cini =
Work backward for sizes fˆ
y = 45 * (5/3) / 5 = 15
x = (15+15) * (5/3) / 5 = 10
45
A P: 4
P: 4
N: 4 P: 12 B
N: 6 45
N: 3
Check the result:

1. the size of the NAND gate: (10+10+10)*(4/3) / 5 = 8
2. NAND gate delay: d1=g1h1+p1= (4/3)*(10+10+10) / 8 + 2 = 7
3. NAND3 gate delay: d2=g2h2+p2= (5/3)*(15+15) / 10 + 3 = 8
4. NOR gate delay: d3=g3h3+p3= (5/3)*(45/15) + 2 = 7
Î7+8+7 = 22
45
A P: 4
P: 4
N: 4 P: 12 B
N: 6 45
N: 3
Best Number of Stages
How many stages should a path use?

Minimizing number of stages is not always fastest
Example: drive 64-bit datapath with unit inverter
InitialDriver 1 1 1 1
D =
DatapathLoad 64 64 64 64
N: 1 2 3 4
f:
D:
Example: drive 64-bit datapath with unit inverter

InitialDriver 1 1 1 1
8 4 2.8
D = NF1/N + P
= N(64)1/N + N
16 8
23
DatapathLoad 64 64 64 64
N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
DIC-Lec5 cwliu@twins.ee.nctu.edu.tw Fastest 59
Derivation for Best Number of Stages
Consider adding inverters to end of path

How many give least delay? N - n1 ExtraInverters
n1 Logic Block:
D = NF + ∑ pi + ( N − n1 ) pinv
1 n1Stages
N
Path Effort F
i =1
∂D 1 1 1
= − F ln F + F + pinv = 0
N N N
∂N
ρ=F
1
N
Define best stage effort
pinv + ρ (1 − ln ρ ) = 0
pinv + ρ (1 − ln ρ ) = 0 has no closed-form solution
Neglecting parasitics (pinv = 0), we find ρ = 2.718 (e)

For pinv = 1, solve numerically for ρ = 3.59
Sensitivity Analysis
How sensitive is delay to using exactly the best number

of stages? 1.6
1.51
D(N) /D(N)
1.4
1.26
1.2 1.15
If pinv = 1
1.0
Nˆ = log ρ F (ρ=6) (ρ =2.4)
0.0
0.5 0.7 1.0 1.4 2.0
N/ N
2.4 < ρ < 6 gives delay within 15% of optimal

We can be sloppy!
I like ρ = 4
Example, Revisited
Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded
automotive processor. Help Ben design the decoder for a register file.
A[3:0] A[3:0]
32 bits
Decoder specifications:
16 word register file
4:16 Decoder
16 words
16
Each word is 32 bits wide Register File

True and complementary address inputs A[3:0]
Ben needs to decide:
How many stages to use?
How large should each gate be?
How fast can decoder operate?
Possible 4:16 Decoder
Each word is 32 bits wide

A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]
10 10 10 10 10 10 10 10
y z word[0]
96 units of wordline capacitance
y z word[15]
Number of Stages
Decoder effort is mainly electrical and branching
Electrical Effort: H = (32*3) / 10 = 9.6
Branching Effort: B=8
If we neglect logical effort (assume G = 1)

Path Effort: F = GBH = 76.8
Number of Stages: N = log4F = 3.1
Try a 3-stage design
Gate Sizes & Delay
Logical Effort: G = 1 * 6/3 * 1 = 2

Path Effort: F = GBH = 154
Stage Effort: fˆ = F 1/ 3 = 5.36 落在2.4與6之間
Path Delay: D = 3 fˆ + 1 + 4 + 1 = 22.1

Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]
10 10 10 10 10 10 10 10
y z word[0]
96 units of wordline capacitance
y z word[15]
Comparison
Compare many alternatives with a spreadsheet

Design N G P D
NAND4-INV 2 2 5 29.8
NAND2-NOR2 2 20/9 4 30.1
INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
NAND2-INV-NAND2-INV 4 16/9 6 19.7
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6
Review of Definitions
Term Stage Path

number of stages 1 N
logical effort g G = ∏ gi
H=
Cout-path
electrical effort h= Cout
Cin Cin-path
Con-path + Coff-path
branching effort b= Con-path B = ∏ bi
effort f = gh F = GBH
effort delay f DF = ∑ f i
parasitic delay p P = ∑ pi
delay d= f +p D = ∑ d i = DF + P
Method of Logical Effort
1) Compute path effort F = GBH

2) Estimate best number of stages N = log 4 F
3) Sketch path with N stages 1
4) Estimate least delay D = NF + PN
5) Determine best stage effort ˆf = F N1
gi Couti
6) Find gate sizes Cini =
fˆ
Limits of Logical Effort
Chicken and egg problem

Need path to compute G
But don’t know number of stages without G
Simplistic delay model
Neglects input rise time effects
Interconnect
Iteration required in designs with wire
Maximum speed only
Not minimum area/power for constrained delay
Summary
Logical effort is useful for thinking of delay in circuits

Numeric logical effort characterizes gates
NANDs are faster than NORs in CMOS
Paths are fastest when effort delays are ~4
Path delay is weakly sensitive to stages, sizes
But using fewer stages doesn’t mean faster paths
Delay of path is about log4F FO4 inverter delays
Inverters and NAND2 best for driving large caps
Provides language for discussing fast circuits
But requires practice to master

Digital Integrated Circuits Lecture 5: Logical Effort and Delay Estimation

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Digital Integrated Circuits

Lecture 5: Logical Effort

 Use equivalent circuits for MOS transistors

 Estimate the delay of a fanout-of-1 inverter by using the basic RC

 Estimate the delay of a fanout-of-1 inverter

 Estimate the delay of a fanout-of-1 inverter

 Estimate the delay of a fanout-of-1 inverter

若沒有寄生電容的ideal Inverter則為tpd = 3RC

 Sketch a 3-input NAND with transistor widths chosen to

 Sketch a 3-input NAND with transistor widths chosen to

 Annotate the 3-input NAND gate with gate and diffusion

 Annotate the 3-input NAND gate with gate and diffusion

 Annotate the 3-input NAND gate with gate and diffusion

 ON transistors look like resistors

= R1C1 + ( R1 + R2 ) C2 + ... + ( R1 + R2 + ... + RN ) C N

 Estimate rising and falling propagation delays of a 2-

 Estimate rising and falling propagation delays of a 2-

 Estimate worst-case rising and falling propagation delays

 Estimate worst-case rising and falling propagation delays of a 2-

 Delay has two parts

 Best-case (contamination) delay can be substantially less than

 Best-case (contamination) falling delay can be substantially less

 Again, Delay has two parts

 Which layout is better?

 Chip designers face a bewildering array of choices

 Logical effort is a method to make these decisions

 Each bit presents load of 3 unit-sized transistors

 Express delays in process-independent unit

 Express delays in process-independent unit

 Express delays in process-independent unit

 Express delays in process-independent unit

 Express delays in process-independent unit

 Express delays in process-independent unit

 Effort delay: 4hC (與外部電容

 DEF: Logical effort is the ratio of the input capacitance of

Cin = 3 Cin = 4 Cin = 5

 Logical effort of common gates

Gate type Number of inputs

 4:1 mux chooses one of 4 inputs using two selects

Logical Effort =2；與輸入的

C=3 C=6 C=6

 Parasitic delay of common gates

Gate type Number of inputs

 Estimate the delay of a fanout-of-4 (FO4) inverter

 Estimate the delay of a fanout-of-4 (FO4) inverter

Logical Effort: g=1

 Estimate the frequency of an N-stage ring oscillator

Logical Effort: g=1

 Logical effort generalizes to multistage networks

 Logical effort generalizes to multistage networks

 Can we always write F = GH?

 No! Consider paths that branch:

 No! Consider paths that branch:

Con path + Coff path

 Path Effort Delay DF = ∑ f i

Recall that F = GBH

各級path effort的乘積為F；path delay則為各級path effort delay的總和

 Thus minimum delay of N stage path is

 This is a key result of logical effort

 Select gate sizes x and y for least delay from A to B

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

 Work backward for sizes

 Check the result:

Use equivalent circuits for MOS transistors

Estimate the delay of a fanout-of-1 inverter by using the basic RC

Estimate the delay of a fanout-of-1 inverter

Estimate the delay of a fanout-of-1 inverter

Estimate the delay of a fanout-of-1 inverter

Sketch a 3-input NAND with transistor widths chosen to

Sketch a 3-input NAND with transistor widths chosen to

Annotate the 3-input NAND gate with gate and diffusion

Annotate the 3-input NAND gate with gate and diffusion

Annotate the 3-input NAND gate with gate and diffusion

ON transistors look like resistors

Estimate rising and falling propagation delays of a 2-

Estimate rising and falling propagation delays of a 2-

Estimate worst-case rising and falling propagation delays

Estimate worst-case rising and falling propagation delays of a 2-

Delay has two parts

Best-case (contamination) delay can be substantially less than

Best-case (contamination) falling delay can be substantially less

Again, Delay has two parts

Which layout is better?

Chip designers face a bewildering array of choices

Logical effort is a method to make these decisions

Each bit presents load of 3 unit-sized transistors

Express delays in process-independent unit

Express delays in process-independent unit

Express delays in process-independent unit

Express delays in process-independent unit

Express delays in process-independent unit

Express delays in process-independent unit

Effort delay: 4hC (與外部電容

DEF: Logical effort is the ratio of the input capacitance of

Logical effort of common gates

4:1 mux chooses one of 4 inputs using two selects

Parasitic delay of common gates

Estimate the delay of a fanout-of-4 (FO4) inverter

Estimate the delay of a fanout-of-4 (FO4) inverter

Estimate the frequency of an N-stage ring oscillator

Logical effort generalizes to multistage networks

Logical effort generalizes to multistage networks

Can we always write F = GH?

No! Consider paths that branch:

No! Consider paths that branch:

Path Effort Delay DF = ∑ f i

Thus minimum delay of N stage path is

This is a key result of logical effort

Select gate sizes x and y for least delay from A to B

Logical Effort G = (4/3)(5/3)(5/3) = 100/27

Work backward for sizes

Check the result:

How many stages should a path use?

Example: drive 64-bit datapath with unit inverter

Consider adding inverters to end of path

pinv + ρ (1 − ln ρ ) = 0 has no closed-form solution

Neglecting parasitics (pinv = 0), we find ρ = 2.718 (e)

How sensitive is delay to using exactly the best number

2.4 < ρ < 6 gives delay within 15% of optimal

Each bit presents load of 3 unit-sized transistors

Each word is 32 bits wide

If we neglect logical effort (assume G = 1)

Try a 3-stage design

Compare many alternatives with a spreadsheet

Chicken and egg problem

Logical effort is useful for thinking of delay in circuits