1

OP-AMP
1. Consider the circuit shown below. Assume diodes and op-amps are ideal.
5 k

5 k D1
vi
v0
5 k D2
10 k

–15V
The plot of transfer characteristic is
v0 v0 v0 v0

5 5 –5 –5
vi vi
(a) (b) (c) –10 (d)
vi vi –5 –5
5 5 10
2. Assume that the operational amplifier in figure is ideal the current I through the 1 k resistor is ________.
2 k

1 k
2 mA 2 k

3. The op-amp circuit shown below behaves as a

C
VS
R

C1
C2

(a) High pass filter (b) Band pass filter (c) Integrator (d) All pass filter

4. In the system shown in figure, the input x(t )  sin t . In the steady state, the response y (t ) will be

s
x(t )   y (t )
s 1
1 1
(a) sin (t  45º ) (b) sin (t  45º ) (c) sin (t  45º ) (d) sin (t  45º )
2 2

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 2
5. In the Wien Bridge oscillator circuit shown in figure, the bridge is balanced when
R3 R1 1
(a)  , C1
R4 R2 R1C1R2C2
R1 VCC
R C 1
(b) 2  2 ,  
R1 C1 R1C1R2C2

R3 R1 C2 1 R3
(c)   , –VCC
R4 R2 C1 R1C1R2C2
C2 R2
R4
R R C 1
(d) 3  1  2 ,  
R4 R2 C1 R1C1R2C2

6. For the circuit shown below, taking the op-amp as ideal, the output voltage Vout in terms of the input voltages
V1 , V2 and V3 is 9

(a) 1.8V1  7.2 V2  V3 +VCC

1
(b) 2V1  8V2  9 V3 V3
1 Vout
V1
(c) 7.2 V1  1.8V2  V3 4
V2 –VSS
(d) 8V1  2V2  9 V3
7. For the circuit shown below, assume that the op-amp is ideal.
R
R R

R
2R
v0
vs
2R

Which one of the following is TRUE ?

(a) v0  vs (b) v0  1.5 vs (c) v0  2.5 vs (d) v0  5 vs
8. The circuit shown in the figure is

R1

V R2 LOAD

rV r || R2
(a) a voltage source with voltage (b) a voltage source with voltage V
R1 || R2 R1
r || R2 V R2 V
(c) a current source with current  (d) a current source with current 
R1  R2 r R1  R2 r

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 3
9. The Zener diode in the regulator circuit shown in the figure has a Zener voltage of 5.8 volts and a Zener knee
current of 0.5 mA. The maximum load current drawn from this circuit ensuring proper functioning over the input
voltage range between 20 volts and 30 volts, is
1k

Vin = (20 V-30V ) VZ = 5.8V Load

(a) 23.7 mA (b) 14.2 mA (c) 13.7 mA (d) 24.2 mA

10. A Zener diode regulator in the figure is to be designed to meet the specifications I L  10 mA, V0  10 V and
Vin varies from 30 V to 50 V. The Zener diode has VZ  10 V and I ZK (knee current) = 1 mA. For satisfac-
tory operation
R
IZ IL = 10 mA

Vin VZ V0 RL

(a) R  1800  (b) 2000   R  2200 

(c) 3700   R  4000  (d) R  4000 
11. What is the voltage measured from the negative terminal of C4 to the negative terminal of the transformer ?
C1 C3

5V D1 D2 D3

C2 C4
(a) –10 V (b) –20 V (c) 10 V (d) 20 V
12. The Zener diode in the circuit shown in figure-1 has the characteristics shown in figure-2. If R2 is the lowest
load resistance to be used in the regulated supply, then to get load regulation,
R1 IL If
(A)
I1 I2
Unregulated Vz
Vin R2 Vout VR Vf
DC input V
10mA

IR
Figure (1) Figure (2)

V0  0.01 R2 (V  V0 ) R2 (V  V0 ) R2 V  0.01 R2
(a) R1  (b) R1  i (c) R1  i (d) R1  0
(Vi  V0 ) R2 V0  0.01 R2 V0  0.01 R2 (Vi  V0 ) R2

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 4

13. The following op-amp circuit is a

R

C C
Vin
Vout
R (k–1)R

(a) Low-pass filter (b) High-pass filter (c) Band-pass filter (d) Band-stop filter
14. For the circuit shown below op-amp is ideal. The value of vid as marked is (in volt) nearly equal to ?
4V

+15 V
10 K vid
v0

–15 V
40 K
10 K

15. Let a signal a1 sin (1t  1 ) be applied to a stable linear time invariant system. Let the corresponding steady
state output be represented as a2 F (2t  2 ) . Then which of the following statements is true ?
(a) F is not necessarily a ‘sine’ or ‘cosine’ function but must be periodic with 1  2 .
(b) F must be a ‘sine’ or ‘cosine’ function with a1  a2 .
(c) F must be a ‘sine’ function with 1  2 and 1  2 .
(d) F must be a ‘sine’ or ‘cosine’ function with 1  2 .
16. For given circuit, condition for linear operation is given by ?
R

2R V0

Vi
2R R
iL RL

2 R 4 R 4 2
(a) Vi  Vsat (b) Vi  Vsat (c) iL RL  Vsat (d) iL RL  Vsat
3 R1 3 RL 3 3

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 5

17. For which of the following conditions, the circuit shown below will function as precision full wave rectifier ?
R2 R3
R R1

R
Vout
Vin

(a) R1  R 2  R (b) R1  R 3  R (c) R 2  2R1 (d) R1  R 2  R 3

18. In the following circuit, find the output voltage V0

Iin
RA
RS
V0

RB

R   R 
(a)  A   Iin  R S (b) Iin  R S  1  A 
 RB   RB 

R   R 
(c)  B   Iin  R S (d) Iin  R S  1  B 
 RA   RA 

19. The op-amp shown in the figure is ideal. The input impedance vin iin is given by
Z
iin
vout

vin
R1
R2

R1 R2 R1
(a) Z (b)  Z (c) Z (d)  Z
R2 R1 R1  R2

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 6
20. In the circuit shown below the op-amps are ideal. Then V out in volts is
1 k 1 k
–2 V
+15 V
+15 V

Vout

1 k –15 V
–15 V

+1 V 1 k
1 k

21. The following circuit has R = 10 k, C = 10 µF. The input voltage is a sinusoid at 50 Hz with an r.m.s. value of
10 V. Under ideal conditions, the current is from the source is
R
10 k
is
op-amp

Vs = 10 V r.m.s. R
50 Hz
10 k
10 µF C

(a) 10 mA leading by 90º (b) 20 mA leading by 90º

(c) 10 A leading by 90º (d) 10 mA lagging by 90º
22. A series R-L circuit is excited at t = 0 by closing a switch as shown in the figure. Assuming zero initial condi-
tions, the value of d 2i dt 2 at t = 0 is
R

V L

(a) V L (b)  V L (c) 0 (d)  RV L2

23. In the circuit shown below, the op-amp is ideal and Zener voltage of the diode is 2.5 volt. At the input, unit step
voltage is applied, i.e. V in(t) = u(t) volts. Also, at t = 0, the voltage across each of the capacitors is zero.
1µF

1V 1 k 1µF
Vin (t)
0V t = 0 Vout (t)

The time t, in milliseconds, at which the output voltage Vout crosses –10 V is
(a) 2.5 (b) 5 (c) 7.5 (d) 10

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 7
24. For the circuit given in the figure, the voltage V C (in volts) across the capacitor is
100 

5 sin(5t)V 1µF VC

100 
(a) 1.25 2 sin  5t  0.25  (b) 1.25 2 sin  5t  0.125 
(c) 2.5 2 sin  5t  0.25  (d) 2.5 2 sin  5t  0.125 
25. For an ideal op-amp circuit given below, the dc gain and the cut off frequency, respectively are
1 k
+

1 F –
2
10k
1k 

(a) 1 and 1 kHz (b) 1 and 100 Hz (c) 11 and 1 kHz (d) 11 and 100 Hz
Ans. (c)
26. The output voltage V0 of the OPAMP circuit given below is ___________ V.

2R

R
–
R V0
1V +
R
2V
R
3V

Ans. (0)
27. An OPAMP is connected in a circuit with a Zener diode as shown in the figure. The value of resistance
R in k for obtaining a regulated output V0 = 9V is __________________
(Specify your answer to two digits after the decimal point)
1k

R
–
V0
+
1k
V2=4.7 V
Vm=12V

Ans. (1.093)
28. In an ideal operational amplifier depicted below, the potential at node A is
25k
+12
1k A
–
+ +
– 1V –12

(a) 0.5 V (b) 0 V (c) 5 V (d) 25 V

Ans. (a)

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 8
29. The non-inverting amplifier shown in the following circuit uses a 741 Op-Amp with
R1  1K, R 2  39K, R 3  1K . The typical parameter values for the 741 Op-Amp are: Open loop
gain Av = 2 × 105, Input resistance R i  2M and Output resistance R o  75 . The Input resistance and
Output resistance for the non-inverting amplifier respectively will be about:
+15V
R1
(a) 400G, 0.015 +
–
(b) 10G, 0.015 R2
–15V I2
(c) 400G, 0.00037
R3
(d) 10G, 0.00037
Ans. (b)
30. The ideal OP-AMP with input resistance Ri, output resistance Ro and gain A, has
(a) Ri  , A  , R0  0 (b) Ri  , BW  , R0  0

(c) CMRR  , A  , Slew rate   (d) Ri  0, A  , R0  

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