Logic Gate Delay Modeling -1

Bishnu Prasad Das

Research Scholar
CEDT, IISc, Bangalore
bpdas@cedt.iisc.ernet.in
 OUTLINE
• Motivation
• Delay Model History
• Delay Definition
• Types of Models
-RC delay Models
-Logical Effort
• Limitation of Logical Effort
• Summary
 Motivation

• Why Model is required?

– For fast simulation
– Solving differential equation is difficult
– For creating optimal design
– Real design will be always more costly and
time consuming.So model is used to simulate
the system before actual implementation.
 Types of Models
• Physical Models
– Based on Physical phenomena of device
• Empirical Models
– Based on curve fitting ( i.e. Quadratic,Cubic etc.)
– No physical significance.
• Table Models
– Storing the data in a Lookup Table
– Do interpolation between stored data
Delay Model History

Courtesy : Synopsys
 Delay Definitions
• tpdr: rising propagation delay
– From input to rising output crossing VDD/2
• tpdf: falling propagation delay
– From input to falling output crossing VDD/2
• tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
• tr: rise slew
– From output crossing 0.2 VDD to 0.8 VDD
• tf: fall slew
– From output crossing 0.8 VDD to 0.2 VDD
 Delay Definitions

• tcdr: rising contamination delay

– From input to rising output crossing VDD/2
• tcdf: falling contamination delay
– From input to falling output crossing VDD/2
• tcd: average contamination delay
– tpd = (tcdr + tcdf)/2
 Delay Definitions
• tpdr: rising propagation delay
– From input to rising output crossing VDD/2
• tpdf: falling propagation delay
– From input to falling output crossing VDD/2
• tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
• tr: rise time
– From output crossing 0.2 VDD to 0.8 VDD
• tf: fall time
– From output crossing 0.8 VDD to 0.2 VDD
 Delay Definitions

• tcdr: rising contamination delay

– From input to rising output crossing VDD/2
• tcdf: falling contamination delay
– From input to falling output crossing VDD/2
• tcd: average contamination delay
– tpd = (tcdr + tcdf)/2
 RC Delay Models
• Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d
 Example: 3-input NAND
• Sketch a 3-input NAND with transistor
widths chosen to achieve effective rise and
fall resistances equal to a unit inverter (R).
 Example: 3-input NAND
• Sketch a 3-input NAND with transistor
widths chosen to achieve effective rise and
fall resistances equal to a unit inverter (R).
 Example: 3-input NAND
• Sketch a 3-input NAND with transistor
widths chosen to achieve effective rise and
fall resistances equal to a unit inverter (R).

2 2 2

3
3
3
 3-input NAND Caps
• Annotate the 3-input NAND gate with gate
and diffusion capacitance.

2 2 2

3
 3-input NAND Caps
• Annotate the 3-input NAND gate with gate
and diffusion capacitance.

2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C

3C
3
3C
3C
3
3C
3C
3
3C
3C
 3-input NAND Caps
• Annotate the 3-input NAND gate with gate
and diffusion capacitance.

2 2 2

3 9C
5C
3 3C
5C
3 3C
5C
 Elmore Delay
• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder
t pd  
nodes i
Ri to sourceCi

 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  CN

R1 R2 R3 RN

C1 C2 C3 CN
 Example: 2-input NAND

• Estimate worst-case rising and falling delay

of 2-input NAND driving h identical gates.
2 2 Y
A 2 6C 4hC

B 2x 2C h copies
 Example: 2-input NAND

• Estimate worst-case rising and falling delay

of 2-input NAND driving h identical gates.
2 2 Y
A 2 6C 4hC

B 2x 2C h copies

R
Y
(6+4h)C t pdr 
 Example: 2-input NAND

• Estimate rising and falling propagation delays

of a 2-input NAND driving h identical gates.

2 2 Y
A 2 6C 4hC

B 2x 2C
h copies

t pdr  6  4h  RC
Y
(6+4h)C
 Example: 2-input NAND
• Estimate rising and falling propagation delays of a
2-input NAND driving h identical gates.

2 2 Y
A 2 6C 4hC

B 2x 2C h copies
 Example: 2-input NAND
• Estimate rising and falling propagation delays of a
2-input NAND driving h identical gates.

2 2 Y
A 2 6C 4hC

B 2x 2C h copies

x
2C
R/2 Y
(6+4h)C
t pdf 
R/2
 Example: 2-input NAND
• Estimate rising and falling propagation delays of a
2-input NAND driving h identical gates.

2 2 Y
A 2 6C 4hC
h copies
B 2x 2C

x R/2 Y
t pdf   2C   R2    6  4h  C   R2  R2 
  7  4h  RC
R/2 2C (6+4h)C
 Delay Components

• Delay has two parts

– Parasitic delay
• 6 or 7 RC
• Independent of load
– Effort delay
• 4h RC
• Proportional to load capacitance
 Contamination Delay
• Best-case (contamination) delay can be substantially
less than propagation delay.
• Ex: If both inputs fall simultaneously

2 2 Y
A 2 6C 4hC

B 2x 2C

R R
Y
tcdr   3  2h  RC
(6+4h)C
 Layout Comparison
• Which layout is better?
VDD VDD
A B A B

Y Y

GND GND
 Delay in a Logic Gate
• Express delays in process-independent unit
d abs
d τ = 3RC
 = FO1 delay without
parasitic delay
• Delay has two components
d f p
• f is due to external loading
• p is due to self loading
 Delay in a Logic Gate
• Express delays in process-independent unit
d abs
d τ = 3RC
 = FO1 delay without
parasitic delay
• Delay has two components
d f p
• Effort delay f = gh (a.k.a. stage effort)
– Again has two components
 Delay in a Logic Gate
• Express delays in process-independent unit
d abs τ = 3RC
d = FO1 delay without
 parasitic delay
• Delay has two components
d f p
• Effort delay f = gh (a.k.a. stage effort)
– Again has two components
• g: logical effort
– Measures relative ability of gate to deliver current
– g  1 for inverter
 Delay in a Logic Gate
• Express delays in process-independent unit
d abs τ = 3RC
d
 = FO1 delay without
parasitic delay
• Delay has two components
d f p
• Effort delay f = gh (a.k.a. stage effort)
– Again has two components
• h: electrical effort = Cout / Cin
– Ratio of output to input capacitance
– Sometimes called fanout
 Delay in a Logic Gate
• Express delays in process-independent unit
d abs τ = 3RC
d
 = FO1 delay without
parasitic delay
• Delay has two components
d f p

• Parasitic delay p
– Represents delay of gate driving no load
– Set by internal parasitic capacitance
 Effort Delay
• Logical Effort g = Cingate/Cin_unit_inv

• Electrical Effort h = Cout / Cingate

• f = g*h = (Cingate/Cin_unit_inv)*(Cout / Cingate)

= (Cout / Cin_unit_inv)

• (Dactual)ext = g*h * τ = (Cout / Cin_unit_inv)*3*R*C

= (Cout / Cin_unit_inv)*R*Cin_unit_inv
= Cout*R
 Computing Logical Effort
• DEF: Logical effort is the ratio of the input
capacitance of a gate to the input capacitance of
an inverter delivering the same output current.
• Measure from delay vs. fanout plots
• Or estimate by counting transistor widths

2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1

Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3
 Catalog of Gates
• Logical effort of common gates

Gate type Number of inputs

1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8
 Catalog of Gates
• Parasitic delay of common gates
– In multiples of pinv (1)
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8
 Delay Plots
2-input
6
NAND Inverter
d =f+p g=

NormalizedDelay:d
5 p=
= gh + p 4 g=
d=
p=
3 d=
2

0
0 1 2 3 4 5

ElectricalEffort:
h = Cout / Cin
 Delay Plots
2-input
6
NAND Inverter
d =f+p g = 4/3

NormalizedDelay:d
5 p=2
= gh + p 4 g=1
d = (4/3)h + 2
p=1
3 d = h +1
• What about 2 EffortDelay:f

NOR2? 1
Parasitic Delay: p
0
0 1 2 3 4 5

ElectricalEffort:
h = Cout / Cin
 Example: Ring Oscillator
• Estimate the frequency of an N-stage ring
oscillator

Logical Effort: g =
Electrical Effort: h =
Parasitic Delay: p =
Stage Delay: d=
Frequency: fosc =
 Example: Ring Oscillator
• Estimate the frequency of an N-stage ring
oscillator

Logical Effort: g = 1
Electrical Effort: h = 1
Parasitic Delay: p = 1
Stage Delay: d=2
Frequency: fosc = 1/(2*N*d) = 1/4N
 Example: FO4 Inverter
• Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort: g =
Electrical Effort:h =
Parasitic Delay: p =
Stage Delay: d=
 Example: FO4 Inverter
• Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort: g = 1
The FO4 delay is about
Electrical Effort: h = 4
200 ps in 0.6 mm process
Parasitic Delay: p = 1 60 ps in a 180 nm process
Stage Delay: d=5 f/3 ns in an f mm process
Multistage Logic Networks

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z
 Limits of Logical Effort

• Chicken and egg problem

– Need path to compute G
– But don’t know number of stages without G
• Simplistic delay model
– Neglects input rise time effects
• Interconnect
– Iteration required in designs with wire
• Maximum speed only
– Not minimum area/power for constrained delay
 Summary

RC Delay Model

Delay measurement using Logical Effort Method
Gate sizing using Logical Effort for minimum
delay
Limitations of Logical Effort
 Reference
• N. H. E. Weste and D. Harris, “CMOS VLSI Design, A
circuits and Systems Perspective” 3rd edition Pearson
Addison Wesley
• Rabaey, Chandrakasan and Nikolic, “Digital Integrated
Circuits, a Design Perspective”, Pearson Education