‭UC Berkeley EECS151‬

‭ _____________________________‬
_
‭↑‬‭Your Name (first last)‬
‭EECS251A‬ ‭______________________________‬
‭SID‬ ‭↑‬

‭ _____________________________‬
_ ‭Fall 2023 Midterm 2‬ ‭______________________________‬
‭↑‬‭Name of person on left (or aisle)‬ ‭Name of person on right (or aisle)‬‭↑‬

‭ _____________________________‬
_ ‭_____________________________‬
‭______________________________‬
‭↑‬ ‭Name of person in front of you‬ ↑
‭ ‬E
‭ xam Location(building and classroom)‬ ‭Name of person behind you‬‭↑‬

‭ ill in the correct circles & squares completely…like this:‬‭

F ⬛
⬤‬‭(select ONE), and‬ ‭ ‬‭(select ALL that apply)‬
‭Print your student ID on top of every single page‬

‭Question‬ ‭1‬ ‭2‬ ‭3‬ ‭4‬ ‭5‬ ‭Total‬

‭Minutes‬ ‭16‬ ‭12‬ ‭12‬ ‭15‬ ‭15‬ ‭70‬

‭Max Points (151)‬ ‭18‬ ‭14‬ ‭11‬ ‭9‬ ‭10‬ ‭62‬

‭Max Points (251A)‬ ‭18‬ ‭14‬ ‭11‬ ‭9‬ ‭16‬ ‭68‬

‭Points‬

‭ o NOT proceed to the next page until you are instructed to do. Only fill out the upper part of the first‬
D
‭page.‬

‭1‬
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‭1) Logically Effortful‬‭(‬‭19 points, 16 minutes)‬

‭ aron believes that he can do a better job sizing digital circuits than Cadence tools. However, Haron is too‬
H
‭busy doing other things, so he has hired you to size his circuits instead.‬

‭ aron is using a process where an inverter sized for equal rise and fall times has a PMOS width twice that of‬
H
‭the NMOS. Assume gamma = 1 and that all gates are sized for equal worst-case rise and fall times.‬

‭a) (5 pts)‬‭Consider the logic chain shown below.‬

‭ rite an expression for the delay (normalized to t‬‭inv‬‭)‬‭of each stage in terms of the input and/or load‬
W
‭capacitances labeled in the diagram (C0, C1, …, CL). The labels above each gate indicate the input‬
‭capacitance of that gate.‬‭Fully simplify any fractions‬‭in your answer. Do not assume anything in‬
‭particular about the sizing of the gates.‬

‭ E(N-input NAND) = (N+2)/3; p(N-input NAND) = N*gamma = N (gamma = 1)‬

L
‭LE(N-input NOR) = (2*N+1)/3; p(N-input NOR) = N*gamma = N (gamma = 1)‬
‭d(i) = p(i) + le(i) * fo(i) * b(i)‬
‭There is a factor of t‬‭inv‬‭in front, but we’re asked‬‭to calculate the delay normalized to t‬‭inv‬‭, so we‬‭omit this factor.‬

‭d0 = 1 + C1/C0‬

‭d1 = 2 + 4/3 * C2/C1‬

‭d2 = 3 + 7*C3/C2‬

‭d3 = 1 + C4/C3‬

‭d4 = 3 + 5/3 * CL/C4‬

‭2‬
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‭b)‬‭(5 pts)‬‭Consider the logic chain shown below. Each‬‭gate is labeled with its input capacitance.‬

‭ alculate the relative sizes of all gates such that the total path delay is minimized. Simplify your answers. Be‬
C
‭sure to enter your answers in the correct order!‬

‭ E = 1 * 4/3 * 1 * 4/3 * 1‬
L
‭B = 4 * 1 * 8 * 1 * 1‬
‭F = CL / C1 = 18‬
‭H = LE * B * F = 1024 = 4^5‬
‭h = H^(⅕) = 4‬

l‭e(i) * b(i) * f(i) = h = 4‬

‭1 * 1 * CL/C5 = 4, so C5 = 18/4*C1 = 9/2*C1‬
‭4/3 * 1 * C5/C4 = 4, so C4 = 3/2*C1‬
‭1 * 8 * C4/C3 = 4, so C3 = 3*C1‬
‭4/3 * 1 * C3/C2 = 4, so C2 = 1*C1‬

‭ 2/C1 = 1‬
C
‭C3/C1 = 3‬
‭C4/C1 = 3/2‬
‭C5/C1 = 9/2‬

‭Space for scratch work (only your answers in the blanks will be graded):‬

‭3‬
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‭c)‬‭(4 pts)‬‭Consider the chain of inverters shown below.‬

‭ ou need to insert a NOR2 gate somewhere in this chain. Assume that when you insert the NOR2 gate, you‬
Y
‭re-size all the gates for minimum delay. The first gate in the chain will always have an input capacitance Cin=1‬
‭unit, regardless of whether it is an inverter or a NOR2 gate.‬

‭ here should you insert the NOR2 gate for minimum delay? If all options result in the same delay, select‬
W
‭“Does not matter”. (Circle one)‬

‭Before C1 After C1 After C2 After C3 After C4‬ ‭Does not matter‬

‭Briefly justify your answer (2 sentences max):‬

I‭f the gates are optimally sized, the total delay will be 5 * H^(⅕)) + 4*1 + 2, where H = F * LE * B = CL/C1 *‬
‭(5/3).‬
‭So the delay is independent of where we place the NOR2 gate.‬

‭ here should you insert the NOR2 gate for minimum energy consumption? If all options result in the same‬
W
‭energy, select “Does not matter”. (Circle one)‬

‭Before C1‬ ‭After C1 After C2 After‬‭C3 After C4 Does not matter‬

‭Briefly justify your answer (2 sentences max):‬

‭ he logical effort of a NOR2 gate is larger than that of an inverter, so we want it to be sized as small as‬
T
‭possible (energy is proportional to capacitance). Thus, we should place it first in the chain.‬

‭4‬
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‭ )‬‭(5 pts)‬‭Consider the logic chain below. Assume‬‭gamma = 1.‬

d
‭Circuit 1‬‭:‬

‭ aúl looks at this circuit, and finds that it is logically equivalent to this logic chain:‬
R
‭Circuit 2‬‭:‬

‭ aúl wants to know if his seemingly simpler circuit is actually faster. Calculate the input-to-output delay of each‬
R
‭circuit as a function of CL, assuming all gates are optimally sized for each value of CL. Normalize your‬
‭answers to t‬‭inv‬‭.‬

‭ our answers should contain numeric constants and CL, but no other variables. Simplify all fractions where‬
Y
‭possible. You do not need to simplify roots; an answer like 4(16/3)‬‭⅓‬ ‭is acceptable.‬

‭D1 (delay of circuit 1) = 4*[16/9*CL]^(¼) + 6‬

‭D2 (delay of circuit 2) = 2*[20/9*CL]^(½) + 4‬

‭ ualitatively, for which regime is Raúl’s simplified circuit (Circuit 2) faster? Assume all gates are optimally sized‬
Q
‭for each value of CL. (circle one)‬

‭Small CL‬ ‭Large CL‬

‭5‬
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‭Space for scratch work (will not be graded).‬

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‭2) Wire Delays, Power, and Moore‬‭()‬

‭ ) (3 pts)‬‭At‬‭time = 0‬‭, a switch is shut connecting‬‭the RC network on the right to the voltage supply network on‬
a
‭the left.‬‭Vout is initially‬‭at‬‭K*VDD (where 0 < K‬‭< 1)‬‭. Now find the time required for‬‭Vout‬‭to reach‬‭Z*VDD‬
‭(where K < Z < 1).‬

‭Show work here:‬

‭𝑉𝐷𝐷‬−‭𝑉𝑜𝑢𝑡‬ ‭𝑑𝑉𝑜𝑢𝑡‬
‭𝑅‬
= ‭𝐶‬ ‭𝑑𝑡‬
‭𝑉𝐷𝐷‬−‭𝑉𝑜𝑢𝑡‬ ‭𝑑𝑉𝑜𝑢𝑡‬
‭𝑅𝐶‬
= ‭𝑑𝑡‬
‭𝑑𝑡‬ ‭𝑑𝑉𝑜𝑢𝑡‬
‭𝑅𝐶‬
= ‭𝑉𝐷𝐷‬−‭𝑉𝑜𝑢𝑡‬
‭𝑡‬ ‭𝑍𝑉𝐷𝐷‬
‭1‬ ‭𝑑𝑉𝑜𝑢𝑡‬
‭𝑅𝐶‬
∫ ‭1‬‭‭𝑑
‬ 𝑡‬‭‬ = ∫ ‭𝑉𝐷𝐷‬−‭𝑉𝑜𝑢𝑡‬ ‭‬
‭0‬ ‭𝐾𝑉𝐷𝐷‬
‭𝑡‬
‭𝑅𝐶‬
=− ‭𝑙𝑛‬(‭𝑉𝐷𝐷‬ − ‭𝑍𝑉𝐷𝐷‬) + ‭𝑙𝑛‬(‭𝑉𝐷𝐷‬ − ‭𝐾𝑉𝐷𝐷‬)
‭𝑉𝐷𝐷‬−‭𝐾𝑉𝐷𝐷‬
‭𝑡‬ = ‭𝑅𝐶𝑙𝑛‬( ‭𝑉𝐷𝐷‬−‭𝑍𝑉𝐷𝐷‬ )
‭1‬−‭𝐾‬
‭𝑡‬ = ‭𝑅𝐶𝑙𝑛‬( ‭1‬−‭𝑍‬ )

‭ ime Required to Reach VDD at Vout (Fill Below)‬

T
‭Reminder: Vout is initially at K*VDD‬

‭𝑉𝐷𝐷‬−‭𝐾𝑉𝐷𝐷‬
‭𝑡‬ = ‭𝑅𝐶𝑙𝑛‬( ‭𝑉𝐷𝐷‬−‭𝑍𝑉𝐷𝐷‬ )
‭1‬−‭𝐾‬
‭𝑡‬ = ‭𝑅𝐶𝑙𝑛‬( ‭1‬−‭𝑍‬ )

‭ ) (3 pts)‬‭Sir Topham Hatt is working on a chip designed‬‭for locomotive applications. He observes the‬
b
‭following current draw‬‭on his chip over the span of‬‭12 seconds. Assume a VDD of‬‭5 V.‬‭Fill in the table‬‭below.‬

‭Show work here:‬

‭Instantaneous Power @ 6 Seconds (Fill Below):‬

‭5A*5V = 25 W.‬

‭7‬
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‭Figure 1:‬‭Current drawn by the chip over time.‬ ‭Average Power @ 12 Seconds (Fill Below):‬

‭34/12*5 =14.2 W.‬

‭ ) (4 pts)‬‭Oski Bear is designing a large cell, called‬‭Golden Gate, shown below. Find the activity factors at its‬
c
‭two outputs. Inputs‬‭A, B, C‬‭are‬‭1‬‭with probability‬‭PA, PB, PC‬‭.‬

‭ how work here:‬

S
‭Probability of 1 post -inverter is ½.‬
‭Probability of 1 post-or is ¾.‬
‭Probability of 1 post-or-out2 is ⅜.‬
‭Thus ⅜*⅝=15/64‬

‭Activity Factor at Out 1:‬

‭0‬

‭Activity Factor at Out 2:‬‭15/64‬

‭ ) (4 pts)‬‭Big Bird has helped to design a new wireline‬‭network for Sesame Street’s digital ASIC department.‬
b
‭Fill in the table below.‬

‭Critical Assumptions:‬
‭●‬ ‭VCTRL is currently set to‬‭HIGH.‬
‭●‬ ‭The propagation delay will be defined for a‬‭50% switch‬‭point.‬
‭●‬ ‭You may ignore all capacitances except those shown.‬
‭●‬ ‭NFET on-resistance is‬‭2R‬‭, PFET on-resistance is‬‭4R‬‭.‬‭Any transistor‬‭that is not on‬‭has‬‭infinite‬
‭resistance.‬

‭8‬
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‭ how work here:‬

S
‭Stage 1 RC : 2R*2C = 4RC‬
‭Stage 2 RC = (2R+R)*(4C + C) = 15C‬
‭Stage 3 RC = (2R+R+3R)*C = 6RC‬

‭Delay (Expressed in RC):‬

‭ln(2)*(25RC)‬

‭ ) (6 pts)‬
c
‭FOR 251A ONLY! 151A STUDENTS WILL NOT RECEIVE CREDIT FOR THIS PROBLEM.‬

‭ ski Bear is also working part-time at RISC-Y, where he has developed the Sather Gate. It is a special form of‬
O
‭inverter implementing‬‭hysteresis‬‭. Its input and output‬‭characteristics and circuit symbol are shown below.‬

‭9‬
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‭ igure 2:‬‭In-out characteristics. Arrows denote the‬

F ‭Figure 2:‬‭Circuit Symbol‬
‭gate’s behavior for a certain transition. The highest‬
‭input voltage‬‭that can be reached is the supply‬
‭voltage of Sather Gate. Likewise for its outputs.‬

‭This gate is to be integrated as part of a chip, shown below.‬

‭Critical Assumptions:‬
‭●‬ ‭Sather Gate‬‭has‬‭infinite resistance‬‭when looking in‬‭from the supply port. This is true for‬‭all modes‬‭of‬
‭operation‬‭. That is to say, it never loads the power‬‭supply network.‬
‭●‬ ‭R1‬‭=‬‭0.25 ohms, R2 = 1 ohm.‬
‭●‬ ‭Digital core and IO behave like ideal current sources. IO draws‬‭1A‬‭. Digital core draws‬‭3A.‬
‭●‬ ‭There is‬‭ground bounce‬‭occurring from some unknown‬‭inductance. Hence the ground of the‬‭left‬
‭Sather Gate is tied to‬‭2V‬‭.‬
‭●‬ ‭Note that at‬‭t<0‬‭,‬‭Voltage A is initially at 2V,‬‭and‬‭Voltage B‬‭is initially at‬‭12 V.‬
‭●‬ ‭Note that at‬‭t=0, VIN of 3V is applied.‬

‭10‬
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‭ how work here:‬

S
‭First figure out what supply voltage the left gate has:‬
‭At the junction between the two resistors, apply KCL. IO therefore draws‬‭1A‬‭, and digital core draws‬‭3A‬‭.‬
‭Therefore, R1 * (1+3) = 1 V. It follows that the drop across R2 is: R2 * 3 = 3 V. Sather gate does not load this‬
‭network. Therefore, the left gate’s supply is‬‭10 V‬‭- 1V - 3V = 6V‬

‭ ext realize that for the left gate:‬

N
‭Supply is between 2V and 6V. Since its output is initially at‬‭2V‬‭, we must follow the rising transition behavior.‬
‭The decision point is (6-2)/2 + 2 = 4V. Therefore,‬‭3V can trigger this. A is set to 6 V.‬

‭ or the right gate:‬

F
‭Since it is initially at‬‭12V‬‭, we must follow its falling‬‭transition behavior. The decision point is‬‭8V‬‭. That‬‭is to‬
‭say, A cannot cause B to fall. Therefore, B remains‬‭at 12V.‬

‭Voltage at A, when VIN = 3V is applied at t =0 (Fill Below):‬

‭6V‬

‭Voltage at B, when VIN = 3V is applied at t =0 (Fill Below):‬

‭12V‬

‭11‬
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‭3) CMOS logic(‬‭11 points, 12 minutes‬‭)‬

‭ ou got your first job in a hardware startup company as a CMOS design engineer, and your boss decided to‬
Y
‭use a technology node where a reference inverter has Wp = 1, Wn = 2 and γ(gamma)= 3.‬

‭ our coworker designed a complex CMOS logic gate, which is provided below. Your task is to make‬
Y
‭sure the input pins(A, B, C, D) are properly connected to achieve the following complex logic Y =‬
‭𝐴𝐶‬ + ‭𝐵𝐶‬ + ‭𝐴𝐵𝐷‬‭.‬

‭a)‬ ‭(3 pts)‬‭Fill in the signal connected to the gate of each transistor on the box below.‬

‭ ote: There are multiple combinations of answers(e.g. (4), (5), and (6) can be mixed up), and any‬
N
‭combination that implements the boolean logic Y = (AC+BC+ABD)’ would be considered correct.‬

‭12‬
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‭b)‬ (‭ 3 pts)‬‭In this technology, determine the width of each transistor(M1~M12) so that the gate size is‬
‭minimized and the gate has the same pull-up and pull-down strength as a reference inverter. Assume‬
‭Wi (i=1~12) is the width of transistor Mi (i=1~12).‬‭Your answer should be a single integer OR a fully‬
‭simplified fraction. That is, if the answer is 4/3, write “4/3”, neither “1.333” nor “8/6”‬‭.‬‭Assume‬
‭that W1 and W10 are fixed to 4 and 3, respectively.‬

‭c)‬ (‭ 5 pts)‬‭Your boss is satisfied with your work, and‬‭they now require you to analyze the CMOS logic gate‬
‭that has been designed by your coworker in this technology. The logic gate is provided below, with each‬
‭transistor’s width provided. Calculate the logical effort(le) of each input pin (A, B, C, D) and the‬
‭parasitic delay(p) of this gate.‬‭Your answer should‬‭be a single integer OR a fully simplified‬
‭fraction. That is, if the answer is 4/3, write “4/3”, neither “1.333” nor “8/6”‬‭.‬

‭13‬
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‭ ote that the given gate has a half of pull-up/pull-down resistance compared to the reference inverter,‬
N
‭which means that an inverter that has the same pull-up/pull-down resistance as the provided gate‬
‭would be‬‭Wp=2 and Wn=4‬‭.‬

‭Logical effort of A = 5/3‬

‭Logical effort of B = 2‬

‭Logical effort of C = 16/3‬

‭Logical effort of D = 10/3‬

‭Parasitic delay = 11‬

‭4)‬‭Toblerone Adder‬‭(14/18 points, 15 minutes)‬

‭ ana really likes carry-lookahead adders, and recently realized that “Kogge-Stone” kind of rhymes with‬
S
‭“Toble-rone”. Toblerone is incidentally her favorite type of chocolate, so she needs your help to design a brand‬
‭new Toblerone adder.‬

‭a)‬ (‭ 2 pts)‬‭The basic building block of most multi-bit‬‭adders and subtractors are single-bit full‬
‭adders. The simplest way we can compose multi-bit subtractors is by stringing them together‬
‭into a ripple-carry subtractor. How many single-bit full adders are needed to implement a 4-bit‬
‭two’s complement ripple-carry subtractor?‬

‭N =‬‭4‬

‭14‬
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‭b)‬ (‭ 2 pts)‬‭How does the worst case delay of a ripple-carry‬‭subtractor relate to the number of bits‬
‭N? Express your answer using big O notation.‬

‭T = O(_‬‭N‭_
‬ )‬

‭c)‬ (‭ 4 pts)‬‭Kogge-Stone adders are carry-lookahead adders,‬‭meaning they are based on propagate‬
‭and generate bits. Sana first wants to create a basic block that is just like a full adder, but‬
‭instead of taking in operands A and B it takes in P = A + B and G = AB. Find expressions for the‬
‭outputs S (sum) and Co (carry out) in terms of P, G, and Ci (carry in).‬

‭Co =‬ ‭G + P Ci‬ ‭S =‬‭GCi + !P Ci + P !G !C‬

‭d)‬ (‭ 6 pts)‬‭Since ripple-carry adders are fairly slow‬‭for wider word lengths, Sana now wants to‬
‭create a tree carry lookahead adder that groups bits into groups of 3. The first step is to create a‬
‭unit cell that computes the propagate and generate bits for a group of 3 bits.‬

‭ rite simplified sum-of-products expressions for P[2:0] and G[2:0] in terms of P0, P1, P2 (least‬
W
‭to most significant propagate bits), G0, G1, and G2 (least to most significant generate bits),‬
‭where P2:0 and G2:0 are the propagate and generate bits for the group, respectively.‬

‭P[2:0] = ____‬‭P0 * P1 * P2‬‭____ G[2:0] = ___‬‭G2‬‭+ P2 * (G1 + (P1 * G0))‬‭____‬

‭15‬
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‭e)‬ (‭ 251a only, 4 pts)‬‭Sana now wants to build a 16-bit tree adder out of his 3-bit toblerone groups.‬
‭He is only allowed to use three-bit carry-merge gates to accomplish this. Please fill in the‬
‭missing propagate terms in the expressions below:‬

‭P[15:0] =‬‭P[15:13] ̇ P[12:10] ̇ P[9:7] ̇ P[6:4]‬ ‭̇ P[3:1]‬ ‭̇ P[0]‬

‭P[14:0] =‬‭P[14:12] ̇ P[11:9] ̇ P[8:6] ̇ P[5:3]‬ ‭̇ P[2:0]‬

‭16‬
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‭17‬
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‭18‬