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Unit II
Instruction Set and
Assembly Language Programming of 8086:
Part 4
B.Tech, ETM,
II Year, II Semester
N.Ramakrishna
Dept. of Electronics and Telematics
GNITS, Hyderabad
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 1
Syllabus
Unit II
Instruction Set and
Assembly Language Programming of 8086:
• Instruction formats
• Addressing modes
• Instruction set
• Assembler directives
• Macros
• Simple programs involving logical, branch and
call instructions, sorting,
evaluating arithmetic expressions,
string manipulations.
Unconditional Jump
Part 1 Label
JMP AA Unconditional JMP
Part 2
Skipped part
Part 3
AA XXXX Next instruction
Format
JMP Operand ; No flags are affected
If SI = 0670H,
destination address is in 0670H and 0671H
IP replaced by value at these addresses.
Part 1
Label
Jcc ABC Conditional Jump
Part 2
NO
condition XXXX
Skipped part
YES
Part 3
ABC XXXX Next
instruction
Conditional Jump
Instructions
Mnemonic : Jcc
Meaning : Conditional Jump
Format : Jcc operand
Operation :
If condition is true jump to the address specified
by operand.
Otherwise the next instruction is executed.
Flags affected : None
JE, JNE, JB, JNB, JAE, and JNAE are used after a compare operation.
CMP SI, DI
JE SAME
(if SI = DI)
JC Carry CF=1
JO Overflow OF = 1
JS Sign SF = 1
CF = 0 or ZF = 0 CF = 1 or ZF = 1 CMP BX, CX
Surely Above Below OR Equal JA BXabove
BXabove (BX is above) is a symbolic location
SF = 0 and OF = 0 SF = 1 and OF = 0
(surely positive) (surely negative)
or (SF = 1 and OF = 1) or (SF = 0 and OF = 1)
(wrong answer negative!) (wrong answer positive!)
and ZF = 0 (not equal) or ZF = 1 (equal)
First Instruction
Call subroutine A
Next instruction
Return
Call subroutine A
Next instruction
RET (RETURN)
• Last instruction in subroutine returns control
to the main program.
• Value of IP or IP and CS from the stack
returned to their corresponding registers.
(this time (SP) (SP)+2 )
Operand
None
Disp16
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 38
Procedure - Example
In main program
CALL SQUARE ;
LOOP
Part 1
MOV CX, N
MORE: XXXX
Part 2
Part 3
LOOP MORE LOOP instruction
Next Instruction
Loop execution:
• Contents of CX decremented
• Checked to determine if CX = 0.
• If CX ≠ 0,
return to the instruction at the label
specified in the loop instruction.
• If CX = 0,
loop is complete and
the instruction following loop is executed.
General format :
LOOP r8 ; r8 is 8-bit signed value.
It is a 2 byte instruction.
Used for backward jump only.
Mov CX,04
BACK: MOV AL, [BX] ;
ADD AL , [SI] ;
MOV [DI], AL ;
INC BX ;
INC SI ;
INC DI ;
LOOP BACK ;
NOP instruction
• Takes up three clock cycles and does no processing.
• After this, it will execute the next instruction.
• Used to provide delays in between instructions.
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 46
Machine control instructions
ESC instruction
• Microprocessor does NOP or accesses a data
from memory for coprocessor.
• Passes the information to 8087 math processor.
• Six bits of ESC instruction provide the opcode
to coprocessor.
• When 8086 fetches instruction bytes,
co-processor also picks up these bytes and
puts in its queue.
• The co-processor will treat normal 8086 instructions
as NOP.
• Floating point instructions executed by 8087
and during this 8086 will be in WAIT.
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 47
Machine control instructions
LOCK instruction
• Prefix to an instruction.
• Makes sure that during execution of the instruction,
control of system bus is not taken
by other microprocessor.
• In multiprocessor systems, individual microprocessors
are connected together by a system bus.
• This is to share the common resources.
• Each processor will take control of this bus
only when it needs to use common resource.
LOCK instruction
• LOCK prefix will ensure that in the middle of an
instruction, system bus is not taken by other processors.
• This is achieved by hardware signal ‘LOCK’ available on
one of the CPU pin.
• This signal will be made active during this instruction
and it is used by the bus control logic to prevent others
from taking the bus.
• Once this instruction is completed,
lock signal becomes inactive and
other microprocessors can take the system bus.
WAIT instruction
• Takes 8086 to an idle condition.
• The CPU will not do any processing during this.
• It will continue to be in idle state until TEST pin of 8086
becomes low or an interrupt signal is received on INTR
or NMI.
• On valid interrupt, ISR is executed and
processor enters the idle state again.