You are on page 1of 52

Microprocessors and Microcontrollers

Unit II
Instruction Set and
Assembly Language Programming of 8086:
Part 4

B.Tech, ETM,
II Year, II Semester
N.Ramakrishna
Dept. of Electronics and Telematics
GNITS, Hyderabad
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 1
Syllabus
Unit II
Instruction Set and
Assembly Language Programming of 8086:
• Instruction formats
• Addressing modes
• Instruction set
• Assembler directives
• Macros
• Simple programs involving logical, branch and
call instructions, sorting,
evaluating arithmetic expressions,
string manipulations.

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 2


Instruction set of
8086 Microprocessor
Prepared By
Manish Singhal
Also from: Microprocessors and Interfacing
by Douglas V. Hall.
Microprocessors and Microcontrollers
by Lyla B.Das.
Adapted and Modified by
N.Ramakrishna
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 3
Branch group of instructions
Program Flow control instructions
Branch instructions provide a lot of convenience
to the programmer
to perform operations selectively, repetitively etc.

Branch group of instructions

Conditional Uncondi- Iteration Call Return


jumps tional instructions instructions instructions
jump

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 4


JUMP Instructions
JUMP instructions:
1. Jump location
in the same code segment  near jump
CS is the same, only IP value changes.
2. Jump location
in a different code segment  far jump
Both CS and IP values change.
3. Label of destination address followed by a colon
4. Jumping can be forward or backward
5. Unconditional jump : JMP Label
6. Conditional jump : based on the status flags
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 5
Unconditional JUMP

Unconditional Jump
Part 1 Label
JMP AA Unconditional JMP

Part 2
Skipped part

Part 3
AA XXXX Next instruction

Format
JMP Operand ; No flags are affected

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 6


Unconditional JUMP

Unconditional Jump Instruction


Near Jump or Far Jump or
Intra segment Jump Inter segment Jump
(Jump within the segment) (Jump to a different segment)
Is limited to the address within Permits jumps from one code
the current segment. It is achieved segment to another. It is
by adding displacement to IP
Operands achieved by modifying CS and IP
Short label (8 bits)
Near label (16 bits)
Far label (32 bits) Inter Segment Jump
Memptr16
Regptr16
memptr32 Inter Segment Jump
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 7
JUMP Instructions
Unconditional JUMP instructions:
Formats
1. JMP label
Label contains the displacement
Direct addressing mode
Example : JMP THERE
Displacement added to IP value
2. JMP reg16
Indirect addressing mode
Register contains the offset
Examples : JMP BX ; make IP = BX
JMP SI ; make IP = SI
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 8
JUMP Instructions
Unconditional JUMP instructions:
Format
3. JMP [reg16]
Double indirect jump
Register points to an address
which contains the jump location
Example : JMP [SI]

If SI = 0670H,
destination address is in 0670H and 0671H
IP replaced by value at these addresses.

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 9


JUMP Instructions
JUMP instructions - Types:
1. Near Jump
Destination 16-bit signed number
Range +/- 32 Kbytes
Displacement added to IP value

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 10


JUMP Instructions
JUMP instructions - Types :
2. Short Jump : Special case of near jump
Destination 8-bit signed number
Range – 128 or +127 bytes
Displacement added to IP value

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 11


JUMP Instructions
JUMP instructions - Types :
3. Far Jump :
Intersegment jump
Destination address in a different code segment
5-byte instruction

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 12


Unconditional JUMP
JUMP instructions – Example 3.8. SHORT directive:

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 13


Unconditional JUMP
JUMP instructions – Example 3.9a:

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 14


Conditional JUMP

Part 1
Label
Jcc ABC Conditional Jump
Part 2
NO
condition XXXX
Skipped part
YES

Part 3
ABC XXXX Next
instruction

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 15


Conditional JUMP

Conditional Jump instructions 2 bytes (?) long.


1-byte opcode followed by
1-byte signed displacement (range of –128 to +127).

Conditional Jump
Instructions

Jumps based on Jumps based on


a single flag more than one flag
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 16
Conditional JUMP

Mnemonic : Jcc
Meaning : Conditional Jump
Format : Jcc operand
Operation :
If condition is true jump to the address specified
by operand.
Otherwise the next instruction is executed.
Flags affected : None

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 17


JUMPs Based on a single flag
JZ r8 ;Jump if Zero flag set to 1 (Jump if result is zero)
JNZ r8 ;Jump if Not Zero (Z flag = 0 i.e. result is nonzero)
JS r8 ;Jump if Sign flag set to 1 (result is negative)
JNS r8 ;Jump if No Sign (result is positive)

JC r8 ;Jump if Carry flag set to 1 There is no jump


JNC r8 ;Jump if No Carry based on AC flag

JP r8 ;Jump if Parity flag set to 1 (Parity is even)


JNP r8 ;Jump if No Parity (Parity is odd)
JO r8 ;Jump if Overflow flag set to 1 (result is wrong)
JNO r8 ;Jump if No Overflow (result is correct)

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 18


JUMPs Based on a single flag

JZ r8 ; JE (Jump if Equal) also means same.

JNZ r8 ; JNE (Jump if Not Equal) also means same.

JC r8 ;JB (Jump if Below) and JNAE (Jump if Not Above or Equal)


also mean same.
JNC r8 ;JAE (Jump if Above or Equal) and JNB (Jump if Not Below
also mean same.
JZ, JNZ, JC and JNC used after arithmetic operation

JE, JNE, JB, JNB, JAE, and JNAE are used after a compare operation.

JP r8 ; JPE (Jump if Parity Even) also means same.

JNP r8 ; JPO (Jump if Parity Odd) also means same.

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 19


Examples for JE or JZ instruction

Ex. For forward jump (Only examples for JE given)

CMP SI, DI

JE SAME

Should be ADD CX, DX ;Executed if ZF = 0


<=127
bytes : (if SI not equal to DI)

SAME: SUB BX, AX ;Executed if ZF = 1

(if SI = DI)

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 20


Examples for JE or JZ instruction

Ex. For backward jump


BACK: SUB BX, AX ; executed if Z = 1
Should be : (if SI = DI)
<= 128 :
bytes
CMP SI, DI
JE BACK
ADD CX, DX ;executed if Z = 0
(if SI not equal to DI)

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 21


Conditional JUMP instructions
Mnemonic meaning condition

JA/JNBE Above/not below or equal CF= 0 or ZF= 0

JAE/JNB Above or Equal/not below CF= 0

JB/JNAE Below/not above nor equal CF=1

JBE/JNA Below or Equal/not above CF=1 or ZF=1

JC Carry CF=1

JCXZ CX register is Zero (CF or ZF) = 0

JE/JZ Equal/Zero ZF=1

JG/JNLE Greater/not less nor equal ((SF xor OF) or SF) = 0

JGE/JNL Greater or Equal/not less (SF xor OF) = 0

JL/JNGE Less/not greater nor equal (SF xor OF) = 1


April 28, 2022 MPMC-N.Ramakrishna
Unit II Part 4 22
Conditional JUMP instructions
Mnemonic meaning condition

JLE/JNG Less or Equal/not greater ((SF xor OF) or ZF) = 1

JNC Not Carry CF = 0

JNE/JNZ Not Equal/not zero ZF = 0

JNO Not overflow OF = 0

JNP/JPO Not parity/parity odd PF = 0

JNS Not sign SF = 0

JO Overflow OF = 1

JP/JPE Parity/parity even PF = 1

JS Sign SF = 1

April 28, 2022 MPMC-N.Ramakrishna


Unit II Part 4 23
Jumping beyond -128 to +127?

Requirement Then do this!


CMP SI, DI CMP SI, DI
JE SAME JNE NEXT
What if ADD CX, DX JMP SAME
>127
: NEXT: ADD CX, DX
bytes
: :
SAME: SUB BX, AX :
SAME: SUB BX, AX

Range for JMP (unconditional jump) can be +215 = + 32K

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 24


Terms used in comparison

• Above and Below used for comparing Unsigned numbers.


• Greater than and less than used with signed numbers.
• All Intel microprocessors use this convention.

95H is above 65H Unsigned comparison - True


95H is less than 65H Signed comparison - True
95H is negative, 65H is positive

65H is below 95H Unsigned comparison - True


65H is greater than 95H Signed comparison - True

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 25


JUMP on multiple flags

Conditional Jumps based on more than one flag are used


after a CMP (compare) instruction.
JBE or Jump if Below or Equal
JNA Jump if Not Above
Jump if No Jump if Ex.

CF = 1 or ZF = 1 CF = 0 and ZF = 0 CMP BX, CX

Below or Equal Surely Above JBE BX_BE

BX_BE (BE is Below or Equal) is a symbolic location

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 26


JUMP on multiple flags

JNBE or Jump if Not (Below or Equal)


JA Jump if Above

Jump if No Jump if Ex.

CF = 0 or ZF = 0 CF = 1 or ZF = 1 CMP BX, CX
Surely Above Below OR Equal JA BXabove
BXabove (BX is above) is a symbolic location

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 27


JUMP on multiple flags

JLE or Jump if Less than OR Equal


JNG Jump if Not Greater than
Jump if No Jump if
SF = 1 and OF = 0 SF = 0 and OF = 0
(surely negative) (surely positive)
OR (SF = 0 and OF = 1) OR (SF = 1 and OF = 1)
(wrong answer positive!) (wrong answer negative!)
OR ZF = 1 (equal) and ZF = 0 (not equal)

i.e. (SF xor OF =1) or ZF = 1 i.e. (SF xor OF = 0) and Z = 0


April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 28
JUMP on multiple flags

JNLE or Jump if Not (Less than OR Equal)


JG Jump if Greater than
Jump if No Jump if

SF = 0 and OF = 0 SF = 1 and OF = 0
(surely positive) (surely negative)
or (SF = 1 and OF = 1) or (SF = 0 and OF = 1)
(wrong answer negative!) (wrong answer positive!)
and ZF = 0 (not equal) or ZF = 1 (equal)

i.e. (SF xor OF = 0) and ZF = 0 i.e. (SF xor OF = 1) or ZF = 1

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 29


JUMP on multiple flags

JL or Jump if Less than


JNGE Jump if Not (Greater than OR Equal)
Jump if No Jump if
SF = 1 and OF = 0 S = 0 and OF = 0
(surely negative) (surely positive)
or (SF = 0 and OF = 1) or (SF = 1 and OF = 1)
(wrong answer positive!) (wrong answer negative!)

i.e. SF xor OF = 1 i.e. SF xor OF = 0


When SF = 1, result cannot When SF = 0, result can be 0
be 0
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 30
JUMP on multiple flags

JNL or Jump if Not Less than


JGE Jump if Greater than OR Equal
Jump if No Jump if
SF = 0 and OF = 0 SF = 1 and OF = 0
(surely positive) (surely negative)
or (SF = 1 and OF = 1) or (SF = 0 and OF = 1)
(wrong answer negative!) (wrong answer positive!)

i.e. SF xor OF = 0 i.e. SF xor OF = 1


When SF = 0, result can be 0 When SF = 1, result cannot
be 0
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 31
Subroutine & Subroutine Handling
Instructions
Main program
Subroutine A

First Instruction
Call subroutine A
Next instruction

Return
Call subroutine A
Next instruction

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 32


Subroutine & Subroutine Handling
Instructions
Subroutine
Special segment of program that can be called
for execution from any point in a program.
• An assembly language subroutine = “procedure”
• CALL instruction is inserted into the main program
to call subroutine.
• To branch to a subroutine
the value in the IP or CS and IP modified.

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 33


Subroutine & Subroutine Handling
Instructions
• After execution, return control to next instruction
that immediately follows the one called the subroutine
i.e., the original value of IP or CS and IP
must be preserved.
• Execution of CALL instruction causes the contents of IP
to be saved on the stack. (this time (SP)  (SP) -2 )
• A new 16-bit (near-proc, mem16, reg16 i.e., Intra
Segment) value which is specified by the instructions
operand is loaded into IP.
Examples: CALL SQUARE CALL 1234H
CALL BX CALL [BX]
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 34
Subroutine & Subroutine Handling
Instructions
Inter Segment
• At CALL instruction, CS and IP placed in a stack.
• New values are loaded in to CS and IP
given by the operand.
• After execution of procedure,
original CS, IP values brought back.
Far-proc, Memptr32
These two words (32 bits) are loaded directly into IP and CS
with execution at CALL instruction.
First 16 bits  IP
Next 16 bits  CS
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 35
CALL

Mnem- Meaning Format Operation Flags


onic Affected

CALL Subroutine CALL operand Execution continues from none


call the address of
the subroutine specified
by the operand.
Information required to
return back to the main
program such as IP and
CS are saved
on the stack.
Operand
Near-proc Far-proc
Memptr 16 Memptr 32
Regptr 16
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 36
RETURN

RET (RETURN)
• Last instruction in subroutine returns control
to the main program.
• Value of IP or IP and CS from the stack
returned to their corresponding registers.
(this time (SP)  (SP)+2 )

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 37


RETURN

Mnem Meaning Format Operation Flags


-onic Affected
RET Return RET or Return to the main None
RET operand program by restoring IP
(and CS for far-proc).
If operand is present,
it is added to the SP.
(to account for the
parameters passed to
the procedure)

Operand
None
Disp16
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 38
Procedure - Example

SQUARE PROC NEAR ;


MOV BL, AL ;
MUL BL ;
RET ;

In main program
CALL SQUARE ;

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 39


LOOP instructions

LOOP
Part 1
MOV CX, N
MORE: XXXX

Part 2

Part 3
LOOP MORE LOOP instruction
Next Instruction

LOOP  backward jump only


Format LOOP Label
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 40
LOOP instructions

• Used to repeat a set of instructions several times.


• Format: LOOP Short-Label
• Operation:
(CX)  (CX)-1
where CX = count ,
the number of times the loop is to be repeated.
• Jump is initialized to location defined by short label
if CX ≠ 0.
if CX = 0, execute next sequential instruction.

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 41


LOOP Instructions

Loop execution:
• Contents of CX decremented
• Checked to determine if CX = 0.
• If CX ≠ 0,
return to the instruction at the label
specified in the loop instruction.
• If CX = 0,
loop is complete and
the instruction following loop is executed.

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 42


LOOP instructions

General format :
LOOP r8 ; r8 is 8-bit signed value.
It is a 2 byte instruction.
Used for backward jump only.

• Maximum distance for backward jump is only 128 bytes.

• LOOP LABEL is almost same as: DEC CX


JNZ LABEL
• LOOP instruction does not affect any flags.

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 43


LOOP instructions

Mnemonic meaning format Operation

LOOP Loop Loop short-label (CX)  (CX) – 1


Jump to location given
by short-label if CX ≠ 0

LOOPE/ Loop while LOOPE/LOOPZ (CX)  (CX) – 1


LOOPZ equal/ Loop short-label Jump to location given
while zero by short-label
if CX ≠ 0 and ZF = 1
LOOPNE/ Loop while LOOPNE/LOOPNZ (CX)  (CX) – 1
LOOPNZ not equal/ short-label Jump to location given
Loop while by short-label
not zero if CX ≠ 0 and ZF = 0

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 44


LOOP Instruction - Example

Mov CX,04
BACK: MOV AL, [BX] ;
ADD AL , [SI] ;
MOV [DI], AL ;
INC BX ;
INC SI ;
INC DI ;
LOOP BACK ;

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 45


Machine control instructions
HLT instruction – HALT processing
• Causes the 8086 to stop fetching and executing
instructions.
• 8086 enters a halt state.
• To get processor out of Halt state
an interrupt signal on the INTR pin or
an interrupt signal on NMI pin or
a reset signal on the RESET input.

NOP instruction
• Takes up three clock cycles and does no processing.
• After this, it will execute the next instruction.
• Used to provide delays in between instructions.
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 46
Machine control instructions
ESC instruction
• Microprocessor does NOP or accesses a data
from memory for coprocessor.
• Passes the information to 8087 math processor.
• Six bits of ESC instruction provide the opcode
to coprocessor.
• When 8086 fetches instruction bytes,
co-processor also picks up these bytes and
puts in its queue.
• The co-processor will treat normal 8086 instructions
as NOP.
• Floating point instructions executed by 8087
and during this 8086 will be in WAIT.
April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 47
Machine control instructions

LOCK instruction
• Prefix to an instruction.
• Makes sure that during execution of the instruction,
control of system bus is not taken
by other microprocessor.
• In multiprocessor systems, individual microprocessors
are connected together by a system bus.
• This is to share the common resources.
• Each processor will take control of this bus
only when it needs to use common resource.

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 48


Machine control instructions

LOCK instruction
• LOCK prefix will ensure that in the middle of an
instruction, system bus is not taken by other processors.
• This is achieved by hardware signal ‘LOCK’ available on
one of the CPU pin.
• This signal will be made active during this instruction
and it is used by the bus control logic to prevent others
from taking the bus.
• Once this instruction is completed,
lock signal becomes inactive and
other microprocessors can take the system bus.

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 49


Machine control instructions

WAIT instruction
• Takes 8086 to an idle condition.
• The CPU will not do any processing during this.
• It will continue to be in idle state until TEST pin of 8086
becomes low or an interrupt signal is received on INTR
or NMI.
• On valid interrupt, ISR is executed and
processor enters the idle state again.

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 50


Text Books
TEXT BOOKS:
1. Advanced Microprocessors and Peripherals – A. K.
Ray and K.M. Bhurchandi, Tata-McGraw Hill, 2nd
edition 2006.
2. The 8051 Microcontoller and Embedded Systems
Using Assembly and C, Second Edition,
Muhammad Ali Mazidi, Janice Gillispie Mazidi,
Rolin D. McKinlay, Prentice Hall

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 51


References
REFERENCES:
1. The 8051 Microcontrollers, Architecture and programming and
Applications -K.Uma Rao, Andhe Pallavi, , Pearson, 2009.
2. Microcontrollers and application, Ajay. V. Deshmukh,
Tata-McGraw Hill, 2005
3. D. V. Hall, Microprocessors and Interfacing, Tata-McGraw
Hill, 2nd edition 2006.
4. Kenneth. J. Ayala, The 8051 microcontroller , 3rd edition,
Cengage learning, 2010
5. Microprocessors and Microcontrollers, Lyla B.Das, Pearson,
2012
6. The 8085 Microprocessor: Architecture, programming and
Interfacing – K. Uday Kumar, B.S. Umashankar, 2008, Pearson

April 28, 2022 MPMC-N.Ramakrishna Unit II Part 4 52

You might also like