A Report on

TOTAL THERMAL POWER DISSIPATION

PREDICTION USING REGRESSION
LEARNING MODEL
For

SUBJECT: DIGITAL LOGIC DESIGN

On
8th November 2023

Submitted By: Guided By:

Name: Srushti Patel Prof. Manish Patel
Semester: 3
Roll No. : 22bec124
 INDEX
Sr. Details Page No
No.
1 Objectives 5
2 Methodology 5
2.1 Verilog Code For Various Electronic Circuits 5
2.2 Estimation Of Total thermal Power Dissipated In Each Circuit 6

2.3 Procedure For Training The Data 7

3 Training All The Models And Selecting The One With Lowest RMSE 10

4 References 16

2
 LIST OF TABLE
Sr. Details Page No
No.
1 Training Data 8
2 Test Data 9

3
 LIST OF FIGURES
Sr. No. Details Page No
1 Input Window 11

2 Response Plot 12
3 Predicted V/S Actual Plot 13
4 Residuals Plot 13
5 Exporting The Model For Making Predictions For Test Data 14

6 Predicting The Power Values 14

7 Degree Of Correlation By Using Coefficent Of Determination (R- 18

Squared)

1. OBJECTIVES

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To develop a highly accurate regression learning model by generating Verilog report of different
combinational and sequential circuits for predicting total thermal power dissipation in
electronic circuits. This project aims to enhance the efficiency and reliability of thermal
management systems by leveraging advanced predictive modeling techniques, ultimately
optimizing the performance and longetivity of electronic device.

2. METHODOLOGY
2.1 VERILOG CODE FOR VARIOUS ELECTRONIC CIRCUITS

For this Verilog code for 50 different combinational/sequential circuits is written and compiled
successfully.

Electronic Circuits
1. Decoder 2x4
2. Half-adder
3. Full-adder
4. Mux 2x1
5. Mux 4x1
6. Mux 8x1
7. priority_encoder_4to2
8. Encoder-4x2
9. demux_1to4
10. decoder_3to8
11. sr_flip_flop
12. jk_flip_flop
13. d_flip_flop
14. t_flip_flop
15. up_counter_4bit
16. Master-slave flip-flop
17. synchronouscounter
18. AsyncCntrDFlipFlop
19. serial adder
20. ripple carry adder
21. carry lookahead adder
22. 4-bit bcd adder subtractor
23. 4x4 unsigned array multiplier
24. 4×4 Booth Multiplier
25. magnitude Comparator
26. 4-bit LFSR
27. 4-bit Parity Generator
28. 4-bit Universal Shift Register
29. Melay with Overlap
30. Moore with Overlap

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 31. FIFO BUFFER
32. LIFO BUFFER
33. arbitrary Counter
34. tristate_buffer
35. up_counter_with_enable
36. counter_decoder_combination1
37. counter_decoder_combination2
38. shift_register_parallel_serial
39. counter_7seg_decoder_combination
40. counter_mux_combination
41. binary_counter_mux_combination
42. binary_up_counter_mux_combination
43. binary to excess-3 converter
44. binary to gray
45. Booth multiplier
46. GRAY to BINARY
47. mod_counter_15
48. Encoder 8:3
49. RAM
50. Sequence Detector Moore

2.2 ESTIMATION OF TOTALTHERMAL POWER DISSIPATED IN EACH CIRCUIT

After this for each circuit we analyze its synthesis report which is generated after successfully
compiling each code. By analyzing the Synthesis report, we gain valuable insights about the
parameters and features that play a pivotal role in influencing the circuit’s dependencies and
characteristics.

Input features affecting the power present in resource section in the fitter properties which
contains 2 further sub-sections which are resource usage summary and partition statistics

1. Total logic elements

2. Total pins
3. Total fan-out
4. Input ports
5. Output ports

The following features are obtained by choosing the PowerPlay Power Analyzer tool in
Processing section at the top of workspace. It gives a summary of all different types of power
whether static or dynamic out of which we have selected the following:

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6. Core Static Thermal Power Dissipation
7. I/O Thermal Power Dissipation

It further consists of sub-section which gives information about current drawn by voltage
supplies which we have taken as our 8th input feature:

8. Total Current Drawn by Supply voltage

Following this initial phase, we transition into the second part of the project. Here, we
meticulously segregate the dataset into training and testing subsets, employing the powerful
regression learner within MATLAB. These data subsets are instrumental in facilitating the
precise training and rigorous testing of our predictive model, which is designed to forecast the
future total power dissipation with utmost accuracy.

2.2 IMPORTING THE DATA IN MATLAB

1. TRAINING DATA
2. TESTING DATA

Upon loading the Excel sheets, we proceed to the 'Apps' tab within the toolbar, where we
select the 'Regression Learner' tool. Subsequently, we initiate the process by clicking on 'New
Session' and opt to import the data directly from the workspace, streamlining the data
acquisition step.

Then a new session window will open up and in response select the output label or dependent
variable here it is total thermal power dissipated.

And in the predictors select the all the necessary features except for the circuit name.

Then in cross-validation select 5 folds so that the model is not going to overfit the data.

Then click on Start session.

Then train all the models and select the best one.

Table 1: TRAINING DATA

Circuit Total Tot Tot Inp Outp Total Total Core Static I/O Thermal
logic al al ut ut Current Thermal Thermal Power

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 Drawn
fan by Power Power
eleme pin por Dissipation(
- ports Supply Dissipation( Dissipation(
nts s ts mW)
out voltage( mW) mW)
mA)
Decoder 2x4 4 7 10 3 4 1.12 110.69 79.93 31.41
Half-adder 2 4 31 2 2 9.6 110.33 79.93 31.41
Full-adder 2 5 8 3 2 9.07 110.44 79.93 30.52
Mux 2x1 1 4 4 3 1 9.06 110.32 79.93 30.39
Mux 4x1 2 7 9 6 1 9.1 110.65 79.93 30.73
Mux 8x1 5 12 20 11 1 9.16 111.27 79.93 31.34
priority_encoder
_4to2 2 6 9 4 2 9.08 110.55 79.93 30.63
Encoder-4x2 2 6 7 4 2 9.08 110.55 79.93 30.63
demux_1to4 4 7 16 3 4 9.1 110.69 79.93 30.77
decoder_3to8 8 11 32 3 8 9.15 111.05 79.93 31.12
sr_flip_flop 1 4 3 3 1 9.06 110.32 79.93 30.39
jk_flip_flop 1 6 8 4 2 9.08 110.55 79.93 30.63
d_flip_flop 2 4 8 2 2 9.06 110.33 79.92 30.41
t_flip_flop 2 5 10 3 2 9.07 110.44 79.92 30.52
up_counter_4bit 4 6 28 2 4 9.08 110.56 79.92 30.64
Master-slave flip-
flop 1 5 12 3 2 9.07 110.44 79.92 30.52
synchronouscou
nter 5 6 28 2 4 9.08 110.59 79.93 30.67
AsyncCntrDFlipFl
op 1 5 6 3 2 9.07 110.44 79.92 30.52
serial adder 11 15 59 5 10 9.2 111.67 79.93 31.75
ripple carry
adder 0 17 0 9 8 9.23 111.8 79.93 31.87
carry lookahead
adder 11 14 41 9 5 9.19 111.52 79.93 31.59
4-bit bcd adder
subtractor 10 13 38 8 5 9.17 111.41 79.93 31.49
4x4 unsigned
array multiplier 29 16 110 8 8 9.21 111.75 79.93 31.82
4×4 Booth
Multiplier 55 16 190 8 8 9.21 111.75 79.93 31.82

3.

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 Table 2 : TEST DATA

The column consisting of circuit name has been removes as it contains string data type which can’t
be given as input.

Total
Core Static
Current I/O Thermal
Thermal
Total logic Total fan- Input Output Drawn by Power
Total pins Power
elements out ports ports Supply Dissipation
Dissipation
voltage (mW)
(mW)
(mA)
102 22 528 12 10 9.29 79.93 32.53
106 22 533 12 10 9.29 79.93 32.53
9 5 40 2 3 9.07 79.92 30.53
0 3 2 2 1 9.04 79.92 30.22
5 7 33 3 4 9.08 79.93 30.79
6 7 22 1 6 9.1 79.93 30.74
20 21 103 1 20 9.28 79.93 32.37
4 11 29 7 4 9.15 79.93 31.24
9 12 40 1 11 9.16 79.93 31.31
3 7 19 1 6 9.1 79.93 30.74
4 8 30 2 6 9.11 79.93 30.86
4 8 30 2 6 9.11 79.93 30.86
2 6 9 3 3 9.08 79.92 30.64
2 6 7 3 3 9.08 79.92 30.64
93 16 305 8 8 9.21 79.93 31.79
3 8 13 4 4 9.11 79.93 30.88
5 6 28 2 4 9.08 79.93 30.67
3 11 15 8 3 9.15 79.93 31.21
137 16 490 12 4 9.17 79.93 31.41
11 4 57 3 1 9.06 79.93 30.41

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2.3 Procedure for TRAINING THE DATA
Features selected:

1. Total logic elements

2. Total pins
3. Total fan-out
4. Input ports
5. Output ports
6. Total Current Drawn by Supply voltage
7. Core Static Thermal Power Dissipation
8. I/O Thermal Power Dissipation
9. Labels/Target Variable : Total Thermal Power Dissipation

Figure 1 : Input Window

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3. TRAINING ALL THE MODELS AND SELECTING THE ONE WITH LOWEST RMSE

Gaussian process regression model has the highest accuracy as it has the lowest RMSE (Root Mean
Square Error) among all the models i.e. 0.12092 .

Figure 2: Response Plot

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Figure 3 : Predicted V/S Actual Plot

Figure 4 : Residuals Plot

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Figure 5 : Exporting The Model For Making Predictions For Test Data

Figure 6 : Predicting The Power Values

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T=readtable('test_data.xlsx');
yfit = trainedModel.predictFcn(T)
yfit =

111.5886
111.5836
110.4671
110.2835
110.6829
110.6995
111.6887
111.1349
111.2155
110.6939
110.7889
110.7889
110.5340
110.5342
111.5802
110.7862
110.5900
111.1205
111.4515
110.4400

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Figure 7: Degree Of Correlation By Using Coefficent Of Determination (R-Squared)

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 4. REFERENCES

1. Daniela Sanchez Lopera, Lorenzo Servadei,RTL Delay Prediction Using Neural Networks. “2021
IEEE Systems Conference (NorCAS)”
2. "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System," IEEE Std /481-
1999,2000.
3. Daniela Sánchez Lopera , Lorenzo Servadei,( 29 August 2022) Early RTL delay prediction using
neural networks, Technical University of Munich, Germany.

4. YouTube link: Forecasting using MATLAB Regression Learner app

https://www.youtube.com/watch?v=FJnXP78wSIw.

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