ACKNOWLEDGEMENT

I take this opportunity to express my deepest gratitude and appreciation to all those
who have helped me directly or indirectly towards the successful completion of this
project.
I express my deep sense of gratitude and thanks to Dr.A.RAMASWAMY
REDDY, Principal, Malla Reddy Institute of Technology, for giving me this
opportunity to carry out project work at highly esteemed organization.
I express my gratitude to C.LAXMIKANTH REDDY, HOD, Department of
ECE, for his constant co-operation, support and for providing necessary facilities
throughout the B. Tech program.
I would like to express my sincere gratitude to my internal guide Mr. A
SREENIVASA RAO, Associate Professor, Department of ECE for his insightful
advice, motivating suggestions, invaluable guidance, help and support in successful
completion of this project.
Next I would like to express my gratitude to my parents, friends and all the faculty
of our department for their cooperation and keen interest throughout this project.

J.SADGUN REDDY (15RJ1A0445)

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 DECLARATION

I J.SADGUN REDDY (15RJ1A0445) student of Bachelor of Technology (ECE),

Malla Reddy Institute of Technology carried out major project on “LOW POWER 4-BIT
ALU USING FULL ADDER AND MUTLIPLEXER” under the esteemed guidance of
MR. A.SREENIVASA RAO Department of Electronics and Communication
Engineering. To the best of my knowledge and belief, this project bears no resemblance
with any report submitted to JNTU or any other university for the award of any degree.

Signature of the internal guide

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 CONTENTS
ABSTRACT vii

LIST OF FIGURES viii

LIST OF TABLES x

ABBERIVATIONS xi

S.No Chapter Page Number

1 INTRODUCTION 01
1.1 ARITHEMATIC LOGICAL UNIT(ALU) 03

1.1.1 SIGNALS 04

1.1.2 DATA 04

1.1.3 OPCODE 05

1.1.4 STATUS 05

1.1.5 CIRCUIT OPERATION 06

1.1.6 FUNCTION 07

2 DATE DIFFUSTION INPUT(GDI) 11

2.1 BASIC GDI FUNCTION 12

2.2 TRANSIENT ANALYSIS 13

2.3 DESIGN OF ARITHEMATIC LOGICAL UNIT 16

2.4 LITERATURE OVERVIEW 17

3 EXISTING METHODS 21

4 PROPOSED METHOD 24

5 SOFTWARES USED 28

5.1 DSCH 28

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 5.2 MICROWIND
31
5.3 EXAMPLES 40

6 RESULTS 47

6.1 RESULTS 47

7 CONCLUSION AND FUTURE SCOPE 48

7.1 CONCLUSION 48

7.2 FUTURE SCOPE 48

BIBLIOGRAPHY 49

APPENDIX A 49

APPENDIX B 51

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 ABSTRACT

Arithmetic logic unit (ALU) is an important part of microprocessor. In digital

processor logical and arithmetic operation executes using ALU. In this paper we describes
4-bit ALU using low power 10-transistor full adder (FA) and Gate diffusion input (GDI)
based multiplexer. By using FA and multiplexer, we have reduced power and delay of 4-
bit ALU as compare to existing design. All design were simulated using DSCH and
Microwind technology. Performance analyses were done with respect to power, delay and
power delay product.
Keywords—4-bit ALU, Gate diffusion input (GDI), Full Adder.

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 LIST OF FIGURES

FIGURE PAGE NUMBER

Fig:1.1 Block Diagram Of ALU 04

Fig:1.2 Basic ALU 04

Fig:1.3 Combinational Logic Circuit 06

Fig:2.1 GDI Basic Cell 12

Fig:2.2 Input Logic States 13

Fig:2.3 A Sample Not Gate 15

Fig:2.4 Logical Gates Using GDI Technology 15

Fig:2.5 GDI Vs CMOS 16

Fig:2.6 Schematic Of 1-Bit ALU Stage 17

Fig:3.1 4 Bit ALU Using CMOS Technology 21

Fig:3.2 4 Bit ALU Using CMOS Technology 22

Fig:3.3 2x1 Mux Using CMOS 22

Fig:3.4 Fulladder With AND, OR gates Using CMOS technique 23

Fig:3.5 1-BIT ALU Waveform Using CMOS Technique 23

Fig:4.1 1-Bit ALU 24

Fig:4.2 Proposed 4-Bit ALU 25

Fig:4.3 Proposed 1 Bit ALU Using GDI 26

Fig:4.4 10t Fulladder Using GDI 26

Fig:4.5 Wave Form For 1-Bit ALU Using GDI 26

Fig:5.1 Menu Of DSCH Software 28

Fig:5.2 Front Page Of Microwind Software 31

Fig:5.3 Minimum N+ And P+ Diffusion With R201 4λ 32

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Fig:5.4 Between Two P+ And N+ Diffusions R202 4λ 32

Fig:5.5 Extra N-Well After P+ Diffusion R203 6λ 33

Fig:5.6 6λ Between N+ Diffusion And N Well R204 33

Fig:5.7 16λ 2 Minimum Diffusion Area R210 34

Fig:5.8 2λ Polysilicon Width R301 34

Fig:5.9 Polysilicon Gate Diffusion R302 2λ 35

Fig:5.10 Extra Polysilicon Surrounding R303 Diffusion 3λ 35

Fig:5.11 Between Two Polysilicon Boxes 3λ R304 36

Fig:5.12 4 λ Diffusion After Polysilicon R307 36

Fig:5.13 2λ Contact Width R401 37

Fig:5.14 1λ Extra Poly Surrounding Contact R404 37

Fig:5.15 1 Extra Metal Surrounding Contact R405 38

Fig:5.16 Extra Diffusion Surrounding Contact R403 1λ 38

Fig:5.17 Between Two Metal 4λ R501 39

Fig:5.18 Minimum Metal Area 16λ2 R510 39

Fig:5.19 Result Of Examples 46

Fig:6.1 1-Bit ALU 47

Fig:6.2 1-Bit Proposed ALU47

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 LIST OF TABLES

TABLE PAGE NUMBER

Table:1 TRUTH TABLE 05

Table:2 COMPARISION OPERATORS 08

Table:3 LOGICAL OPERATORS 08

Table:4 BINARY ARITHEMATIC OPERATORS 09

Table:5 UNARY ARITHEMATIC OPERATORS 09

Table:6 BITWISE OPERATORS 09

Table:7 SHIFT OPERATORS 10

Table:8 FOR 4-BIT ALU 27

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 ABBREVATIONS

ALU Arithmetic Logical Unit

GDI Date Diffusion Input

VLSI Very Large Scale Integration

CMOS Complementary Metal Oxide Semiconductor

DSP Digital Signal Processing

FA Full Adder

MUX Multiplexer

CPU Central Processing Unit

GPU Graphics Processing Unit

DSCH Digital Schematic

PTL Pass Transistor Technology

FS-GDI Full Swing Date Diffusion Input

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xii