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Multiplexer
Presented By :
J Sadgun Reddy (15RJ1A0445)
K Laxman (15RJ1A0460)
K Aravind (15RJ1A0459)
contents:
• ABSTRACT
• INTRODUCTION TO PROJECT
• DESIGN OF ALU
• GDI
• FULL ADDER
• 2X1
• 4X1
• 1BIT ALU
• ADVANTAGES AND DISADVANTAGES
• CONCLUSION
• FUTURE SCOPE
ABSTRACT
• In this we have designed low power 4-bit arithmetic logical unit using full
adder and GDI based multiplexer.
• By using full adder and multiplexer we have reduced power and delay of
4-bit ALU .
• All design were simulated using DSCH and MICROWIND technology.
• The performance analyses were done with respect to power , delay and
power delay product.
INTRODUCTION TO PROJECT
• An ALU is the fundamental unit used for all computing
system.
• We have designed an ALU to handle two inputs of 4-bits
each to produce a required output based on output selection
line.
• The possible outputs are NOR , XOR , OR , XNOR , AND ,
DECREMENT , ADD , SUB and INCREMENT.
DESIGN OF ALU
Disadvantages
• More complex
CONCLUSION
• The proposed ALU design in terms of power consumption and transistor count is
reduced.
• This work presents a 4-bit ALU designed in250nm technology for low power and
minimum area with GDI technique.
Future scope:
• The alu can be further enhanced with the design of control unit.
• More functionality can be implemented.
• Scan methods can also be implemented.