LAXmajortheory

15RJ1A0460 LOW POWER 4-BIT ALU USING FULLADDER
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1. INTRODUCTION:
Exploitation of very large scale integration (VLSI) technology has developed to

the point where millions of transistor can be implemented on a single chip.
Complementary metal oxide semiconductor (CMOS) has been the backbone in mixed
signal because it reducing power and providing good mix component for analog and
digital design.
The mainstays of power consumption in CMOS circuits are static power (Ps),
dynamic power (Pd) and short circuit power (Psc). Thus, the total power consumption
(Pt) is
Pt= Ps+ Pd + Psc ……………………………. (1)
Ps is caused by leakage current between the diffusion region and the substrate. Pd
consumes due to capacitive load and clock frequency and Psc is caused by short circuit
current. Increasing number of transistors per chip area and scale down technologies have
consumed more power thus the main objective is to reduce the power consumption by
using different techniques for improving performance of VLSI circuits.
ALU is the section of the computer processor that executes arithmetic and logical
operation. ALU is an exclusively combinational logic circuit which means output
changes with changing of input response. The ALU is a utile device in microprocessor,
performing various logical and arithmetic operations.
In our daily life, we use a lot of portable electronic devices; these devices
basically are low power high speed VLSI circuits works simultaneously. One of these
circuits is the Arithmetic logic unit (ALU) which considered an essential component in
many applications such as Microprocessor, digital signal processing, image processing,
etc. Addition considered essential part of the arithmetic unit and almost all other
arithmetic operations includes addition therefore any improvement in the adder cell is
reflected as a major improvement in the ALU. In this paper a 4-Bit ALU is designed
using a low power adder cell realized by the Full Swing GDI technique and compared to
previous work in terms of power dissipation and transistor count. Simulation
environment is cadence virtuoso using TSMC 65nm process. This paper is organized as
follows: Section II overviews the GDI methodology and presents its benefits and
limitations. The design of the arithmetic logic unit is discussed in Section III. Section IV
presents simulation results and comparison. In VLSI, such as DSP and microprocessors,
logic gates and arithmetic circuits are very much used.In that most commonly used
DEPARTMENT OF ECE 1 MRIT

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operations of these circuits are AND, OR, addition, subtraction and multiplication. In
arithmetic circuits, the building block of all digital circuits are Logic gates also full adder
cell is the extensively used in it. Recently in mobile communication and computation,
building low-power systems has emerged as highly in demand because of the fast
growing technology. As these is the era of growing technology and scaling of devices up
to nanometer regime, the Arithmetic and Logic circuits are to be designed with less
power, compact size and propagation delay. In any digital system a processor is an
important part. An ALU is one of the main components of a microprocessor. Basically
ALU is a combinational circuit that performs arithmetic and logical operations on a pair
of n bit operands. The arithmetic logic circuits are to be designed with compact size, less
power and propagation delay. CMOS uses both PMOS and NMOS transistors. CMOS
design gives high power dissipation, and high delay. Cell can be design with less power
consumption, less area and can be faster as compared to CMOS techniques by using GDI
technique cell. In GDI cell using only two transistors allows implementation of a wide
range of complex logic functions.GDI method is suitable for design of fast, low power
circuits, using reduced number of transistors as compared to CMOS, while improving
power characteristics and allowing simple Shannon’s theorem-based design by using
small cell library. The aim of this work is to examine a typically in order to explain and
interpret the GDI technique and compared with CMOS technique. This paper
demonstrates the concept of GDI technique for design of ALU. In this paper ALU is
designed by using GDI technique. Vaijayanti Panse et.al [1] He proposed the work
“Minimization of Transistors Count for 2:1 MUX using GDI Technique” .GDI technique
is used to reduce the number of transistors compared to conventional CMOS design. The
designs are implemented using 90nm cmos process in Microwind3.1v and DSCH3 and
their respective simulation results. Biswarup Mukherjee et.al [2] He proposed work
“Design & Study of a Low Power High Speed Full Adder Using GDI Multiplexer”. He
proposed a new method for implementing a low power full adder by means of a set of
Gate Diffusion Input (GDI) cell based multiplexers. Simulated outcome using state- of-
art simulation tool shows finer behavioral performance of the projected method over
general CMOS based full adder. Here conventional FA & proposed 12-T full adder
circuits are analyzed in standard simulator using 250 nm technologies. Amanpreet Kaur,
[3] he proposed work “Comparative Analysis of GDI based D Flip Flop Circuits using
90nm and 180nm Technology “. He proposed D flip flop design topologies has been
developed and analyzed. The evaluation is carried out by tanner tool with 180 nm & 90

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nm technology. Performance comparison is presented with respect to number of

transistors, power dissipation and delay. Arkadiy Morgenshtein[4] He proposed work
“GDI (Gate Diffusion Input) - a new technique of low power digital circuit design. He
proposed this technique allows reducing power consumption, delay and area of digital
circuits, while maintaining low complexity of logic design. A prototype test chip of 8-bit
CLA Adder has been fabricated, based on GDI and CMOS cell libraries, showing up to
45% reduction in power-delay product in GDI. These are the previous work done. In this
paper 4 bit ALU is implemented in tanner at 22nm, at 32nm and at 45 nm. Number of
transistor is reduced and therefore Area is reduced.
1.1 ARITHMETIC LOGIC UNIT (ALU) :
Arithmetic Logic Unit The heart of every computer is an Arithmetic Logic Unit
(ALU). This is the part of the computer which performs arithmetic operations on
numbers, e.g. addition, subtraction, etc. In this lab you will use the Verilog language to
implement an ALU having 10 functions. Use of the case structure will make this job easy.
The ALU that you will build (see Figure 1) will perform 10 functions on 8-bit inputs (see
Table 1). Please make sure you use the same variable name as the ones used in this lab.
Don’t make your own. The ALU will generate an 8-bit result (result), a one bit carry (C),
and a one bit zero-bit (Z). To select which of the 10 functions to implement you will use
ALU CTL as the selection lines. ALU is a fundamental building block of a central
processing unit (CPU) in any computing system; reversible arithmetic unit has a high
power optimization on the offer. By using suitable control logic to one of the input
variables of parallel adder, various arithmetic operations can be realized.
An arithmetic logic unit (ALU) is a combinational digital electronic circuit that

performs arithmetic and bitwise operations on integer binary numbers. This is in contrast
to a floating-point unit (FPU), which operates on floating point numbers. An ALU is a
fundamental building block of many types of computing circuits, including the central
processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs). A
single CPU, FPU or GPU may contain multiple ALUs.
The inputs to an ALU are the data to be operated on, called operands, and a code
indicating the operation to be performed; the ALU's output is the result of the performed
operation. In many designs, the ALU also has status inputs or outputs, or both, which

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convey information about a previous operation or the current operation, respectively,

between the ALU and external status registers.
Fig:1.1 Block Diagram Of ALU
1.1.1 Signals:
An ALU has a variety of input and output nets, which are the electrical conductors used
to convey digital signals between the ALU and external circuitry. When an ALU is
operating, external circuits apply signals to the ALU inputs and, in response, the ALU
produces and conveys signals to external circuitry via its outputs.
1.1.2 Data:
A basic ALU has three parallel data buses consisting of two input operands (A and B)
and a result output (Y). Each data bus is a group of signals that conveys one binary
integer number. Typically, the A, B and Y bus widths (the number of signals comprising
each bus) are identical and match the native word size of the external circuitry.
Fig:1.2 Basic ALU

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1.1.3 Opcode:
The opcode input is a parallel bus that conveys to the ALU an operation selection code,
which is an enumerated value that specifies the desired arithmetic or logic operation to
be performed by the ALU. The opcode size (its bus width) determines the maximum
number of different operations the ALU can perform; for example, a four-bit opcode can
specify up to sixteen different ALU operations. Generally, an ALU opcode is not the
same as a machine language opcode, though in some cases it may be directly encoded as
a bit field within a machine language opcode.
1.1.4 Status:
Outputs:
The status outputs are various individual signals that convey supplemental information
about the result of the current ALU operation. General-purpose ALUs commonly have
status signals such as:
• Carry-out, which conveys the carry resulting from an addition operation, the
borrow resulting from a subtraction operation, or the overflow bit resulting from a
binary shift operation.
• Zero, which indicates all bits of Y are logic zero.
• Negative, which indicates the result of an arithmetic operation is negative.
• Overflow, which indicates the result of an arithmetic operation has exceeded the
numeric range of Y.
• Parity, which indicates whether an even or odd number of bits in Y are logic one.
Table:1 Truth Table

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Inputs:
The status inputs allow additional information to be made available to the ALU
when performing an operation. Typically, this is a single "carry-in" bit that is the stored
carry-out from a previous ALU operation.
1.1.5 Circuit Operation:
Fig:1.3 combinational logic circuit
The combinational logic circuitry of the 74181 integrated circuit, which is a

simple four-bit ALU
An ALU is a combinational logic circuit, meaning that its outputs will change
asynchronously in response to input changes. In normal operation, stable signals are
applied to all of the ALU inputs and, when enough time (known as the "propagation
delay") has passed for the signals to propagate through the ALU circuitry, the result of
the ALU operation appears at the ALU outputs. The external circuitry connected to the
ALU is responsible for ensuring the stability of ALU input signals throughout the
operation, and for allowing sufficient time for the signals to propagate through the ALU
before sampling the ALU result.
In general, external circuitry controls an ALU by applying signals to its inputs.

Typically, the external circuitry employs sequential logic to control the ALU operation,
which is paced by a clock signal of a sufficiently low frequency to ensure enough time
for the ALU outputs to settle under worst-case conditions.
For example, a CPU begins an ALU addition operation by routing operands from
their sources (which are usually registers) to the ALU's operand inputs, while the control

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unit simultaneously applies a value to the ALU's opcode input, configuring it to perform
addition. At the same time, the CPU also routes the ALU result output to a destination
register that will receive the sum. The ALU's input signals, which are held stable until
the next clock, are allowed to propagate through the ALU and to the destination register
while the CPU waits for the next clock. When the next clock arrives, the destination
register stores the ALU result and, since the ALU operation has completed, the ALU
inputs may be set up for the next ALU operation.
An ALU is one of the main components of a microprocessor.ALU also contribute

to one of the highest power- density locations on the processor, as it is clocked at the
highest speed and is busy mostly all the time which results in thermal hotspots and sharp
temperature gradients within the execution core. Therefore, this motivate us strongly for
a energyefficient ALU designs that satisfy the high- performance requirements, while
reducing peak and average power dissipation. Basically ALU is a combinational circuit
that performs arithmetic and logical operations on a pair of n bit operands. Arithmetic
Unit Employing fast and efficient adders in arithmetic logic unit will aid in the design of
low power high performance system. In this paper Arithmetic Unit consists of adder and
substractor and logical unit consists of AND, OR.
1.1.6 Functions:
A number of basic arithmetic and bitwise logic functions are commonly supported by
ALUs. Basic, general purpose ALUs typically include these operations in their
repertoires
Verilog
Parameters
Parameters are constants and not variables:
parameter num = 8;
Operators
?:Construct
assign y = sel?a:b;
if sel is true, then y is assigned to a, else it is assigned b.

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Concatenation
In Verilog it is possible to concatenate bits using { }:
{a, b, c, a, b, c} is equivalent to: {2{a, b, c}}
Comparison Operators
assign y = a>b?a:b;
assign y if a > b and assign it to b otherwise.
Table 2 shows a list of comparison operators.
Table 2: Comparison Operators
Operator Description
> Greater than
< Less than
>= Greater than or equal to
<= Less than or equal to
== Equality
=== Equality including x and z
!= Inequality
!== Inequality including x and z
Logical Operators
Table 3: Logical Operators
! Logical negation
&& Logical AND
|| Logical OR
A number of basic arithmetic and bitwise logic functions are commonly
supported by ALUs. Basic, general purpose ALUs typically include these operations in
their repertoires

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Binary Arithmetic Operators
Table 4: Binary Arithmetic Operators
+ Addition
– Subtraction
* Multiplication
/ Division (truncates any fractional part)
% equality
Unary Arithmetic Operators
Table 5: Unary Arithmetic Operators
- Change the sign of the operand
Bitwise Operators
Table 6: Bitwise Operators
~ Bitwise negation
& Bitwise AND
| Bitwise OR
~& Bitwise NAND
~| Bitwise NOR
~^ or ^~ (equivalent)
A number of basic arithmetic and bitwise logic functions are commonly

supported by ALUs. Basic, general purpose ALUs typically include these operations in
their repertoires

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Shift Operators
Table 7: Shift Operators
<< Left shift
>> Right shift
• Left operand is shifted by the number of bit positions given by the right operand
• Zeros are used to fill vacated bit positions.

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2.GATE-DIFFUSIO N I NP UT (GDI ):
A new technique of low-power digital combinatorial circuit design is described.

This technique allows reducing power consumption, propagation delay, and area of
digital circuits while maintaining low complexity of logic design. Performance
comparison with traditional CMOS and various pass-transistor logic design techniques is
presented. The different methods are compared with respect to the layout area, number of
devices, delay, and power dissipation. Issues like technology compatibility, top-down
design, and pre-computing synthesis are discussed, showing advantages and drawbacks
of GDI compared to other methods. There are three inputs in a GDI cell - G (common
gate input of NMOS and PMOS), P (input to the source/drain of PMOS) and N (input to
the source/drain of NMOS).Bulks of both NMOS and PMOS are connected to N and P
respectively. Table 1.1 shows different logic functions implemented by GDI logic based
on different input values. So, various logic functions can be implemented with less
power and high speed with GDI technique as compared to conventional CMOS design.
It can be seen that large number of functions can be implemented using the basic
GDI cell. MUX design is the most complex design which requires 8-12 transistors with
the traditional CMOS, that can be implemented with GDI, which requires only 2
transistors. Many functions can be implemented efficiently by GDI with minimum
number of transistor. Function1 and Function2 are universal set for GDI, and consists of
only two transistors, compared to NAND and NOR. When compared to CMOS, the GDI
Technique use less transistors and power dissipation is also less. A new technique of low
power digital circuit design is a GDI (Gate Diffusion Input). Power consumption, delay
and area of digital circuits is reduced by This technique, maintains low complexity of
logic design. Since GDI cell has no power supply connected to it, there will be a voltage
drop at the output. This drop will be negligible for small circuits. Implementations of
GDI circuits in SOI or twin-well CMOS processes are expected to supply more power-
delay efficient design, due to the use of a complete cell library with reduced transistor
count. Because of less number of transistors, the switching is reduced and hence there
will be a less power, delay and also reduced area. Because of the less number of
transistors the switching node capacitance will be reduced that results in reduction of
dynamic power.

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Rapid development ofportable digital applications, thedemand for increasing spee

d, compactimplementation, and low power dissipation triggers numerous research
efforts. The wish to improve the performance of logic circuits, once based on traditional
CMOS technology, resulted in the
Development of many logic design techniques during the last two decades.
One form of logic that is popular in low-power digital circuits is pass-transistor logic
(PTL).Formal methods for deriving pass-transistor logic have been presented for nMOS.
They are based on the model, where a set of control signals is applied to the gates of
nMOS transistors. Another set of data signals are applied to the sources of the n-
transistors. Many PTL circuit implementations have been proposed in the literature.
Some of the main advantages of PTL over standard. CMOS design are:
1) High speed, due to the small node capacitances;
2) Low power dissipation, as a result of the reduced number of transisistors.
3) Lower interconnection effects, due to a small area.
2.1 BASIC GDI FUNCTIONS
Fig: 2.1 GDI basic cell.
The GDI method is based on the use of a simple cell as shown in Fig. 1. At first
glance, the basic cellreminds one of the standard CMOS inverter, but there are some

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important differences.1) The GDI cell contains three inputs: G(common gate input of
nMOS and pMOS), P(input to the source/drain of pMOS), and N (input to the
source/drain of nMOS).2) Bulks of both nMOS and pMOS are connected to N orP
(respectively), so it can bear bitrarily biased at contrast with a CMOS inverter. Most of
the designed circuits were based on theF1 and F2 functions. The reasons for this are
asfollows.1) Both F1 and F2 are complete logic families (allows realization of any
possible two-input logic function).2) F1 is the only GDI function that can be realized in a
standard p-well CMOS process, because the bulk of any nMOS is constantly and equally
biased.3) When N input is driven at high logic level and P input is at low logic level, the
diodes between NMOS and PMOS bulks to Out are directly polarized and there is ashort
between N and P, resulting in static power dissipation and V ou t ~0.5V DD .
2.2 Transient Analysis

The exact transient analysis for a basic GDI cell, in most cases, is similar to a
standard CMOS inverter, widely presented in the literature. This classic analysis is
based on the Shockley model
,where the drain current is expressed as follows.
INPUT LOGIC STATES VERSUS FUNCTIONALITY AND OUTPUT SWING OF F1

FUNCTION:
. Fig:2.2 Input Logic States

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Without a swing drop from the previous stages, a GDI cell functions as an
inverter buffer and recovers the voltage swing. Although this feature allows a self-swing
restoration in certain cases, in this paper the worst case is assumed and additional
circuitry is used for swing restoration in the implemented circuits.
The performance of a digital circuit is judged by its speed in producing output
when an input is given to it. The most common technology for designing digital circuits
is the CMOS technology. After the development of CMOS logic, there was increasing
need to optimize circuit in terms of speed. One technique thought of was by using Pass
Transistor Technology (PTL) which makes use of lesser number of gates to realize an
operation. The Transmission Gate (TG) is one of them which is typically a combination
of NMOS and PMOS transistors connected in parallel. The GDI cell represents another
form of pass transistor technology which looks similar to CMOS but differs in the supply
provided to the input terminals. The main advantages of PTL over conventional CMOS
design are as follows1) Lesser number of transistors results in low power dissipation and
lesser delay. 2) Lesser number of transistors so smaller area and lesser interconnect
effects. However, PTL technologies also suffers from two main problems such as
reduced circuit speed at low power operations and greater static power dissipation. The
paper presents a design technique that is the GDI technique that can be used to design
fast, low power circuits using only a few transistors. II. Gate Diffusion Input The GDI
cell is similar to a CMOS inverter structure. In a CMOS inverter the source of the PMOS
is connected to VDD and the source of NMOS is grounded. But in a GDI cell this might
not necessarily occur. There are some important differences between the two. The three
inputs in GDI are namely1) G- common inputs to the gate of NMOS and PMOS 2) N-
input to the source/drain of NMOS 3) P- input to the source/drain of PMOS Bulks of
both NMOS and PMOS are connected to N or P (respectively), that is it can be
arbitrarily biased unlike in CMOS inverter. Moreover, the most important difference
between CMOS and GDI is that in GDI N, P and G terminals could be given a supply
‘VDD’ or can be grounded or can be supplied with input signal depending upon the
circuit to be designed and hence effectively minimizing the number of transistors used in
case of most logic circuits (eg. AND, OR, XOR, MUX, etc). As the allotment of supply
and ground to PMOS and NMOS is not fixed in case of GDI, therefore, problem of low
voltage swing arises in case of GDI which is a drawback and hence finds difficulty in
case of implementation of analog circuits. III. Operational analysis The most common

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problem with PTL technique is its low voltage swing. An extra buffer circuitry may be
used additionally to eliminate the problem of low swing and improve drivability. The
problem of low swing can be understood with the help of a random function.
Fig :2.3 A Simple NOT Gate
Fig:2.4 Logic Gates using GDI technology

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Fig:2.5 GDI vs CMOS
2.3 Design of Arithmetic Logic Unit
An ALU is a key component in the Central Processing Unit (CPU) of any

computer; even the simplest microprocessors contain one. It performs arithmetic
operations such as addition, subtraction, increment, decrement and logic operations such
as AND, OR, XOR and XNOR [6]. The proposed design of the 4-Bit ALU consists of 4
stages, each stage is an 1-Bit ALU realized using the previously discussed circuits as
follows: Each 1-Bit ALU stage consists of two 2x1 multiplexers, two 4x1 multiplexers
and one full adder cell, this design requires 48 transistors as depicted in Fig. 5. Any

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desired operation can be performed based on the selection line S0, S1, S2 code; Table II
summarizes the truth table of the proposed ALU.
The 4x1 multiplexer at the input responsible for the B input based on the values
of S0 and S1 selection lines it selects from logic 1, B, ‫ ܤ‬And logic 0 to perform the
Decrement, Addition, Subtraction and the Increment operations respectively, S2 chooses
between the arithmetic and the logic operations.
Fig:2.6 Schematic of 1-Bit ALU Stage
2.4 LITERATURE OVERVIEW:
[1] A. Morgenshtein, I. Shwartz, and A. Fish, “Gate Diffusion Input (GDI) logic in
standard CMOS Nanoscale process,” 2010 IEEE 26th Convention of Electrical and
Electronics Engineers in Israel, 2010.
In this paper CMOS compatible Gate Diffusion Input (GDI) design technique is
proposed. The GDI method enables the implementation of a wide range of complex logic
functions using only two transistors. This method is suitable for the design of low-power
logic gates, with a much smaller area than Static CMOS and existing PTL techniques. As
opposite to our originally proposed GDI logic, the modified GDI logic is fully
compatible for implementation in a standard CMOS process. Simulations of basic GDI
gates under process and temperature corners in 40nm CMOS process are shown and

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compared to similar CMOS gates. We show that while having the same delay, GDI gates
achieve leakage and active power reduction of up to 70% and 50%, respectively.
[2] A. Morgenshtein, A. Fish, and I. Wagner, “Gate-diffusion input (GDI): a power-

efficient method for digital combinatorial circuits,” IEEE Transactions on Very
Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst., vol. 10, no. 5, pp.
566–581, 2002
[3].A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, and A. Fish, "Full swing

gate diffusion input logic—Case-study of low-power CLA adder design,"
Integration, the VLSI Journal, vol. 47, no. 1, pp. 62–70, Jan. 2014.
Full Swing Gate Diffusion Input (FS-GDI) methodology is presented. The

proposed methodology is applied to a 40 nm Carry Look Ahead Adder (CLA). The CLA
is implemented mainly using GDI full-swing F1 and F2 gates, which are the counterparts
of standard CMOS NAND and NOR gates. A 16-bit GDI CLA was designed in a 40 nm
low power TSMC process. The CLA, implemented according to the proposed
methodology, presents full functionality and robustness under global and local process
variations at wide range of supply voltages. Simulation results show 2 area reduction, 5
improvement in dynamic energy dissipation and 4 decrease in leakage, with a slight
(24%) degradation in performance, when compared to the CMOS CLA. Advanced
design metrics of GDI cells, such as minimum energy point (MEP) operation and
minimum leakage vector (MLV), are discussed.
[4].M. Shoba, R. Nakkeeran, "GDI based full adders for energy efficient arithmetic
applications", Engineering Science and Technology, an International Journal, vol.
19, no. 1, pp. 485–496, Mar. 2016.
Addition is a vital arithmetic operation and acts as a building block for

synthesizing all other operations. A high-performance adder is one of the key
components in the design of application specific integrated circuits. In this paper, three
low power full adders are designed with full swing AND, OR and XOR gates to
alleviate threshold voltage problem which is commonly encountered in Gate Diffusion
Input (GDI) logic. This problem usually does not allow the full adder circuits to operate
without additional inverters. However, the three full adders are successfully realized
using full swing gates with the significant improvement in their performance. The

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performance of the proposed designs is compared with the other full adder designs,
namely CMOS, CPL, hybrid and GDI through SPICE simulations using 45 nm
technology models. Simulation results reveal that proposed designs have lower energy
consumption among all the conventional designs taken for comparison.
[5]. Chandra Srinivasan, “Arithmetic Logic Unit (ALU) Design Using

Reconfigurable CMOS Logic,” M.S. Thesis, Dept. of Electr. & Comput. Eng.,
Louisiana State Univ., Baton Rouge, LA, USA 2003.
Using the reconfigurable logic of multi-input floating gate MOSFETs, a 4-bit

ALU has been designed for 3V operation. The ALU can perform four arithmetic and four
logical operations. Multi-input floating gate (MIFG) transistors have been promising in
realizing increased functionality on a chip. A multi-input floating gate MOS transistor
accepts multiple inputs signals, calculates the weighted sum of all input signals and then
controls the ON and OFF states of the transistor. This enhances the transistor function to
more than just switching. This changes the way a logic function can be realized.
Implementing a design using multi-input floating gate MOSFETs brings about reduction
in transistor count and number of interconnections. The advantage of bringing down the
number of devices is that a design becomes area efficient and power consumption
reduces. There are several applications that stress on smaller chip area and reduced
power. Multi-input floating gate devices have their use in memories, analog and digital
circuits. In the present work we have shown successful implementation of multi-input
floating gate MOSFETs in ALU design. A comparison has been made between adders
using different design methods w.r.t transistor count. It is seen that our design,
implemented using multi-input floating gate MOSFETs, uses the least number of
transistors when compared to other designs. The design was fabricated using double
polysilicon standard CMOS process by MOSIS in 1.5µm technology. The experimental
waveforms and delay measurements have also been presented.
[6].G. Sree Reddy, K. V. Koteswara Rao,“32-Bit Arithmetic and Logic Unit Design
With Optimized Area and Less Power Consumption By Using GDI Technique”
International Journal of Research In Computer Applications and Robotics, Vol.3
Issue.4, pp. 51-66, April 2015.
The paper presents to design of 32-bit Arithmetic and Logic Unit by taking the
advantage of concept called Gate Diffusion Input Technique (GDI). Arithmetic and

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Logic Unit is the important block to design the embedded and microprocessors. The
Arithmetic Unit will do the arithmetic operations, as ADDITION and
SUBSTRACTION. The Logic unit will do the logic operations, as AND, OR, XOR and
XNOR by using the concept GDI technique. The simulation results were taken using the
Digital Schematic tool in 120nm technology. The optimized Area and Power is
calculated by using Micro Wind tool in 120 nm technology. The simulation results tells
that the design is more efficient compared with the CMOS logic, Pass transistor logic
and transmission gate logic with less area and power consumption.

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3.EXISTING METHOD:
we use a lot of portable electronic devices; these devices basically are low power
high speed VLSI circuits works simultaneously. One of these circuits is the Arithmetic
logic unit (ALU) which considered an essential component. In CMOS design it takes
more time and more power consumption. Main concept of GDI is that gate of PMOS and
NMOS is diffused. In these days in digital circuits design, for a digital circuit designer’s
a high speed, high throughput and small silicon area and also low- power consumption in
digital circuit is most essential things for a designers. GDI is such a technique that we
can use for design of low power digital circuits. And it is also a novel design method of a
low power digital circuit. In GDI cell using only two transistors allows implementation
of a wide range of complex logic functions. In GDI by using only two transistor (PMOS
AND NMOS) many function such as AND, OR, XOR and XNOR can be
implemented.GDI method is suitable for designing of fast, low power circuits, using
reduced number of transistor as compared to CMOS techniques and also improving
power characteristics. As compared to CMOS, fast, low power circuits can be designed
bu using gdi technique.This approach leads to reduction in power consumption,
propagation delay and area of digital circuits. while having low complexity of logic
design. An important feature of GDI cell is that the source of the PMOS in a GDI cell is
not connected to VDD and the source of the NMOS is not connected to GND. Source
terminal of Pmos is acting as one input, and Source of Nmos is acting as another input.
Therefore GDI cell gives two extra input pins for use which makes the GDI design more
flexible than CMOS design.
Fig :3.1 4bit ALU using cmos technique

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ALU can perform various logic operations like NOT, AND, OR, NAND, NOR,
XOR, XNOR etc. For these operations a special unit is made called as Logical Unit. This
Logic Unit performs all logic operations asked to perform. A MUX operated by select
lines, for which particular logic operation to perform, is used inside this logic block.
Fig:3.2 4 Bit ALU Using Cmos Technique
Fig:3.3 2x1 mux using cmos

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Fig:3.4 fulladder with AND ,OR gates using CMOS technique
Fig:3.5 1 bit alu waveform using CMOS technique

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4.PROPOSED METHOD:
The 4x1 multiplexer at the input responsible for the B input based on the values
of S0 and S1 selection lines it selects from logic 1, B, ‫ ܤ‬And logic 0 to perform the
Decrement, Addition, Subtraction and the Increment operations respectively, S2 chooses
between the arithmetic and the logic operations.
Fig:4.1 1-bit ALU
To realize the 4-Bit ALU four stages were used as shown in Fig. 6. While the
carry input of ALU0 connected to selection line S1 to obtain logic 1 which needed for
subtraction and increment operations, however the other values don’t affect the results of
the logic operations. The proposed 4-Bit ALU circuits were designed using 65nm TSMC
CMOS process, the size of PMOS is triple that of the NMOS transistor size to achieve
the best power and delay performance. The simulations were done using the SPECTRE
based Cadence Virtuoso simulator with a power supply of 1V. Using A=1100, B=0101
as tset inputs.
Among these designs the proposed ALU design outperforms in terms of power
consumption and transistor count. In respect of power consumption the proposed ALU

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operates at least values. Compared with the other designs the Transistor count is also
reduced.
Fig:4.2 proposed 4-bit ALU
Fig.4.2 shows the waveform of the proposed ALU, The results of the proposed
design compared with the 4-Bit ALU designs in [5], [6], [7] are shown in Table III.

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Fig:4.3 Proposed 1 bit alu using gdi
Fig:4.4 10t fulladder using GDI
Fig:4.5 Waveform for 1 bit alu using GDI

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Table 8: for ALU
S2 S1 S0 Operations
0 0 0 OR
0 0 1 XOR
0 1 0 XNOR
0 1 1 AND
1 0 0 DECREMENT
1 0 1 ADD
1 1 0 SUB
1 1 1 INCREMENT

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5.SOFTWARE TOOLS USED:
5.1 DSCH Software (Logic Schematic Editor and Digital Simulator)
DSCH2 is opened by double clicking its icon on desktop.
Window of DSCH2 will appear as follow.
Fig:5.1 Menu Of DSCH sofware

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File Menu
Edit Menu

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Insert Menu
View Menu
Simulate Menu

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Symbol Library
6.2 MICROWIND
Microwind is a tool for designing and simulating circuits at layout level.
MICROWIND WINDOW:
Fig:5.2 microwind window

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DESIGN RULES:
12λ Minimum width r101
12 λ Between wells r102
144 λ2 Minimum well Area r110
Fig:5.3 Minimum N+ and P+ diffusion width r201 4λ
Fig:5.4 Between two P+ and N+ diffusions r202 4λ

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Fig:5.5 Extra N-well after P+ diffusion r203 6λ
Fig:5.6 6 λ Between N+ diffusion and n-well r204

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Fig:5.7 16λ2 Minimum diffusion area r210
Fig:5.8 2λ Polysilicon Width r301

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Fig:5.9 Poly silicon gate on Diffusion r302 2λ
Fig:5.10 Extra Polysilicon surrounding r307 Diffusion 3λ

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Fig:5.11 Between two Polysilicon boxes 3λ r304
Fig:5.12 4λ Diffusion after Polysilicon r307

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Fig:5.13 2λ Contact width r401
Fig:5.14 1λ Extra Poly surrounding contact r404

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Fig:5.15 1λ Extra metal surrounding contact r405
Fig:5.16 Extra diffusion surrounding contact r403 1λ

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Fig:5.17 Between two Metals 4λ r501
Fig:5.18 Minimum Metal area 16λ2 r510

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5.3 EXAMPLES:
I- NMOS transistor
II- PMOS transistor
III-Inverter
EXAMPLE: NMOS

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EXAMPLE: PMOS

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EXAMPLE: INVERTER

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–Well

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Fig:5.19 result of examples

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6. RESULTS:
6.1 RESULT:
Fig:6.1 1-bit ALU
Fig:6.2 1-bit proposed ALU

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7.CONCLUSION AND FUTURE SCOPE
7.1 CONCLUSION:
This work presents a 4-Bit ALU designed in DSCH and Microwind CMOS
process . Simulation results showed an advantage of the proposed ALU design in terms
of power consumption and transistor count, while maintaining Full-Swing Operation.
The proposed design consists of 192 transistors and operates under 1V supply voltage.
Power consumption in CMOS circuit is classified in two categorize: static power
dissipation and dynamic power dissipation. In today’s CMOS circuit’s static power
dissipation is negligible thus not considered as compared to dynamic power dissipation.
Dynamic Power dissipation in a CMOS circuit is given by P = CLf VDD2. The power
supply is directly related to dynamic power. The numbers of power supply to ground
connections are reduced in GDI implementation which reduces the dynamic power
consumption. This work presents a 4-bit ALU designed in250nm technology for low
power and minimum area with GDI technique. Various topologies of multiplexer and full
adder implementation is studied and compared. The 2x1multiplexer, 4x1 multiplexer, 1-
bit full adder with 10- transistors designed using GDI technique is chosen for lowering
power consumption and minimum possible area. Power dissipation, propagation delay
and the number of transistors of ALU were compared using CMOS, n MOSPTL and
GDI techniques. GDI technique proved to have best result in terms of performance
characteristics among all the design techniques.
7.2 FUTURE SCOPE:
In future, Arithmetic based sub systems will consists of Shannon based adder
cell, high performance low power full adder, high speed counter using GDI technique
and Vedic multiplier designs. They can be used in the implementation of finite impulse
response filter design for DSP which are advantageous for low power applications. ASIC
design for low power digital filter with low latency and power gating can be carried out.
These arithmetic sub systems can be used in the implementation of arithmetic and logic
units and multiply and accumulate units for DSP processor which improves performance
of the system in different level of abstraction. The GDI based counter designs can be
improved by using clock swing techniques in flip- flops.

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8.BIBILOGRAPHY
APPENDEX A:
REFERENCES:
[1]. R. Shalem, E. John, and L.K.John, “A novel low-power energy recovery full adder
cell,” in Proc. Great Lakes Symp.VLSI,Feb. 1999, pp.380–383.
[2]. A.Sharma, R Singh and R. Mehra, “ Low Power TG Full Adder Design Using
CMOS Nano Technology,”
[3]. L.Bisdounis, D.Gouvetas and O.Koufopavlou, “A comparative study of CMOS

circuit design styles for low power high-speed VLSI circuits” Int. J. of Electronics,
Vol.84, No.6, pp 599-613,1998. Anu Gupta, Design Explorations of VLSI Arithmetic
Circuits, Ph.D. Thesis, BITS, Pilani, India, 2003.
[4]. Saradindu Panda, N. Mohan Kumar, C.K. Sarkar., “Transistor Count Optimization of
Conventional CMOS Full Adder &Optimization of Power and Delay of New
Implementation of 18Transistor Full Adder by Dual Threshold Node Design with
Submicron Channel Length" in Computers and Devices for Communication, 2009.
CODEC 2009. 4th International Conference on pp: I – 4
[5]. T. Vigneswaran, B. Mukundhan, and P. Subbarami Reddy," A Novel Low Power,

High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold
Loss Problem" in World Academy of Science, Engineering and Technology 132006 pp:
I-7.
[6]. T. Esther Rani, M. Asha Rani, Dr. Rameshwarrao, “AREA OPTIMIZED LOW
POWER ARITHMETIC AND LOGIC UNIT” 978-1-4244-8679-3/11/$26.00 ©2011
IEEE.
[7]. Manish Kumar, Md. Anwar Hussain, and L.L.K. Singh,” Design of a Low Power
High Speed ALU in 45nm Using GDI Technique and Its Performance Comparison, CNC
2011, CCIS 142, pp. 458–463, 2011.

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[8]. Morgenshtein, A., Fish, A., Wagner, I.A.: Gate-Diffusion Input (GDI) – A
Technique for Low Power Design of Digital Circuits: Analysis and Characterization. In:
ISCAS 2002, USA (May2002).

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APPENDIX B
NAME :Javidi sadgun reddy
HT.NO :15RJ1A0445
Email ID:javidisadgunreddy@gmail.com
PH.NO :8142444846
NAME :Koyyada Laxman
HT.NO :15RJ1A0460
Email ID:koyyadalaxman8@gmail.com
PH.NO :9121464809
NAME :Kotagiri Aravind
HT.NO :15RJ1A0459
Email ID:kotagiriaravind4@gmail.com
PH.NO :9951585947

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15RJ1A0460 LOW POWER 4-BIT ALU USING FULLADDER

Exploitation of very large scale integration (VLSI) technology has developed to

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nm technology. Performance comparison is presented with respect to number of

1.1 ARITHMETIC LOGIC UNIT (ALU) :

An arithmetic logic unit (ALU) is a combinational digital electronic circuit that

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convey information about a previous operation or the current operation, respectively,

Fig:1.1 Block Diagram Of ALU

Fig:1.2 Basic ALU

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Table:1 Truth Table

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1.1.5 Circuit Operation:

Fig:1.3 combinational logic circuit

The combinational logic circuitry of the 74181 integrated circuit, which is a

In general, external circuitry controls an ALU by applying signals to its inputs.

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An ALU is one of the main components of a microprocessor.ALU also contribute

Parameters are constants and not variables:

if sel is true, then y is assigned to a, else it is assigned b.

In Verilog it is possible to concatenate bits using { }:

{a, b, c, a, b, c} is equivalent to: {2{a, b, c}}

assign y if a > b and assign it to b otherwise.

Table 2 shows a list of comparison operators.

Table 2: Comparison Operators

Table 3: Logical Operators

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Binary Arithmetic Operators

Table 4: Binary Arithmetic Operators

Unary Arithmetic Operators

Table 5: Unary Arithmetic Operators

Table 6: Bitwise Operators

A number of basic arithmetic and bitwise logic functions are commonly

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Table 7: Shift Operators

• Zeros are used to fill vacated bit positions.

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A new technique of low-power digital combinatorial circuit design is described.

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Rapid development ofportable digital applications, thedemand for increasing spee

2.1 BASIC GDI FUNCTIONS

Fig: 2.1 GDI basic cell.

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2.2 Transient Analysis

INPUT LOGIC STATES VERSUS FUNCTIONALITY AND OUTPUT SWING OF F1

. Fig:2.2 Input Logic States

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Fig :2.3 A Simple NOT Gate

Fig:2.4 Logic Gates using GDI technology

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Fig:2.5 GDI vs CMOS

2.3 Design of Arithmetic Logic Unit

An ALU is a key component in the Central Processing Unit (CPU) of any

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Fig:2.6 Schematic of 1-Bit ALU Stage

2.4 LITERATURE OVERVIEW:

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[2] A. Morgenshtein, A. Fish, and I. Wagner, “Gate-diffusion input (GDI): a power-

[3].A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, and A. Fish, "Full swing

Full Swing Gate Diffusion Input (FS-GDI) methodology is presented. The

Addition is a vital arithmetic operation and acts as a building block for