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UNIT -3
I/O Organization & I/O Interface
Input Output Organization:
Input/Output Subsystem
The I/O subsystem of a computer provides an efficient mode of communication between the central
system and the outside environment. It handles all the input-output operations of the computer system.
Peripheral Devices
Input or output devices that are connected to computer are called peripheral devices. These devices are
designed to read information into or out of the memory unit upon command from the CPU and are
considered to be the part of computer system. These devices are also called peripherals.
For example: Keyboards, display units and printers are common peripheral devices.
1. Input peripherals : Allows user input, from the outside world to the computer. Example:
Keyboard, Mouse etc.
2. Output peripherals: Allows information output, from the computer to the outside world.
Example: Printer, Monitor etc
3. Input-Output peripherals: Allows both input(from outised world to computer) as well as,
output(from computer to the outside world). Example: Touch screen etc.
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Interfaces
Interface is a shared boundary between two separate components of the computer system which
can be used to attach two or more components to the system for communication purposes.
1. CPU Interface
2. I/O Interface
Input-Output Interface
Data transfer between the central unit and I/O devices can be handled in generally three types of
modes which are given below:
1. Programmed I/O
Programmed I/O:
It is due to the result of the I/O instructions that are written in the computer program. Each
data item transfer is initiated by an instruction in the program. Usually the transfer is from a
CPU register and memory. In this case it requires constant monitoring by the CPU of the
peripheral devices.
Interrupt- initiated I/O:
Since in the above case we saw the CPU is kept busy unnecessarily. This situation can
very well be avoided by using an interrupt driven method for data transfer. By using
interrupt facility and special commands to inform the interface to issue an interrupt
request signal whenever data is available from any device. In the meantime the CPU can
proceed for any other program execution. The interface meanwhile keeps monitoring the
device. Whenever it is determined that the device is ready for data transfer it initiates an
interrupt request signal to the computer. Upon detection of an external interrupt signal
the CPU stops momentarily the task that it was already performing, branches to the
service program to process the I/O transfer, and then return to the task it was originally
performing.
Note: Both the methods programmed I/O and Interrupt-driven I/O require the active
intervention of the
processor to transfer data between memory and the I/O module, and any data transfer
must transverse
a path through the processor. Thus both these forms of I/O suffer from two inherent
drawbacks.
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The I/O transfer rate is limited by the speed with which the processor can test and
service a
device.
The processor is tied up in managing an I/O transfer; a number of instructions must be
executed
for each I/O transfer.
The data transfer between a fast storage media such as magnetic disk and memory unit is
limited by the speed of the CPU. Thus we can allow the peripherals directly communicate
with each other using the memory buses, removing the intervention of the CPU. This type of
data transfer technique is known as DMA or direct memory access. During DMA the CPU is
idle and it has no control over the memory buses. The DMA controller takes over the buses to
manage the transfer directly between the I/O devices and the memory unit.
The purpose of the communication link is to resolve the differences that exist between the
central computer and each peripheral.
The major differences are:
Peripherals are electromechanical and electromagnetic devices and their manner of operation
is different from the operation of the CPU and memory, which are electronic devices. Therefore
a conversion of signal values may be required.
The data transfer rate of peripherals is usually slower than the transfer rate of the CPU, and
consequently, a synchronization mechanism may be needed. Data codes and formats in
peripherals differ from the word format in the CPU and memory.
The operation modes of peripherals are different from each other and each must be controlled
so as not to disturb the operation of other peripherals connected to the CPU.
To resolve these differences, computer systems include special hardware components between
the CPU and peripherals to supervise and synchronize all input and output transfers. These
components are called interface units because they interface between the processor bus and
the peripheral device.
Figure 1 shows the block diagram of I/O interface unit. It consists of 2 data registers called
ports, a control register, a status register, bus buffers and timing and control circuits.
· The interface communicates with the CPU through data bus.
· The chip select (CS) and register select (RS) inputs determine the address assigned to the
interface.
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· The I/O read and write are two control lines that specify an input or output respectively.
· The four registers communicate directly with the I/O device attached to the interface.
· The I/O data to and from the device can be transferred into either port A or port B.
The interface may operate with an output device or with an input device or with a device that
requires both input and output.
PCI 32 bits have a transport speed of 33 MHz and work at 132 MBps.
PCI 64 bits have a transport speed of 33 MHz and work at 264 MBps.
PCI 64 bits have a transport speed of 66 MHz and work at 512 MBps.
Advantage of PCI :
You’ll interface a greatest of five components to the PCI and you’ll be able moreover supplant
each of them by settled gadgets on the motherboard.
You have different PCI buses on the same computer.
The PCI transport will improve the speed of the exchanges from 33MHz to 133 MHz with a
transfer rate of 1 gigabyte per second.
Figure 2(a): Conceptual design of PCI bus for single processor system
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Disadvantage of PCI :
The acronym SCSI stands for small computer system interface. It was adopted as a standard by
the American National Standard Institute (ANSI) in 1986. This bus connects I/O devices such as
hard disk units and printers to personal computers. SCSI was originally designed to transfer data
a byte at a time at rates up to 5 MB/s. The Figure 3 shows the SCSI I/O bus.
SCSI is smaller and simpler bus and its data sub bus is only 8-bits wide. Its data bus is also used to
transfer addresses. Ten additional lines provide all the necessary control functions. Recent extensions
to the original SCSI standard have wider data buses (16 and 32 bits), more control features and higher
SCSI Standard
SCSI-1 defines the basics of the first SCSI buses, including cable length signaling characteristics
,commands and transfer modes.
Devices corresponding to the SCSI-1 standard use only a narrow (8- bit) bus, With a 5 MB/s
maximum transfer rate.
· Only single-ended transmission was supported, with passive termination.
· There were also difficulties associated with the standard gaining universal acceptance due to
the fact that many manufacturers implemented different subsets of its features.
· Devices that adhere to the SCSI-l standard in most cases can be used with host adapters and
other devices that use the higher transfer rates of the more advanced SCSI-2 protocols, but
they will still function at their original slow speed.
SCSI-2 is an extensive enhancement over SCSI-1. In addition, the standard de�nes the following
significant new features as additions to the original SCSI-1 specification:
1.Fast SCSI: This higher-speed transfer protocol doubles the speed of the bus to 10 MHz
2.Wide SCSI: The width of the original SCSI bus was increased to 16 (or even 32) bits. This
permits
more data throughput at a given signaling speed.
3.More Devices per Bus: On buses that are running with Wide SCSI, 16 devices are supported.
SCSI-3 - SCSI-3 specification defines the mechanical, electrical and protocol layers of the
interface. Data
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transfers of 8 bits at 20Mbps over a 50 pin connector and 16 bits at 40Mbps over a 68 pin
connector. The number of devices on the bus increased to 16 (for Fast-10), Fast-20 allows 8
devices maximum with a number of other combinations.
Universal Serial Bus (USB):-
A USB is a common computer port, which shorts for Universal Serial Bus and allows
communication between a computer and peripheral or other devices. It is the most common
interface used in today's computers, which can be used to connect printers
, scanners, keyboards mice, game controllers, digital cameras, external hard drives and flash
drives. The USB has replaced a wide range of interfaces like the parallel and serial port because
it is used for a wide variety of uses as well as offers better support for electrical power. With a
single USB port, up to 127 peripherals can be connected with the help of a few USB hubs,
although that will need quite a bit of dexterity.
A USB is intended to allow hot-swapping and enhance plug-and-play. Without having to restart
the computer, plug-and-play makes it capable of operating the system to involuntarily discover
and configure, and hot-swapping allows replacement and removal of a new peripheral device.
In the devices like smartphones and tablets, a USB may also use for supplying power as well as
charge their batteries. Its first version 1.0, was introduced in January 1996. Then, Intel Compaq,
Microsoft, and other companies adopted this industry-standard quickly.
USB Features :-
� Simple cables
� One interface for many devices
� Automatic configuration
� No user setting
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There are two methods used for transferring data between computers which
are given below: Serial Transmission and Parallel Transmission.
Serial Transmission:
Parallel Transmission:
Synchronous
S.NOTransmission Asynchronous Transmission
In Synchronous
transmission, Data is In asynchronous transmission,
sent in form of blocks or Data is sent in form of byte or
1. frames. character.
In Synchronous
transmission, time In asynchronous transmission,
interval of transmission time interval of transmission is
4. is constant. not constant, it is random.
In Synchronous
transmission, There is no In asynchronous transmission,
gap present between There is present gap between
5. data. data.
Input/Output Processor :-
An input-output processor (IOP) is a processor with direct memory access capability. In this, the
computer system is divided into a memory unit and number of processors.
Each IOP controls and manage the input-output tasks. The IOP is similar to CPU except that it
handles only the details of I/O processing. The IOP can fetch and execute its own instructions.
These IOP instructions are designed to manage I/O transfers only.
Below is a block diagram of a computer along with various I/O Processors. The memory unit
occupies the central position and can communicate with each processor. The CPU processes
the data required for solving the computational tasks. The IOP provides a path for transfer of
data between peripherals and memory. The CPU assigns the task of initiating the I/O
program.The IOP operates independent from CPU and transfer data between peripherals and
memory.
The communication between the IOP and the devices is similar to the program control method
of transfer. And the communication with the memory is similar to the direct memory access
method.
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In large scale computers, each processor is independent of other processors and any processor
can initiate the operation.
The CPU can act as master and the IOP act as slave processor. The CPU assigns the task of
initiating operations but it is the IOP, who executes the instructions, and not the CPU. CPU
instructions provide operations to start an I/O transfer. The IOP asks for CPU through interrupt.
Instructions that are read from memory by an IOP are also called commands to distinguish
them from instructions that are read by CPU. Commands are prepared by programmers and are
stored in memory. Command words make the program for IOP. CPU informs the IOP where to
find the commands in memory.
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Removing the CPU from the path and letting the peripheral device manage the memory buses
directly would improve the speed of transfer. This technique is known as DMA.
In this, the interface transfer data to and from the memory through memory bus. A DMA
controller manages to transfer data between peripherals and memory unit.
Many hardware systems use DMA such as disk drive controllers, graphic cards, network cards
and sound cards etc. It is also used for intra chip data transfer in multicore processors. In DMA,
CPU would initiate the transfer, do other operations while the transfer is in progress and
receive an interrupt from the DMA controller when the transfer has been completed.
Working of DMA :
Following list of points will describe briefly about DMA and its working as follows.
For DMA, you basically need a hardware called DMAC (Direct Memory Access
Controller) which will help in the throughout process of data transfer between the
Memory and IO device directly.
First what happens is IO device sends the DMA request to DMA Controller, then further
DMAC device sends HOLD signal to CPU by which it asks CPU for several information
which are needed while transferring data.
CPU then shares two basic information with DMAC before the Data transfer which are:
Starting address (memory address starting from where data transfer should be
performed) and Data Count (no of bytes or words to be transferred).
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CPU then sends HLDACK (Hold Acknowledgement) back to DMAC illustrating that now
DMAC can successfully pass on the information.
Then further DMAC shares the DMA ACK (DMA Acknowledgement) to the IO device
which would eventually let IO device to access or transfer the data from memory in a
direct and efficient manner.
Modes of DMA Transfer :
During the DMA Transfer CPU can perform only those operation in which it doesn’t
require the access of System Bus which means mostly CPU will be in blocked state.
For how much time CPU remains in the blocked state or we can say for how much time
CPU will give the control of DMAC of system buses will actually depend upon the
following modes of DMA Transfer and after that CPU will take back control of system
buses from DMAC.
Mode-1 :
Burst Mode –
In this mode Burst of data (entire data or burst of block containing data) is
transferred before CPU takes control of the buses back from DMAC.
This is the quickest mode of DMA Transfer since at once a huge amount of
data is being transferred.
Since at once only the huge amount of data is being transferred so time will
be saved in huge amount.
Mode-2 :
Cycle Stealing Mode –
Slow IO device will take some time to prepare data (or word) and within that time CPU
keeps the control of the buses.
Once the the data or the word is ready CPU give back control of system buses to DMAC
for 1-cycle in which the prepared word is transferred to memory.
As compared to Burst mode this mode is little bit slowest since it requires little bit of
time which is actually consumed by IO device while preparing the data.
Percentage of Time CPU remains blocked :
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Let time taken to prepare data be Tx and time taken to transfer the data be Ty. Then
percentage of time CPU remains blocked due to DMA is as follows.
Percentage of time CPU remains in blocked state = Ty * 100% / Tx
Mode-3 :
Interleaving Mode –
Whenever CPU does not require the system buses then only control of buses will be
given to DMAC.
In this mode, CPU will not be blocked due to DMA at all.
This is the slowest mode of DMA Transfer since DMAC has to wait might be for so long
time to just even get the access of system buses from the CPU itself.
Hence due to which less amount of data will be transferred.
Example :
Consider a device operating on 2MBPs speed and transferring the data to
memory is done using Cycle Stealing mode. It takes 2 microseconds to transfer
16 bytes of data to memory when it is ready or prepared. Then for what
percentage of time CPU is blocked due to DMA transfer?
Explanation –
Internal data preparation speed given = 2 MBPs.
So for preparing 2 MB it takes ------> 1 second
For preparing 1B it takes -------> 1 second / 2MB
So now for 16B data preparation it takes ------->1 second * 16B / 2MB
(after reciprocating Mega will be become micro