Module 3 INPUT OUTPUT ORGANIZATION (COA BE306C)

MODULE 3
INPUT/OUTPUT ORGANIZATION
One of the basic features of a computer is its ability to exchange data with other devices.
Computers are an integral part of home appliances, manufacturing equipment, transporta on
systems, banking and point-of-sale terminals.
Input to a computer may come from a sensor switch, a digital camera, a microphone, or a fire alarm.
Output may be a sound signal to be sent to a speaker or a digitally coded command to change the
speed of a motor, open a valve, or cause a robot to move in a specified manner.
Accessing I/O devices:

 A simple arrangement to connect I/O devices to a computer is to use a single bus

arrangement.
 The bus enables all the devices connected to it to exchange informa on.
 It consists of three sets of lines used to carry Address, data, and control signals.
 Each I/O device is assigned a unique set of addresses.
 To access an I/O device, the processor places the address on the address lines.
 The device recognizes the address, and responds to the control signals.
 The processor requests either a read or a write opera on, and the requested data are
transferred over the data lines
There are two ways in which the I/O devices are addressed:
1. Memory mapped I/O
2. I/O mapped I/O
Memory Mapped I/O

 When I/O devices and the memory share the same address space, the arrangement is called
memory-mapped I/O.
 Any machine instruc on that can access memory can be used to transfer data to or from an
I/O device.

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 Simpler so ware is sufficient and same instruc ons can be used to access both memory
and I/O devices
For example,
Move DATAIN,R0
Move R0,DATAOUT
I/O mapped I/O

 When I/O devices and the memory have different address spaces, the arrangement is called
I/O-mapped I/O.
 Special IN and OUT instruc ons to perform I/O transfers.
 I/O devices may have to deal with fewer address lines.
 I/O address lines need not be physically separate from memory address lines.
In fact, address lines may be shared between I/O devices and memory, with a control signal to
indicate whether it is a memory address or an I/O address.

Block diagram of an I/O interface for an input device

Figure 4.2 illustrates the hardware required to connect an I/O device to the bus. I/O device is
connected to the bus using an I/O interface circuit which has:

 Address decoder
 Control circuit
 Data and status registers.

 Address decoder enables the device to recognize its address when this address appears on the
address lines.

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 Data register holds the data being transferred to or from the processor.
 The status register contains informa on relevant to the opera on of the I/O device.
 Data and status registers are connected to the data bus, and have unique addresses.
 I/O interface circuit coordinates I/O transfers

Example of I/O opera ons involving a keyboard and a display device in a computer system

The rate of transfer to and from I/O devices is slower than the speed of the processor. This creates the need
for mechanisms to synchronize data transfers between them.

A simple example of I/O opera ons involving a keyboard and a display device in a computer system.

The four registers shown in Figure 4.3 are used in the data transfer opera ons.

Register STATUS contains two status flags, SIN and SOUT and Interrupt flags for input and output

 SIN: provides the status informa on for the input (keyboard)

 SOUT: provide status informa on for the output (display unit)
 KIRQ: Keyboard Interrupt Request
 DIRQ: Display interrupt Request

The CONTROL register contains the KEN and DEN bits.

 KEN: Keyboard enable

 DEN: Display enable

DATAIN register: Holds the data received from the Keyboard

DATAOUT register: Holds the data to be sent to the display

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 This program reads a line of characters from the keyboard and stores it in a memory buffer
star ng at loca on LINE.
 Then, it calls a subrou ne PROCESS to process the input line.
 As each character is read, it is echoed back to the display.
 Register R0 is used as a pointer to the memory buffer area.
 The contents of R0 are updated using the Autoincrement addressing mode so that successive
characters are stored in successive memory loca ons.
 Each character is checked to see if it is the Carriage Return (CR) character, which has the
ASCII code 0D (hex).
 If the pressed key is Carriage Return, a Line Feed character (ASCII code 0A) is sent to move
the cursor one line down on the display and subrou ne PROCESS is called.
 Otherwise, the program loops back to wait for another character from the keyboard.
Mechanisms used for synchronizing the data transfer between the processor and the I/O devices:
The rate of transfer to and from I/O devices is slower than the speed of the processor. This creates
the need for mechanisms to synchronize data transfers between them.
1. Program controlled I/O: Processor repeatedly monitors a status flag to achieve the
necessary synchroniza on. Processor polls the I/O device.
2. Interrupts: Synchroniza on is achieved by having the I/O device send a special signal over
the bus whenever it is ready for a data transfer opera on.

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3. DMA: Used for high-speed I/O devices. It involves having the device interface transfer data
directly to or from the memory, without con nuous involvement by the processor.

INTERRUPTS
In program-controlled I/O, when the processor con nuously monitors the status of the device, it
does not perform any useful tasks.
An alternate approach would be for the I/O device to alert the processor when it becomes ready.
Do so by sending a hardware signal called an interrupt to the processor.
The interrupt is sent on the interrupt-request (IRQ) line.
Processor can perform other useful tasks while it is wai ng for the device to be ready.
Ac ons involved when an interrupt occurs
Processor is execu ng the instruc on located at address i when an interrupt occurs.
Rou ne executed in response to an interrupt request is called the interrupt-service rou ne. (ISR)

 When an interrupt occurs, control must be transferred to the interrupt service rou ne.
 But before transferring control, the current contents of the PC (i+1), must be saved in a
known loca on.
 This will enable the return-from-interrupt instruc on to resume execu on at i+1.
 Return address, or the contents of the PC are usually stored on the processor stack.
When a processor receives an interrupt-request, it must branch to the interrupt service rou ne.
It must also inform the device that it has recognized the interrupt request.
This can be accomplished in two ways:
1. Explicit interrupt-acknowledge signal
2. Implicit part of data which is to be transferred between the device and the processor

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Consider a task that requires con nuous extensive computa ons to be performed and the results
to be displayed. The displayed results must be updated every ten seconds. The ten-second
intervals can be determined by a simple mer circuit, which generates an appropriate signal. The
processor treats the mer circuit as an input device that produces an interrupt signal.

 The task can be implemented with a program that consists of two rou nes, COMPUTE and
PRINT. The processor con nuously executes the COMPUTE rou ne.
 When it receives an interrupt request from the mer, it suspends the execu on of the
COMPUTE rou ne and executes the DISPLAY rou ne which sends the latest results to the
display device.
 Upon comple on of the DISPLAY rou ne, the processor resumes the execu on of the
COMPUTE rou ne.
 Since the me needed to send the results to the display device is very small compared to
the ten-second interval, the processor in effect spends almost all of its me execu ng the
COMPUTE rou ne.
Differences between Subrou nes and Interrupt Service Rou nes
1. A subrou ne performs a func on required by the program from which it was called.
Interrupt-service rou ne may not have any rela on with the program that was being
executed when interrupt was raised.
2. A subrou ne and the calling program are used by the same user. Interrupt-service rou ne
and the program that it interrupts may belong to different users.

As a result, before branching to the interrupt-service rou ne, not only the PC, but other
informa on such as condi on code flags, and processor registers used by both the interrupted
program and the interrupt service rou ne must be stored.

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Interrupt Hardware
Most computers are likely to have several I/O devices that can request an interrupt on the same
Interrupt Request line
All devices are connected to the line via switches to ground.

 To request an interrupt, a device closes its associated switch.

 Thus, if all interrupt-request signals INTR1 to INTRn are inac ve, that is, if all switches are
open, the voltage on the interrupt-request line will be equal to 𝑉𝑑𝑑.
 This is the inac ve state of the line.
 When a device requests an interrupt by closing its switch, the voltage on the line drops to
0, causing the interrupt-request signal, INTR, received by the processor to go to 1
 Since the closing of one or more switches will cause the line voltage to drop to 0, the value
of INTR is the logical OR of the requests from individual devices, that is,
 INTR =INTR1 + INTR2 + ⋯ + INTRn

Enabling and Disabling of Interrupts:

Interrupts can arrive at any me and the processor has to stop the execu on of present program.
Some mes this is not desirable situa on. Enabling and disabling of interrupts allow the user to block
unnecessary disturbances.
It is convenient to be able to enable and disable interrupts at both the processor and I/O device
ends. The processor can either accept or ignore interrupt requests. An I/O device can either be
allowed to raise interrupt requests or prevented from doing so.

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The different methods to avoid occurrence of another interrupt when one interrupt is serviced:
1. Using hardware to ignore request on Interrupt request line ll first line of ISR (Interrupt
Service Rou ne) is executed. The first line of ISR should be Interrupt Disable and the last line
of ISR should be Interrupt Enable
2. Disabling of interrupts automa cally by the use of some control bits in registers that can be
accessed by program instruc ons.
Program Status Register: (PS)
IE=Interrupt Enable is one bit of this register.
When IE = 1, interrupt requests from I/O devices are accepted and serviced by the processor.

When IE= 0, the processor simply ignores all interrupt requests from I/O devices
The processor saves the contents of the program counter and the processor status register.
The processor automa cally disables interrupts before star ng the execu on of the
interrupt-service rou ne.

IE=1, Processor saves the contents of PS register

The processor sets IE=0 in PS register, thus disabling further interrupts.
Then, it begins execu on of the interrupt-service rou ne.
When a Return-from-interrupt instruc on is executed, the saved contents of the PS
register are restored, se ng the IE bit back to 1. Hence, interrupts are again enabled
3. To make the Interrupt Responding circuit to respond only to the leading edge of the signal

Summary of the sequence of events involved in handling an interrupt request from a single
device. (Assuming that interrupts are enabled in both the processor and the device):
1. The device raises an interrupt request.
2. The processor interrupts the program currently being executed and saves the contents of the PC
and PS registers.
3. Interrupts are disabled by clearing the IE bit in the PS to 0.
4. The ac on requested by the interrupt is performed by the interrupt-service rou ne, during which
me the device is informed that its request has been recognized, and in response, it deac vates the
interrupt-request signal.
5. Upon comple on of the interrupt-service rou ne, the saved contents of the PC and PS registers
are restored (enabling interrupts by se ng the IE bit to 1), and execu on of the interrupted
program is resumed.

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Handling mul ple devices:

Consider the situa on where a number of devices capable of ini a ng interrupts are connected to
the processor. Because these devices are opera onally independent, there is no definite order in
which they will generate interrupts. For example, device X may request an interrupt while an
interrupt caused by device Y is being serviced, or several devices may request interrupts at exactly
the same me.
1. When a request is received though a common IRQ line, it should be possible for the
processor to find the address of the device which has sent the interrupt
2. If more than one device has sent the interrupt request at the same me, it should be
possible for the processor to know which device has to be serviced first.
When a device sends an interrupt request, it also sets the corresponding bit in the status register.
The ISR can poll all the I/O devices and the first device encountered with its IRQ bit set to 1 is the
device that should be serviced.
An appropriate subrou ne is then called to provide the requested service.
The polling scheme is easy to implement. Its main disadvantage is the me spent interroga ng the
IRQ bits of devices that may not be reques ng any service.
An alterna ve approach is to use vectored interrupts
Vectored interrupts:
A device reques ng an interrupt can iden fy itself if it has its own interrupt-request signal, or if it
can send a special code to the processor through the interconnec on network.
The processor’s circuits determine the memory address of the required interrupt-service rou ne.
A commonly used scheme is to allocate permanently an area in the memory to hold the addresses
of interrupt-service rou nes. These addresses are usually referred to as interrupt vectors, and they
are said to cons tute the interrupt-vector table
This arrangement implies that the interrupt-service rou ne for a given device must always start at
the same loca on.
When an interrupt occurs, the processor should know the star ng address of the interrupt service
rou ne for that par cular interrupt. This address is called interrupt vector and it is loaded into the
PC.
In most computers, I/0 devices send the interrupt-vector code over the data bus.
Here, the I/O device reques ng service sends the high value on INTR line. When the processor is
ready to accept the interrupt, it ac vates the interrupt acknowledge INTA signal. The I/O device
responds by sending its interrupt vector code and turns off INTR signal.

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Interrupt Nes ng
When an interrupt is to be serviced, the processor disables all the interrupt requests. So, the other
devices have to wait to get the service. But in some cases, this wai ng state is not desirable.
So, I/O devices are organized in a priority structure.
An interrupt request from a high-priority device is accepted while the processor is execu ng the
interrupt service rou ne of a low priority device.
A priority level is assigned to a processor that can be changed under program control.
Priority level of a processor is the priority of the program that is currently being executed.
When the processor starts execu ng the interrupt service rou ne of a device, its priority is raised to
that of the device.
If the device sending an interrupt request has a higher priority than the processor, the processor
accepts the interrupt request.

A mul ple-priority scheme can be implemented easily by using separate interrupt-request and
interrupt- acknowledge lines for each device, as shown in Figure 4.7.
Each of the interrupt-request lines is assigned a different priority level.

Interrupt requests received over these lines are sent to a priority arbitra on circuit in the processor.
A request is accepted only if it has a higher priority level than that currently assigned to the
processor.

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Simultaneous Requests:
If more than one device sends the interrupt requests simultaneously, processor should have the
means to decide which one to be serviced.
If there are mul ple INTR lines, processor can use priority schemes to decide which request is to be
serviced.
If there is only a single line, the following methods are used:
1. Polling scheme
2. Daisy chain scheme
Polling scheme:

 Here the device which raises the interrupt, sets the corresponding bit in the status register
 The processor polls the status registers of I/O devices to determine which device is
reques ng an interrupt.
 In this case the priority is determined by the order in which the devices are polled.
 The first device with status bit set to 1 is the device whose interrupt request is accepted.
Daisy chain scheme:

 Devices are connected to form a daisy chain.

 The interrupt-request line INTR is common to all devices
 Interrupt-acknowledge line INTA is connected in a daisy-chain fashion.
 When devices raise an interrupt request, the interrupt-request line INTR is ac vated.
 The processor responds by se ng INTA line to 1
 This signal is received by device 1; if device 1 does not need service, it passes the signal to
device 2.
 If device 1 has a pending request for interrupt, it blocks the INTA signal and proceeds to put
its iden fying code on the data lines.
 Device that is electrically closest to the processor has the highest priority.

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Combina on of Priority structure and Daisy chain scheme is shown below:

 Devices are organized into groups.

 Each group is assigned a different priority level.
 All the devices within a single group share an interrupt- request line, and are connected to
form a daisy chain

Controlling Device Requests

1. At the device end: The interface circuit of each I/O device has Interrupt Enable (IE) bit. If for a
device IE=1, then that par cular device is allowed to generate the interrupt request signal.
2. At the processor end: Interrupt-enable (IE) bit in the processor status register or the priority
structure of the interrupts determines whether a given interrupt will be accepted

DIRECT MEMORY ACCESS

 A special control unit may be provided to transfer a block of data directly between an I/O
device and the main memory, without con nuous interven on by the processor.
 This approach is called direct memory access, or DMA.
 DMA transfers are performed by DMA controller, which is a control circuit that is a part of
the I/O device interface.
 DMA controller performs func ons that would be normally carried out by the processor:
 For each word, it provides the memory address and all the control signals.
 To transfer a block of data, it increments the memory addresses and keeps track of the
number of transfers
 DMA controller can transfer a block of data from an external device to the processor, without
any interven on from the processor.

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 However, the opera on of the DMA controller must be under the control of a program
executed by the processor. That is, the processor must ini ate the DMA transfer.
 To ini ate the DMA transfer, the processor informs the DMA controller of:
 Star ng address,
 Number of words in the block.
 Direc on of transfer (I/O device to the memory, or memory to the I/O device).
 Once the DMA controller completes the DMA transfer, it informs the processor by raising an
interrupt signal.
 While a DMA transfer is taking place, the program that requested the transfer cannot
con nue, and the processor can be used to execute another program.
 A er the DMA transfer is completed, the processor can return to the program that requested
the transfer.
 When the transfer is completed, the DMA controller informs the processor by sending an
interrupt request.
 In response, the OS puts the suspended program in the Runnable state so that it can be
selected by the scheduler to con nue execu on.

 Two registers are used for storing the star ng address and the word count.
 The third register contains status and control flags.
 The R/W bit determines the direc on of the transfer.
 When this bit is set to 1 by a program instruc on, the controller performs a read opera on.
 Otherwise, it performs a write opera on.
 When the controller has completed transferring a block of data and is ready to receive
another command, it sets the Done flag to 1.
 Bit 30 is the Interrupt-enable flag, IE.
 When this flag is set to 1, it causes the controller to raise an interrupt a er it has completed
transferring a block of data.
 Finally, the controller sets the IRQ bit to 1 when it has requested an interrupt
An example of a computer system is given in Figure 4.19, showing how DMA controllers may be
used.

 DMA controller connects a high-speed network to the computer bus.

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 Disk controller, which controls two disks also has DMA capability.
 It provides two DMA channels.
 It can perform two independent DMA opera ons, as if each disk has its own DMA controller.
 The registers to store the memory address, word count and status and control informa on
are duplicated.

 To start a DMA transfer of a block of data from the main memory to one of the disks, a
program writes the address and word count informa on into the registers of the
corresponding channel of the disk controller.
 The DMA controller proceeds independently to implement the specified opera on.
 When the DMA transfer is completed, the “Done” bit in the status and control register of the
DMA channel is set .
 At the same me, if the IE bit is set, the DMA controller sends an interrupt request to the
processor and sets the IRQ bit. (indica ng that the transfer is complete)
 Processor and DMA controllers have to use the bus in an interwoven fashion to access the
memory.
 DMA devices are given higher priority than the processor to access the bus.
 Among different DMA devices, high priority is given to high-speed peripherals such as a disk
or a graphics display device.
Cycle stealing mode: The processor originates memory access cycles and DMA controller uses it
(steals) for data transfer as and when required.
Block or Burst mode: DMA controller ini ates transfers on the bus for a block of data at a me

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