Introduction To VLSI

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INTRODUCTION TO
VLSI CIRCUIT DESIGN
SHAHRIYAR MASUD RIZVI
ASSISTANT PROFESSOR
FACULTY OF ENGINEERING
AIUB
© Shahriyar Masud Rizvi, 2006, 2009

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REFERENCES:
1. Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design - A
Systems Perspective, 2nd Edtion.
2. John P. Uyemura, Introduction to VLSI Circuits and Systems.
3. M. D. Ciletti, Advanced Digital Design with the Verilog HDL.
4. Yu Cao, Arizona State University, AZ, USA.
5. Bogdan Wilamowski, University of Wyoming WY, USA and Auburn University, AL,
USA.

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VLSI-Very Large Scale Integration
VLSI Design or VLSI Circuit Design refers to

designing high-density electronic circuits, typically
circuits that contain transistor in excess of 100,000.
There are 2 types of VLSI Circuits-Analogue and

Digital.
In this course, by VLSI Design or VLSI Circuit

Design, we mean Digital VLSI Circuit Design,
primarily CMOS Digital VLSI Circuit Design.
VLSI Circuit Design typically (and in this class)

involves discussions about different logic styles and
implementation technologies for implementing
digital circuits, transistor and mask-level layout and
interconnect, fabrication technologies and analysis of
various design and performance parameters such as
Speed, Power, Cost, Reliability etc.
The discussion typically is at Logic (Gate), Circuit

(Transistor) and Physical/Mask (Silicon) Level.
Integration simply means more devices per chip.

Integration improves design, that is its speed, power
consumptions, size—and reduces manufacturing
costs.

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Digital VLSI Circuit Design

Fundamentals
Logic Styles (NMOS, CMOS, Bipolar, Pseudo-NMOS, Dynamic CMOS, Transmission
Gate, Pass Transistor logic etc.)
Implementation Technologies (Full-Custom design and Semi-Custom design including

ASIC (MPGA and SBIC), FPLD (CPLD and FPGA) etc.)
Boolean Logic
Logic Minimization
Relevant Courses
Digital Logic Design

Digital Electronics
Electronic Device
Solid-State Electronics/Semiconductor Electronics
Materials
Practical Aspects Relevant Courses
Combinational Logic Design: Adders, Multipliers, Multiplexers, ALUs etc.
Sequential Logic Design: Registers, Register Files, Counters, Shift Registers, Finite State
Machines (FSM) etc.
Memory Design: RAM (SRAM, DRAM), ROM (PROM. EPROM, EEPROM, Flash) etc.
Electronic Design Automation (EDA), Computer Aided Design (CAD), Computer Aided
Engineering (CAE) tools
System-level, Architecture-level, Register Transfer (RT) Level design.
Relevant Courses
High-Level or Behavioral Synthesis/Architecture Description Language (ADL/)System-
on-Chip (SOC) Design/Analog and Mixed-Signal (Digital + Analog) Design ( System-
Level (typically discussed in graduate program (MS/PhD)
Computer Architecture (Architecture Level)
VHDL (or Verilog) Modeling and Synthesis (RT-Level)
Microprocessor (System-Level)

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In the Middle—VLSI
Clock Generators and Clock Buffers
Clock Synchronizers, Clock Managers, Clock Tree Insertion
Test Synthesis, Fault Analysis, Scan-chain
Speed (Delay)
Power Consumption
Cost
Reliability
Logic-Level (Gate-Level), Circuit-Level (Transistor-Level) and Physical Design

(Mask/Silicon-Level) Design/Layout Synthesis
Relevant Course
VLSI Circuit Design

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Levels of Abstraction:
HARDWARE + SOFTWARE
ELECTRONIC SYSTEM LEVEL (ESL)/ HARDWARE-SOFTWARE CO-DESIGN,
SYSTEM-ON-CHIP (SOC)
Hardware + Software, SOC

Electronic System Level (ESL) ESL Languages
(i.e. SystemC, SystemVerilog, MATLAB)
(Previously SuperLog, Vera, e etc.)
Bus Functional Model

Board Level
Instruction Set Architecture Level (ISA) ADL Languages (i.e. LISA, Expression, ACME, AADL)
or Processor-Memory-Switch Level (PMS)
(High-Level) Algorithmic C, C++, System C, SystemVerilog

or (High-Level) Behavioral Level
System Hardware
Behavior
Algorithm
Architecture
Register Transfer Level (RTL) HDL Languages (i.e. VHDL, Verilog HDL)
(Previously ABEL)
Structural Level
Gate Level HDL Languages (i.e. VHDL, Verilog HDL)
Switch Level HDL Language (Verilog HDL)
Circuit Level SPICE, Verilog-AMS, VHDL-AMS,Verilog-A

Polygons
Sticks
Mask Level /Device Level
Silicon

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HARDWARE
System
Behavior
Algorithm
Architecture
Structural Level
Switch Level HDL Language (Verilog HDL)
Circuit Level SPICE, Verilog-AMS, VHDL-AMS, Verilog-A

Polygons
Sticks
Silicon
System
Behavior
Algorithm
Architecture
Circuit Level SPICE, Verilog-AMS, VHDL-AMS, Verilog-A
Silicon

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Full-Custom Chip (FCC) Design
Register Transfer Level Design Front-end Design
Logic Design
Circuit Design
Physical Design (Mask Design/Layout Design) Back-end Design
Silicon
Semi-Custom Chip (ASIC/FPLD) Design
Register Transfer Level Design Front-end Design
Logic Design
Physical Design (Mask Design/Layout Design) Back-end Design
Silicon

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Example of designing at various Levels of Abstraction:
1-bit, 2-to-1 Multiplexer (Mux):
System Level:
A
Mux Y
Sel
Behavioral Level:
Pass A when Sel is 1.

Pass B when Sel is 0.
Architecture Level:
A
Register Y
Mux
B Register
Register
Sel
OR
A
Mux Y
Sel

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OR
Enable
A
Mux Y
Sel
Let us select the following simple architecture
A
Mux Y
Sel

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Algorithmic Level (Algorithm):
Sel A B Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 1 0 1
1 0 1 0
1 1 1 1
FOR SEMI-CUSTOM CHIPS (FPLDS/ASICS)
BOOLEAN EQUATIONS SUITABLE FOR LOGIC-LEVEL
Y = Sel . A. B + Sel . A. B + Sel . A. B + Sel . A. B
Y = Sel . B. (A + A) + Sel . A . (B + B)
Y = Sel . B + Sel . A
FOR FULL-CUSTOM CHIPS
BOOLEAN EQUATIONS SUITABLE FOR CIRCUIT-LEVEL
Y = Sel . A. B + Sel . A. B + Sel . A. B + Sel . A. B
Y = Sel . B. (A + A) + Sel . A . (B + B)

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Register Transfer (RT) Level:

Using Hardware Description Languages (HDL)
VHDL Verilog HDL

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Mux_1Bit_2_to_1 IS module Mux_1Bit_2_to_1(Sel,A,B,Y);

PORT (Sel, A, B : IN STD_LOGIC; input Sel;
Y : OUT STD_LOGIC); input A;
END Mux_1Bit_2_to_1; input B;
output Y;
ARCHITECTURE Behavior OF
Mux_1Bit_2_to_1 IS wire Sel, A, B;
BEGIN reg Y;
PROCESS (Sel, A, B) always @ (Sel or A or B)

BEGIN begin
IF (Sel = '1') THEN Y <= A; if (Sel == 1) Y = A;
ELSIF (Sel = '0') THEN Y <= B; else if (Sel == 0) Y = B;
ELSE Y <= '0'; else Y = 0;
END IF;
end
END PROCESS;
endmodule
END Behavior;
Logic Level (Gate Level)
Can be Automatically generated by Synthesis Tools/Synthesizers

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Circuit Level (Transistor Level)

Using Mirror-Logic
Not necessary for Semi-Custom Chips (FPLDS/ASICS)
Necessary for Full Custom Chips

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Physical Level (Mask-Level/Layout)
Mask-Level Physical Design is Not necessary for Semi-Custom Chips

(FPLDS/ASICS)
Necessary for Full Custom Chips
Gate-level Physical Design can be generated by Place and Route (PAR) tools

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LEVEL OF ABSTRACTIONS IN TOP-DOWN DESIGN FLOW

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Digital Design Techniques:
Traditional Non-Automated Design Process:
Select Standard Parts (Discrete gates and Standard ICs)

Physically connect (wire) the parts together
Verify Functionality through Oscilloscope/Logic Analyzer
Learn in Digital Logic Design
OR
Draw Gate-Level Schematic

Verify Schematic
Draw Transistor-Level Schematic
Verify Schematic
Draw Mask-Level Schematic
Verify Schematic
Send Design for Fabrication
Verify Functionality of Fabricated Design through Oscilloscope/Logic Analyzer
Learn in VLSI Circuit Design class.
Semi-Automated Design Process
Draw Gate-Level Schematic in a Schematic Design Entry software (Schematic Entry)

Verify Schematic
Convert Gate-Level Schematic to Transistor-Level Schematic (Manual/Automatic)
Verify Schematic
Convert Transistor-Level Schematic to Mask-Level Schematic(Automatic)
Verify Schematic
Send Design for Fabrication
Verify Functionality of Fabricated Design through Oscilloscope/Logic Analyzer

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Automated Design Process (Using EDA Tools)
Initial Front-End Design Steps
These design steps are common for both Full-Custom and Semi-Custom Chips
-whether you go for In-System Configuration/Programming (FPLD) or Fabrication
(ASIC or Full-Custom Chips)
Write RT Level HDL code -HDL Design Entry

Verify HDL Code -Functional Simulation
Convert RT Level HDL code to Gate-Level Description (Automatic)
-Logic Synthesis
Verify Gate-Level Description -Post-Synthesis Simulation
Learn in VHDL Modeling and Logic Synthesis class.
Option A.
Place and Route/Fit Gate-Level Description to Layout of Target FPLD Chip (Automatic)
-Automatic Place-and-Route
Verify Fitted/Placed-and-Routed Layout -Post-Fit Simulation/
Post-Route Simulation
Program an FPLD (CPLD/FPGA) (Automatic)-
Programming/Configuration/Download
Verify Functionality of Implemented Design through Oscilloscope/Logic Analyzer
Option B.
Place gate-Level Description to Layout of the Target ASIC chip (Automatic)

-Placement
Insert Design for Test (DFT) (such as Scan-Chain, JTAG, BIST) and Automatic Test
Pattern Generation (ATPG) - DFT Insertion and ATPG
Verify for Faults -Fault Simulation
Insert Clock-Tree -Clock-Tree Insertion
Route final Layout (Automatic) -Routing

Post-Route Simulation/
Layout Simulation

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Fabricate ASIC- -Fabrication
Learn in VLSI Circuit Design class in future.
Option C.
Semi-Automated Design Process
Select Technology or Process
Write SPICE/VHDL-AMS/Verilog-AMS code for Transistor Level design (Manual) or

Convert Synthesized Gate-level Description to Transistor-Level Schematic (Automatic)
-Circuit Design
Verify Circuit-Level Schematic
-Circuit Simulation
Place gate-Level Description to Layout of the Target Full-Custom chip (Automatic)

-Placement
Insert Design for Test (DFT) (such as Scan-Chain, JTAG, BIST) and Automatic Test
Pattern Generation (ATPG) - DFT Insertion and ATPG
Verify for Faults -Fault Simulation
Insert Clock-Tree -Clock-Tree Insertion
Route final Layout (Automatic) -Routing

Post-Route Simulation/
Layout Simulation
Fabricate ASIC- -Fabrication

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Digital Design Techniques-Top-Down Design vs. Bottom-Up Design:
Digital circuits can be designed at Top-Down or from Bottom-Up. In bottom-up design,

the details are figured out first. For example, transistor or mask-level cells are designed
first. Later the individual cells are connected to form the complete design.
In top-down design, the system is designed at an abstract level such as at behavioral or

architectural level first, details are figured out later. For example, the top-level block
diagram with system input and output is designed first. Then RT level description is
written. Gate-Level Description is generated later. Afterwards, it is converted to Mapped
Layout to prepare for FPLD Programming or Mask-Level Layout is generated for
sending design to Fabrication (for fabrication of an ASIC).
Top-Down design takes away from Logic (Gate) and Circuit (Transistor) to abstract
behavior, macro architecture and abstract programming (HDL)

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VLSI HISTORY AND ADVANCES:

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Sel Bar

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EDA Tools:
Electronic Design Automation (EDA):
EDA tools are specific Computer Aided Design (CAD) and Computer Aided Engineering
(CAE) tools that are used to verify and implement digital circuits originally defined
through an HDL.
Key Processes:
Synthesis:
An automated process that takes in a Register Transfer (RT) level textual design
description described at a Hardware Description Language (HDL) or a structural or
algorithmic graphical design description described through a gate-level schematic,
Intellectual Property (IP) or a State Chart/Algorithmic State Machine (ASM) chart, 1.
translates it to an RT Level HDL code, if necessary, 2. optimizes it at RT Level, 3.
converts it to a generic Structural Gate-Level description, 4. optimizes it at Gate-Level
for Speed or Area or other design constraints and 5. then finally customizes the Gate-
Level description for a specific target technology (FPLD/ASIC) by using technology
cells available in that target technology.
Synthesis has 2 parts: RTL Synthesis and Logic Synthesis.
RTL Synthesis involves 2 parts: Translation and Optimization.
Logic Synthesis has 3 parts: Translation, Optimization and Mapping.
1. RTL Synthesis:
An automated process that takes in a Register Transfer (RT) level textual design
description described at a Hardware Description Language (HDL) or a structural or
algorithmic graphical design description described through a gate-level schematic,
Intellectual Property (IP) or a State Chart/Algorithmic State Machine (ASM) chart, 1.
translates it to an RT Level HDL code, if necessary, (Translation) and 2. optimizes it at
RT Level (Optimization).
2. Logic Synthesis:
An automated process that converts the optimized Register Transfer (RT) level HDL
description to a generic Structural Gate-Level description (Translation) and optimizes it
at Gate-Level for Speed or Area or other design constraints (Optimization) and then
finally customizes the Gate-Level description for a specific target technology
(FPLD/ASIC) by using technology cells available in that target technology (Map).

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2. Cell Placement and Floorplanning:
3. Design for Test (DFT) Insertion and Automatic Test Pattern Generation (ATPG)
4. Clock-Tree Insertion
5. Cell Routing

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Functional/Behavioral/RTL Simulation:
This process verifies the HDL code. It checks the functionality of the design including
logical and syntactical correctness. It contains no information about Inertial or
Propagation Delay (including Clock-to-Q Delay).
This is an ideal simulation; without any type of delay—“Inertial” Delay (initial delay at
power up), Propagation Delay (for combinational logic) or Clock-to-Q Delay (T clk-to-Q)
(for sequential logic)—and the influence of global Set-Reset signals.
The default Propagation Delay is Delta_Delay, which is typically defined as 0 ps, which
can be considered as zero delay.
Since it has no synthesis information, it does not check whether the HDL code can be
synthesized or not. In other words, non-synthesizable code (i.e. using /, abs, mod, rem, **
operators, using Real data types (floating point)) can be verified through Functional
Simulation but will fail in Synthesis.
Post-Synthesis/Logic Simulation:
This process verifies the synthesized gate-level circuit. It checks the functionality of the
synthesized design. Generally it contains no information about Inertial or Propagation
Delay (including Clock-to-Q Delay) (since it is done before Automatic Place-and-Route).
Some tools might incorporate approximate estimates of such delays at this simulation. It
is however sensitive to the effect of global Set-Reset signal (i.e. PRLD/GSR for Xilinx
FPLDs).
Since it is done after synthesis, it does check whether the HDL code can be synthesized
or not. In other words, non-synthesizable code (i.e. using /, abs, mod, rem, ** operators,
using Real data types (floating point)) cannot be verified through Post-Synthesis
Simulation, even though it might have been passed earlier by Functional Simulation.

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Layout Simulation:
Static Timing Analysis:
Power Estimation:
Design Rule Check
Formal Verification:

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Implementation Technologies for Digital Circuits:
Digital circuits can be implemented using General-Purpose and Un-Customized circuits

or in Special-Purpose and Customized circuits.

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27
Digital Hardware
General Purpose Custom Logic/

Devices Special-Purpose
Devices
Generic General Application-

Purpose Specific General
Devices Purpose
Devices
Standard Processors/ Application- Application-Specific

Products CPUs Specific Standard Microprocessors
(SP) Products
(ASSP)
Discrete Discrete Standard Microprocessors

Gates Flip- ICs (MPU) and
Flops (i.e. Microcontrollers Digital Signal Network Processors
Timers, (MCU) Processors (DSPs)
Counters)
Microprocessors Microcontrollers
(MPU) (MCU)
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Digital Hardware
General Purpose Special-Purpose

Devices Devices/
Custom Logic
Full-Custom Chips Semi-Custom Chips
Application Specific
Integrated Circuits Programmable Logic
(ASICs)
Simple Programmable Logic Field Programmable Logic Devices

Devices (SPLDs) (FPLDs)
Standard Cell-based Mask Structured Programmable Programmable Complex Field Programmable Platform
Integrated Circuits Programmable Gate ASICs/ Array Logic Logic Array Programmable Gate Arrays FPGAs
(CBIC) Arrays (MPGAs) Platform ASICs (PAL) (PLA) Logic Devices (FPGAs)
(CPLDs)
General Purpose (Un-Customized) device:
General-Purpose devices are not meant for any specific application. They are meant for
many tasks, not for a single, specific task. Their hardware architecture or functionality is
not customized for any specific application/task. They are designed by manufacturer, but
in some cases, their functionality can be customized by the designer (i.e.
Microprocessor). They are generally available in the market.
General Purpose (Un-Customized) device are of 2 types:

1. Standard Parts (Discrete gates and Standard ICs)
2. Microprocessors
Special-Purpose (Customized) device:
Special Purpose devices are meant for a specific application. They are typically meant for
a single task, not for many tasks. Their functionality and design architecture are defined
by the designer himself/herself. Chip Architecture remains fixed and defined by
manufacturer, though. They are generally not available in the market in the complete
functional form.
Special-Purpose (Customized) devices are of 2 types:

1. Full Custom Device
2. Semi-Custom Device
Semi-Custom Devices are of 2 types:

1. Application Specific ICs (ASICs)
2. Field Programmable Logic Devices (FPLDs)
ASICs are of 2 types:

1. Standard Cells/ Standard Cell-Based ICs (CBIC)
2. Gate Arrays/ Mask Programmable Gate Arrays (MPGAs)
FPLDs are of 2 types:

1. Complex PLDs (CPLDs)
2. Field Programmable Gate Arrays (FPGAs)
Full Custom Devices are completely designed by the designer. Both their hardware
architecture (both Chip and Design Architecture) and functionality are defined by the
designer. Typically they are designed from bottom-up. Cells from vendors are not used at
all. All the cells are designer-defined. You can think of them as “hand-crafted” chips.
They can be considered an array of transistors and user-defined cells.
Semi-Custom Devices are designed by the designer and partially or completely

manufactured by the manufacturer. Their functionality (Design Functionality) is always
defined by the designer. Chip Architecture is generally defined by the manufacturer and
cannot be changed. Design Architecture is always defined by the designer; it can be
changed by the designer after implementation in some cases such as FPLDs or remains
fixed after implementation in others, such as ASIC.
ASICs are not completely pre-fabricated and require a final fabrication. So, designer
needs to design and provide a mask-level layout that can be understood by fabrication
tools. ASIC is an array transistors, user-defined cells and vendor-defined cells.
MPGA type ASIC is an array of transistors, flip-flops, user-defined cells and pre-defined
vendor-defined basic cells. These cells are mostly 4-transistor cells, which can be easily
connected to form NAND and NOR gates or D Flip-flops (D flip-flops generally needs 6
transistors).Designer can define both cells (for design) and interconnections.
CBIC type ASIC is an empty ASIC chip where the definer can “fill” with vendor-defined
basic cells (transistors, gates, flip-flops) or vendor-defined cells/macros/IP. These cells
are pre-designed and pre-simulated and validated and also layout-ready. So after place-
and-route, CBICs become array of pre-defined vendor-defined cells. Designer can only
define interconnections between cells.
FPLDs are pre-fabricated; but requires customization through programming/download for

a specific application/task. FPLD is an array of gates/logic blocks, flip-flops, user-defined
cells and pre-defined vendor-defined cells.
CPLD type FPLD is an array of gates, flip-flops, user-defined cells and pre-defined
vendor-defined cells. In a macro-level, CPLD hardware architecture is an array of PALs-
Programmable Array Logic, that has a programmable AND network, a fixed OR gate and
some flip-flops. Each PAL is an array of gates, flip-flops, predefined vendor-defined cells
and can also have user-defined cells. Designer can define both cells and interconnections.
FPGA type FPLD is an array of logic blocks (such as CONFIGURABLE LOGIC

BLOCKS (CLB))--which are themselves composed of Look Up Tables (LUT)), muxes
and flip-flops--and user-defined cells and pre-defined vendor-defined cells. At macro-
level, FPLD hardware architecture is an array of Configurable Logic Blocks (CLB). Each
CLB is an array of LUTs, muxes and some flip-flops. Designer can define both cells and
interconnections.
Full Custom vs. Semi-Custom and ASIC vs. FPLD:
Typically, Full-custom devices have the highest speed (smallest delay) and density
(largest no. of gates/flops) and least power consumption among all types of digital
implementation technologies. Their cost-both NRE (no-Recurring Engineering) cost and
per-unit cost-are the highest. Wafers are not pre-fabricated. No mask-level layers are
defined. No cells or layers are pre-fabricated. Everything is made from ground up. They
are used only in high-end applications (i.e. for highly sensitive and super-fast components
in Defence, Aerospace, Spacecrafts etc.). But they cannot be modified/upgraded after
fabrication (design and chip architecture (hardware) and design functionality are fixed).
Due to their cost, large volume production is not economically viable/feasible. Feasible
for very small-volume production.
ASICs have lower speed, density and cost and higher power consumption as compared to
Full Custom devices. But between ASICs and FPLDs, ASICs typically have higher speed
and density and lower power consumption. But they cannot be modified/upgraded after
fabrication (design and chip architecture (hardware) and design functionality are fixed
after fabrication). As compared to FPLDs, their NRE cost is higher, but per-unit cost is
lower. The long-term cost is low primarily because they are partially manufactured as the
wafer is already pre-fabricated, some cells are already available in the library and
typically only metallization layer/mask (in some cases, a few other masks)—for
interconnection—is customized, other layers are typically predefined. Feasible for large
volume production.
On the other hand, FPLDs typically have relatively lower speed and density and higher
power consumption, as compared to ASICs. However, they can be modified/upgraded
after programming (design architecture (and thereby, design functionality, in certain
cases) is programmable, even though chip architecture is fixed). FPLDs can be
reprogrammed with a modified or upgraded design in the field either locally or remotely
through Internet. Because of their reprogrammability, FPLDs provide the fastest design
prototyping (rapid prototyping), fastest production (low-volume) and marketing (since
they have faster time-to-market) and the maximum flexibility to design changes and
upgrades (since they can be reprogrammed). They can be used for ASIC prototyping,
before ASIC fabrication (since prototyping is rapid in FPLDs as compared to ASICs). As
compared to ASICs, their NRE cost is lower, but per-unit cost is higher. Feasible for
small to medium volume production.
For a given application, Microprocessors are typically the slowest among all digital
implementation technologies (ignoring Standard Parts), since they are not designed for a
specific application/task. But they are the most flexible, among all the technologies, since
their functionality can be easily customized by the user (Chip Functionality is
programmable--even though chip architecture is fixed) through a high-level program
(Assembly, C, C++, Java etc.). Microprocessors are fully fabricated. Their functionality
is customized by the user for a given application/task. Since they are useful in many
application/tasks, they are feasible for large volume production.
For large and complex digital systems/PCBs, typically Microprocessors are used as a
central control and computation unit. Ultra High-speed computation is handled by ASICs
and Full-Custom devices (if you can afford it!). Ultra High-speed computations whose
specification/functionality might change according to external factors, demand or with
time, and thus might need to be modified or upgraded from time to time, are handled by
FPLDs.
Chip Architecture Design Architecture Chip Functionality Design Functionality

Technology
Type
Fixed or Defined by Fixed or Defined Fixed or Programmable Defined by Fixed or Programmable Defined by
Programmable Programmable by after Implementation after Implementation
after after
Implementation Implementation
Full-Custom Customized by Designer Fixed Designer -- -- Fixed Designer
IC the Designer,
but Fixed after
Fabrication.
SBIC type Fixed Manufacturer Fixed Designer -- -- Fixed Designer
ASIC
MPGA type Fixed Manufacturer Fixed Designer -- -- Fixed Designer

ASIC
FPLD Fixed Manufacturer Programmable Designer No Generic Functionality Manufacturer Fixed for a given Designer
(CPLD/FPGA) version
Has to be customized for (can be
a specific modified/upgraded in a
task/application. new
(undefined before first download/programming)
Programming/Download)
Microprocessor Fixed Manufacturer -- -- Programmable Designer -- --
But
No Generic Functionality
Has to be customized for
a specific
task/application.
(undefined before first
Programming)
Note that a Microprocessor implemented in an FPLD has the best of both worlds-
Programmable Design Architecture (since FPLD) and Programmable Design
Functionality (since Microprocessor).
For Multiple-Chip system, based on Standard Parts (Discrete Gates (i.e., AND, OR, NOT
etc.) and Standard ICs (Flip-flops, Registers, Synchronous Counters, Timers, Muxes,
Demuxes etc.)), the following table is applicable.
System/Design Architecture Individual Chip Architecture System/Design Functionality Individual Chip Functionality
Technology
Type
Fixed or Defined by Fixed or Defined by Fixed or Programmable Defined by Fixed or Defined by
Programmable Programmable after Implementation Programmable after
after after Implementation
Implementation Implementation
Multiple Chip Manually Defined by Fixed Manufacturer Manually Changeable Defined by Fixed Manufacturer
System based Changeable Designer. Designer.
on Standard
Parts
1. FULL-CUSTOM CHIPS:
2. SEMI-CUSTOM CHIPS
A. ASICS:
1. MPGA:
2. STANDARD CELL-BASED INTEGRATED CIRCUITS (CBIC):
MACROCELL
PRIMITIVE CELLS
(BASIC CELLS)
(I.E. NAND, NOR ETC.)
FULL-CUSTOM VS. SEMI-CUSTOM ASICS:
B. FPLDS
1. CPLDS
2. FPGAS:
Typical Top-Down Design Flow for Semi-Custom Chips (ASICs/FPLDs) using EDA tools:
LEVEL 3
Marketing Requirement
(Product Requirement)
Feasibility (Economic) Study (may be optional)

For product,
(is there demand for product,
will production be Small-scale or medium-scale or large-
scale (mass),
will FPLD or ASIC or Full-Custom Chip
be financially feasible)
Select Implementation Style/Technology

(General Purpose or Special-Purpose)
Select Target Technology (FPLD or ASIC (CBIC

or MPGA))
Select Package (PC or VQ etc., 108 or 208 or 1156

etc.)
Select Vendor and/or Third-Party for IP cores and

EDA tools
Select Vendor for Target Technology (for FPLD)

or Fabrication (For ASIC or Full-Custom Chip)
Interface / IO communication requirements (serial IO constraints/requirements

interface SPI, UART, USART, USB etc. or parallel (IO standards (LVTTL, LVCMOS etc.), IO speed
interface, PCI etc. or Ethernet interface (regular and drive strength
Ethernet or Giga-bit Ethernet etc.) (FX2 OR other high-speed interfaces etc.),
Design Specifications
Board or SOC constraints/requirements
System
Behavior
(what does the digital circuit do (add, subtract,
multiply? etc.))
Algorithm
(State Chart, ASM Chart etc.)
Architecture
(if it is adder Ripple-carry Adder architecture or
Carry Look Ahead architecture?)
Architecture
(if it is adder Ripple-carry Adder architecture or
Carry Look Ahead architecture?)
Algorithmic Graphical Vendor-supplied or Gate-level Graphical Description

Design Description third-party Graphical or
(State Chart/ ASM Chart) Block-level IP .SCH
.VHD/.V/EDIF (.EDF/.EDN ETC.)
.VHD/.VHT/.VHO (VHDL TESTBENCH)

OR .TF (VERILOG HDL TESTBENCH)
RT Level Test Vectors or

Textual Design Stimulus Functional/
Description RT Level/Behavioral
(HDL code (VHDL (Testbench Simulation
or Verilog HDL) (VHDL Testbench
(written at or Verilog Text
Behavioral or Fixture))
Dataflow level)) Assertion Simulation
.VHD (VHDL) OR .V (VERILOG HDL)
Synthesis
Design Constraints (Speed, Area RT Level Synthesis Test Vectors or

Vendor- etc.) Stimulus
supplied or
Third-Party (Testbench
Pre-defined Logic Synthesis (excluding Mapping) (VHDL Testbench
or pre- or Verilog Text
fabricated Fixture))
IP
cell/macro Logic Synthesis (Mapping)
IO constraints
(Location)
.NGD (FOR XILINX (XST)) OR Logic Simulation/
Post-Synthesis
.XNF (FOR XILINX BY THIRD-PARTY)
Technology Cells Simulation
of OR
Target Technology EDIF (.EDN/.EDF) (FOR THIRD PARTY)
For ASIC Implementation
For FPLD Implementation

Layout of Layout of
Target Target
Technology Technology Floorplanning
(ASIC) (FPLD) (for FPGAs)
Test Vectors or
Stimulus Post-Route/Post-Place-
and-Route/Post-
(Testbench Fit/Timing Simulation
Cell Placement Automatic (VHDL Testbench
IO Constraints Place-and-Route/Fitting or Verilog Text
(IO standards,
Fixture)) Static Timing Analysis
IO drive
(STA)
strength etc.)
.NCD (FOR XILINX)
Power Estimation
Design for Test (DFT)
Insertion (i.e. Scan-chain,
JTAG, BIST) and
Automatic Test Pattern Fault
Generation (ATPG) Simulation Standard Delay File
(SDF)
Clock-Tree Insertion Placed-and-Routed/

Fitted
Gate-Level HDL
Model/Netlist
Layout
Cell Routing Simulation
Static Timing Analysis

(STA)
Power Estimation
Forma Verification
(Layout vs. Schematic
(LVS))
Design Rule Check

(DRC)
Layout Parameter
Extraction (LPE)
For ASIC implementation For FPLD Implementation
FPLD Prototype Device Programming/

or FPGA Device Configuration/
Emulation of In-System Programming/
ASIC Download
FPLD Prototype . BIT AND .MCS

(of ASIC) (FOR FPGA AND
Testing and CONFIGURATION MEMORY (PROM/FLASH),
online debugging
RESPECTIVELY)
TAPEOUT OR
GDS II/CIF .JED (FOR CPLD)
Prototype Fabrication
FPLD Prototype Testing

ASIC Prototype FPLD Prototype and online debugging
ASIC Prototype Testing and
online debugging
GDS II/CIF
Fabrication for Device Programming for

Production Production
$$$$$ $$$$$
LEVEL 2 Design Specifications
Select Implementation Style/Technology,

Target Technology,
Package,
Vendor (for IP, EDA tool, target
technology/library) and
Third-party (for IP, EDA tool)
System
Graphical Design Entry

Behavior
(Gate-level or Algorithmic
or Block-level (IP))
(Graphical Description)
Algorithm
and/or
IP Design Descriptions
(Structural Description)
Architecture
.SCH OR EDIF (i.e. .EDF/.EDN)
Generated RT Level RT Level Test Vectors or

Design Description Design Entry Stimulus Functional Simulation/
RT Level Simulation/
(Textual Description) (Textual Description) (Testbench /Behavioral Simulation
(VHDL Testbench
HDL code HDL code or Verilog Text
Fixture))
(VHDL or Verilog HDL) (VHDL or Verilog HDL) .VHD/.VHT/.VHO (VHDL TESTBENCH)
Design Constraints (Speed, Area
etc.)
Vendor-supplied or Third-Party Synthesis Test Vectors or

Pre-defined or pre-fabricated Stimulus Logic Simulation/
IP cell/macro (RTL Synthesis Post-Synthesis
+ (Testbench Simulation
Logic Synthesis) (VHDL Testbench
IO constraints or Verilog Text
(Location) Fixture))
.VHD/.VHT/.VHO(VHDL TESTBENCH)
Technology Cells OR .TF (VERILOG HDL TESTBENCH)
of .NGD (FOR XILINX (XST)) OR
Target Technology .XNF (FOR XILINX BY THIRD-PARTY)
OR EDIF (.EDN/.EDF) (FOR THIRD PARTY)
Layout of Target Layout of Target
Technology Technology
(ASIC) For ASIC Implementation For FPLD Implementation (FPLD)
IO Constraints Cell Placement Floorplanning IO Constraints

(IO standards, IO (IO standards, IO
drive strength (for FPGAs) drive strength
etc.) etc.)
Design for Test

Fault (DFT) Insertion
Simulation and
Automatic Test
Pattern Generation
(ATPG)
Post-Route
Simulation/
Test Vectors or Test Vectors or Post-Place-and-
Layout Simulation Stimulus Stimulus Route/ Simulation/
Post-Fit Simulation/
(Testbench) Clock-Tree (Testbench) Timing Simulation
(VHDL Testbench Insertion (VHDL Testbench
or Verilog Text or Verilog Text
Static Timing Analysis Fixture)) Fixture))
(STA)
.VHD/.TF .VHD/.TF Static Timing
Analysis (STA)
Power Estimation
Placed-and-Routed/ Cell Routing Automatic Placed-and-Routed/
Fitted Place-and-Route Fitted
Gate-Level HDL (PAR)/ Gate-Level HDL
Model/Netlist Fitting Model/Netlist Power Estimation
Design Rule Check
(DRC) GDS II/ CIF .NCD (FOR XILINX)
.VHD (FOR VHDL)/ .VHD (FOR VHDL)/
.V (FOR VERILOG HDL) .V (FOR VERILOG HDL)
Formal Verification
(Layout vs. Schematic) Mask Layout TAPEOUT Standard Delay File
(LVS) Model/Netlist (SDF)
.MSK
.SDF
Standard Delay File
(SDF)
.SDF Device Programming/

Device Configuration/
In-System
Prototype Fabrication Programming/
Download
For Prototype
ASIC Prototype Testing ASIC Prototype FPLD Prototype FPLD Prototype Testing
and online debugging and online debugging

LEVEL 1
Design Specifications
Select
Implementation Style/Technology,
Target Technology,Package,
Vendor, Third-party
System
Behavior
Algorithm
Architecture
Generated RT Level
Design Description
(Textual Description)
HDL code
(VHDL or Verilog HDL) RT Level Test Vectors or
Design Entry Stimulus Functional Simulation/
from RT Level Simulation/
(Textual Description) (Testbench /Behavioral Simulation
Graphical Design Entry/ (VHDL Testbench
IP/EDIF design description HDL code or Verilog Text
(.SCH/EDIF (i.e. .EDF/.EDN)) Fixture))
(VHDL or Verilog HDL) .VHD/.VHT/.VHO (VHDL TESTBENCH)
Design Constraints (Speed, Area
etc.)
Vendor-supplied or Third-Party Synthesis Test Vectors or

Pre-defined or pre-fabricated Stimulus Logic Simulation/
IP cell/macro (RTL Synthesis Post-Synthesis
+ (Testbench Simulation
Logic Synthesis) (VHDL Testbench
IO constraints or Verilog Text
(Location) Fixture))
.VHD/.VHT/.VHO(VHDL TESTBENCH)
Technology Cells OR .TF (VERILOG HDL TESTBENCH)
of .NGD (FOR XILINX (XST)) OR
Target Technology .XNF (FOR XILINX BY THIRD-PARTY)
OR EDIF (.EDN/.EDF) (FOR THIRD PARTY)
Layout of Target Layout of Target
Technology Technology
(ASIC) For ASIC Implementation For FPLD Implementation (FPLD)
IO Constraints Cell Placement Floorplanning IO Constraints

(IO standards, IO (IO standards, IO
drive strength (for FPGAs) drive strength
etc.) etc.)
Design for Test

Fault (DFT) Insertion
Simulation and
Automatic Test
Pattern Generation
(ATPG)
Clock-Tree
Insertion
Cell Routing Automatic

Place-and-Route
(PAR)/ Post-Route
Layout Simulation Fitting Simulation/
Test Vectors or Test Vectors or Post-Place-and-
Stimulus .NCD (FOR XILINX) Stimulus Route/ Simulation/
.MSK Post-Fit Simulation/
Static Timing Analysis (Testbench) (Testbench) Timing Simulation
(STA) (VHDL Testbench (VHDL Testbench
or Verilog Text or Verilog Text
Fixture)) TAPEOUT Fixture))
Power Estimation Static Timing
Analysis (STA)
GDS II / CIF
Design Rule Check Power Estimation
(DRC)
Formal Verification
Device Programming/
(Layout vs. Schematic)
Prototype Fabrication Device Configuration/
(LVS)
In-System Programming/
Download
For Prototype
.BIT and .MCS for FPGA and configuration memory

.JED for CPLD
ASIC Prototype Testing ASIC Prototype FPLD Prototype FPLD Prototype Testing
and online debugging and online debugging

$$$$$ $$$$$
Files Generated by EDA Tools in Top-Down Design Flow
HDL Design EntryÆ VHD or V
Graphical/Schematic Design EntryÆ SCH
IPÆ SCH / EDIF
Testbench or Stimulus Æ VHD OR TF
Logic Synthesis Æ NGD / XNF / EDIF
Automatic Place-and-RouteÆ NCD / EDIF
Device Programming/DownloadÆ BIT (for FPGAs)

JED (for CPLD)
MCS (for PROM/Flash ROM)
(for storage of FPGA configuration bit-stream)
Layout SynthesisÆ MSK / EDIF
TapeoutÆ GDS II / CIF

(for Fabrication)
User Contraints Æ UCF
EDIF Electronic Data Interchange Format (generic)

NGD Xilinx ISE Native Generic Database (Xilinx, Inc.)
XNF Xilinx Netlist Format (Xilinx, Inc.)
NCD Native Circuit Description
BIT Xilinx ISE Bitstream File (Xilinx, Inc.)
JED Xilinx ISE Device Configuration Information (Xilinx, Inc.)
MCS Xilinx ISE Memory Configuration Stream (Xilinx, Inc.)
CIF CalTech Intermediate Graphic
GDS II Graphical Design Standard
MSK
UCF User Constraints File
SDF Standard Delay Format
COMPARISON OF IMPLEMENTATION TECHNOLOGIES:
LAB FPLD BOARDS:
Some of my FPLD boards:

Introduction To VLSI

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Introduction To VLSI

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SHAHRIYAR MASUD RIZVI

© Shahriyar Masud Rizvi, 2006, 2009

2. John P. Uyemura, Introduction to VLSI Circuits and Systems.

3. M. D. Ciletti, Advanced Digital Design with the Verilog HDL.

4. Yu Cao, Arizona State University, AZ, USA.

© Shahriyar Masud Rizvi, 2006, 2009

VLSI-Very Large Scale Integration

VLSI Design or VLSI Circuit Design refers to

There are 2 types of VLSI Circuits-Analogue and

In this course, by VLSI Design or VLSI Circuit

VLSI Circuit Design typically (and in this class)

The discussion typically is at Logic (Gate), Circuit

Integration simply means more devices per chip.

© Shahriyar Masud Rizvi, 2006, 2009

Digital VLSI Circuit Design

Implementation Technologies (Full-Custom design and Semi-Custom design including

Digital Logic Design

Practical Aspects Relevant Courses

Combinational Logic Design: Adders, Multipliers, Multiplexers, ALUs etc.

System-level, Architecture-level, Register Transfer (RT) Level design.

Computer Architecture (Architecture Level)

VHDL (or Verilog) Modeling and Synthesis (RT-Level)

© Shahriyar Masud Rizvi, 2006, 2009

Clock Generators and Clock Buffers

Clock Synchronizers, Clock Managers, Clock Tree Insertion

Test Synthesis, Fault Analysis, Scan-chain

Logic-Level (Gate-Level), Circuit-Level (Transistor-Level) and Physical Design

VLSI Circuit Design

© Shahriyar Masud Rizvi, 2006, 2009

Hardware + Software, SOC

Bus Functional Model

(High-Level) Algorithmic C, C++, System C, SystemVerilog

Circuit Level SPICE, Verilog-AMS, VHDL-AMS,Verilog-A

© Shahriyar Masud Rizvi, 2006, 2009

Circuit Level SPICE, Verilog-AMS, VHDL-AMS, Verilog-A

© Shahriyar Masud Rizvi, 2006, 2009

Full-Custom Chip (FCC) Design

Register Transfer Level Design Front-end Design

Physical Design (Mask Design/Layout Design) Back-end Design

Semi-Custom Chip (ASIC/FPLD) Design

Register Transfer Level Design Front-end Design

Physical Design (Mask Design/Layout Design) Back-end Design

© Shahriyar Masud Rizvi, 2006, 2009

© Shahriyar Masud Rizvi, 2006, 2009

Example of designing at various Levels of Abstraction:

1-bit, 2-to-1 Multiplexer (Mux):

Pass A when Sel is 1.

© Shahriyar Masud Rizvi, 2006, 2009

Let us select the following simple architecture

© Shahriyar Masud Rizvi, 2006, 2009

Algorithmic Level (Algorithm):

FOR SEMI-CUSTOM CHIPS (FPLDS/ASICS)

BOOLEAN EQUATIONS SUITABLE FOR LOGIC-LEVEL

Y = Sel . A. B + Sel . A. B + Sel . A. B + Sel . A. B

FOR FULL-CUSTOM CHIPS

BOOLEAN EQUATIONS SUITABLE FOR CIRCUIT-LEVEL

Y = Sel . A. B + Sel . A. B + Sel . A. B + Sel . A. B

© Shahriyar Masud Rizvi, 2006, 2009

Register Transfer (RT) Level:

VHDL Verilog HDL

ENTITY Mux_1Bit_2_to_1 IS module Mux_1Bit_2_to_1(Sel,A,B,Y);

PROCESS (Sel, A, B) always @ (Sel or A or B)