INSTRUCTION CYCLE, MACHINE CYCLE AND T-STATE:

Instruction Cycle is defined as the time required to complete the execution of an

instruction. The 8085 instruction cycle consists of 1 to 6 machine cycles or 1 to 6 operations.
Machine cycle is defined as the time required to complete one operation of accessing
memory, I/O or acknowledging an external request. This cycle may consist of 3 to 6 T-states.
T-state is described as one subdivision of the operation performed in one clock period.
These subdivisions are internal states synchronized with the system clock, and each T-state is
precisely equal to one clock period. The terms T-state and clock period are often used
synonymously.

Instruction cycle can be divided into a number of machine cycles by the MPU. And
machine cycle is divided into a number of T states by the MPU.
The common machine cycles are:
1. Opcode Fetch
2. Memory Read
3. Memory Write
4. I/O Read
5. I/O Write

Opcode Fetch Machine Cycle:

Here we illustrate the steps and the timing of data flow when the instruction code 0100 1111
(4F – MOV C, A) stored in location 9005 is being fetched.
To fetch the byte 4F, the MPU needs to identify the memory location 9005 and enable the
data flow from memory. This is called the Fetch cycle. The dataflow is shown in following
Figure, and the timings are explained below:

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 Internal Data Bus

ALU Instruction B C 9005 4F

Decoder
D E ⁞
H L
SP
Control PC
Logic
Address Bus

RD′

Figure: data flow from memory to MPU

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 Next figure shows the timing of how a data byte is transferred from memory to the MPU; it
shows five different groups of signals in relation to the system clock. The address bus and data
bus are shown as two parallel lines. This is a commonly used practice to represent resent logic
levels of groups of lines: some lines are high and others are low. The crossover of the lines
indicates that a new byte (information) is placed on the bus and a dashed straight line indicates
the high impedance state. To fetch the byte, the MPU performs the following steps:

Step 1: The MPU places the 16-bit memory address from the PC on the address bus.
Next Figure shows that at T1 the high-order memory address 90, is placed on the address
lines A15 – A8, the low-order memory address 05 is placed on the bus AD7 – AD0 and the ALE
signal goes high. Similarly, the status signal IO / M′ goes low, indicating that this is a memory-
related operation.
Step 2: The control unit sends the control signal RD′ to enable the memory chip.
The control signal RD′ is sent out during the clock period T2, thus enabling the memory chip.
The RD′ signal is active during two clock periods.

Step 3: The byte from the memory location is placed on the data bus
When the memory is enabled, the instruction byte (4F) is placed on the bus AD7 – AD0
and transferred to the microprocessor. The RD′ causes 4F to be placed on bus AD7 – AD0
(shown by the arrow), and when RD′ goes high, causes the bus to go into high impedance.

Step 4: The byte is placed in the instruction decoder of the microprocessor and the
task is carried out according to the instruction.
The machine code or the byte (4F) is decoded by the instruction decoder the contents of
the accumulator are copied into register C. This task is performed during the period T4 in Figure.

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 Opcode Fetch Machine Cycle

T1 T2 T3 T4

9005: 4F
A15
90 90
A8

AD7
05 4F
AD0

ALE

RD′

Timing Diagram of the Instruction: MOV C A

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 M1 (Opcode Fetch Machine Cycle)

T1 T2 T3 T4

9005: 3E
A15 9006: 57
90 90
A8

AD7
05 3E
AD0

ALE

RD′

Timing Diagram of the Instruction: MVI A 57 (continued to next page)

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 M2 (Memory Read Machine Cycle)

T5 T6 T7

A15
90 90
A8

AD7
06 57
AD0

ALE

RD′

Timing Diagram of the Instruction: MVI A 57 (continued from previous page)

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 M1 (Opcode Fetch Machine Cycle)

T1 T2 T3 T4

9005: 32
A15 9006: 80
90 90
A8 9007: 95

AD7
05 32
AD0

ALE

RD′

Timing Diagram of the Instruction: STA 9580 (continued to …)

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 M2 (Memory Read Machine Cycle)

T5 T6 T7

A15
90 90
A8

AD7
06 80
AD0

ALE

RD′

Timing Diagram of the Instruction: STA 9580 (continued from and to)

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 M3 (Memory Read Machine Cycle)

T8 T9 T10

A15
90 90
A8

AD7
07 95
AD0

ALE

RD′

Timing Diagram of the Instruction: STA 9580 (continued from and to)

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 M4 (Memory Write Machine Cycle)

T11 T12 T13

A15
95 90
A8

AD7
80 (A)
AD0

ALE

WR′

Timing Diagram of the Instruction: STA 9580 (continued from)

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 Commonly used Machine cycles in 8085 are:

OF – Opcode Fetch Machine Cycle

SF – Opcode Fetch (Special) Machine Cycle
MR – Memory Read Machine Cycle
MW – Memory Write Machine Cycle
IOR – I/O Read Machine Cycle
IOW – I/O Write Machine Cycle
BI – Bus Idle Machine Cycle
IA – Interrupt Acknowledge Machine Cycle

Some Instructions with Machine Cycles and T-states are shown below:
Instruction No. of Bytes Machine Cycles Total No. of T states
MOV A, B 1 OF(4) 4
MOV A, M 1 OF(4) MR(3) 7
MOV M, A 1 OF(4) MW(3) 7

MVI A, 45 2 OF(4) MR(3) 7

MVI M, 45 2 OF(4) MR(3) MW(3) 10

LXI H 9000 3 OF(4) MR(3) MR(3) 10

LDA 9000 3 OF(4) MR(3) MR(3) MR(3) 13
STA 9000 3 OF(4) MR(3) MR(3) MW(3) 13
IN 90 2 OF(4) MR(3) IOR(3) 10
OUT 90 2 OF(4) MR(3) IOW(3) 10

INR C 1 OF(4) 4
DCR C 1 OF(4) 4
INR M 1 OF(4) MR(3) MW(3) 10
DCR M 1 OF(4) MR(3) MW(3) 10

INX H 1 SF(6) 6
DCX H 1 SF(6) 6

JMP 9000 3 OF(4) MR(3) MR(3) 10

JNZ 9000 3 OF(4) MR(3) MR(3) / OF(4) MR(3) 10 / 7
CALL 9000 3 SF(6) MR(3) MR(3) MW(3) MW(3) 18
RET 1 OF(4) MR(3) MR(3) 10
RST1 1 SF(6) MW(3) MW(3) 12

PUSH B 1 SF(6) MW(3) MW(3) 12

POP 1 OF(4) MR(3) MR(3) 10

HLT 1 OF(4) BI(1) 5

Table: Some Instructions with Machine Cycles and T-states

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Find total time to execute following program if Microprocessor Clock Frequency is 2 MHz.

LXI B 0203
MVI A 00
ADD B
ADD C
STA 9000
HLT

Find total time to execute following program if Microprocessor Clock Frequency is 3 MHz.

LXI B 0203
MVI A 00
ADD B
ADD C
STA 9000
HLT

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COUNTER AND TIME DELAYS:

Steps:
 A counter is designed simply by loading appropriate number into one of the registers and
using INR or DNR instructions
 Loop is established to update the count.
 Each count is checked to determine whether it has reached final number; if not, the loop
is repeated.

Time Delay procedure is used to design a specific delay. A register is loaded with a number,
depending on the time delay required and then the register is decremented until it reaches zero by
setting up a loop with conditional jump instruction

Time Delay using one Register:

Find total time to execute following program if Microprocessor Clock Frequency is 2 MHz.

LABEL OPCODE OPERAND COMMENTS

START MVI C, FF Load Register C
LOOP DCR C Decrement C
JNZ LOOP Halt the program

Method 1:

Total No. of T-states:

7 + (4*255 + 10*254 + 7*1) = 3574

Method 2:

Total No. of T-states:

7 + ((4+10)*255−3) = 3574

Time required = (3574 * 0.5) micro seconds

= 1787 micro seconds
= 1.787 milli seconds

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Time Delay using a Register Pair:

LABEL OPCODE OPERAND COMMENTS

START LXI B, FFFF Load BC with 16-bit count
LOOP DCX B Decrement BC by 1
MOV A, C Place contents of C in A
ORA B OR B with C to set Zero flag
JNZ LOOP If result is not equal to 0, jump back to loop

Total No. of T-states:

10 + (6+4+4+10)*65535−3 = 1572847

Time required = (1572847 * 0.5) micro seconds

= 786423.5 micro seconds
= 786.4235 milli seconds
= 0. 7864235 seconds

If, Microprocessor clock frequency is 3 MHz, then

Time required = (1572847 * 0.33) micro seconds
= 519039.51 micro seconds
= 519.03951 mili seconds
= 0.51903951 seconds ≈ 0.5 seconds

[So if we use this delay routine 2 times, we can generate a delay of about 1 second]

Time Delay using a Loop within a Loop:

LABEL OPCODE OPERAND COMMENTS

START MVI B, 38 Load B
LOOP2 MVI C, FF Load C
LOOP1 DCR C Decrement C by 1
JNZ LOOP1 If result is not equal to 0, jump back to inner loop
DCR B Decrement B by 1
JNZ LOOP2 If result is not equal to 0, jump back to outer loop

This is assignment of students to calculate

total time to execute this delay routine

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