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Electronic hardware design of electrical capacitance tomography systems

Article  in  Philosophical Transactions of The Royal Society A Mathematical Physical and Engineering Sciences · June 2016
DOI: 10.1098/rsta.2015.0331

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Research
Cite this article: Saied I, Meribout M. 2016
Electronic hardware design of electrical
capacitance tomography systems. Phil. Trans.
R. Soc. A 374: 20150331.
http://dx.doi.org/10.1098/rsta.2015.0331
Accepted: 22 February 2016
One contribution of 10 to a theme issue
‘Super-sensing through industrial process
tomography’.
Subject Areas:
electrical engineering
Keywords:
electrical capacitance tomography,
tomography, capacitive sensors, capacitance
measurement, fast data acquisition
Author for correspondence:
M. Meribout
e-mail: mmeribout@pi.ac.ae
Electronic hardware design of
electrical capacitance
tomography systems
I. Saied and M. Meribout
Department of Electrical Engineering, Petroleum Institute,
Abu Dhabi, United Arab Emirates
IS, 0000-0002-0204-0626; MM, 0000-0002-0058-1090
Electrical tomography techniques for process imaging
are very prominent for industrial applications, such
as the oil and gas industry and chemical refineries,
owing to their ability to provide the flow regime of
a flowing fluid within a relatively high throughput.
Among the various techniques, electrical capacitance
tomography (ECT) is gaining popularity due to its
non-invasive nature and its capability to differentiate
between different phases based on their permittivity
distribution. In recent years, several hardware designs
have been provided for ECT systems that have
improved its resolution of measurements to be around
attofarads (aF, 10−18 F), or the number of channels,
that is required to be large for some applications that
require a significant amount of data. In terms of image
acquisition time, some recent systems could achieve
a throughput of a few hundred frames per second,
while data processing time could be achieved in only
a few milliseconds per frame. This paper outlines
the concept and main features of the most recent
front-end and back-end electronic circuits dedicated
for ECT systems. In this paper, multiple-excitation
capacitance polling, a front-end electronic technique,
shows promising results for ECT systems to acquire
fast data acquisition speeds. A highly parallel field-
programmable gate array (FPGA) based architecture
for a fast reconstruction algorithm is also described.
This article is part of the themed issue ‘Super-
sensing through industrial process tomography’.
1. Introduction
Electrical capacitance tomography (ECT) is a technique
used to obtain information about the spatial distribution
of a mixture of dielectric materials inside a vessel or
2016 The Author(s) Published by the Royal Society. All rights reserved.
pipeline, by measuring the capacitance between a set of electrodes placed around its periphery
2
and converting them into an image showing the distribution of permittivity. ECT systems have
been extensively used in industry for monitoring non-conductive processes in oil, gas and

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chemical industries. ITS’s m3c ECT instrument is among the more recent commercially available
devices that has been used in multiphase flow applications [1]. The m3c instrument has an
accuracy of 0.01–1 picofarads (pF) and a data acquisition speed of up to 50 frames per second.
Atout Process is another company that makes cutting-edge multiphase flowmeters based on ECT
systems [2]. Although their products are not commercially available yet, significant research and
tests have been successfully performed on their devices. In one such test, 4 kg of wheat was
released through the sensor pipe in order to simulate the flow of dispersed solids. Using gravity-
driven flow, researchers were able to measure the concentration of the particles and velocity with
an uncertainty that was in the range of ±1 to ±3% [2]. The detection of the granular substance
of wheat in this case proves that ECT systems have the potential capability to handle and detect
other important granular substances such as black powder and/or sand detection in gas pipelines.
The ability of high-speed imaging and non-invasiveness make ECT ideal for industrial
processes that involve fast-moving or changing materials. A typical AC-based ECT system
using phase-sensitive demodulation could achieve a data acquisition speed of 140 frames s−1
(for a 12-electrode sensor) [1]. The authors claim that the throughput can be increased to up
to 1000 frames s−1 if faster electronics is selected. Another ECT system based on a differential
sampling method could achieve a throughput of 800 frames s−1 (for a 12-electrode sensor) [3].
The measured capacitance is only charged and discharged once in one measurement cycle.
There is no noise at the output of the measurement circuit and a parallel detecting scheme is
implemented in the system so that the data acquisition time can be reduced [3,4]. The hardware of
the AC-based ECT systems consists mainly of analogue electronics that makes the design process
challenging for measuring very low capacitance values. Recently, the development of digital
signal processor technology has paved the way to another purely digital measurement solution,
namely the digital to capacitance converter technique, which can provide very high-sensitivity
measurements with a much easier hardware design. A recent study was carried out in paper [5]
where the data acquisition unit used is a commercial PTl300E-TP-G capacitance measurement unit
that has the ability to collect sets of capacitance data at 100 frames s−1 with an effective resolution
of 0.1 femtofarads (fF) and measurement noise level better than 0.07 fF [5].
Although ECT systems have been studied extensively, research is still ongoing to find an
optimal system design that contains a faster sampling rate and creates higher-quality images.
In order to design such a system, efforts are being made on both the front-end electronics and
back-end processing units. The outline of this paper is as follows: §2 will discuss the overview
of the ECT system and its overall functionality. Section 3 will focus on the front-end electronics
for ECTs and provide recent technologies that have been researched for this field. Section 4 will
discuss the back-end processing unit for ECTs and the different algorithms that have been used
for image reconstruction. Finally, §§5 and 6 contain the discussion and conclusion for this paper.

2. Overview of an electrical capacitance tomography system

Figure 1 shows the overall hardware structure of an ECT probe system [7]. It consists of
three subsystems: the primary capacitance sensor, which comprises a set of multiple electrodes
surrounding the object under measurement; a front-end capacitance measurement electronics,
which includes a capacitance measurement circuit and a multiplexing–demultiplexing unit to
perform the measurements in a time-multiplexed manner; and a back-end processing unit for
high-level control and execution of the reconstruction algorithm within a predefined time. The
electrodes are usually made of highly conductive materials such as copper or gold. The electrodes’
dimensions and geometry depend on the volume of the target medium, in addition to the ECT
space dimension (e.g. two- or three-dimensional ECT system). For a regular 4 inch pipeline two-
dimensional ECT system, eight electrodes of dimensions around 1 cm width and 10 cm length
have been successfully used and tested [1,8]. Figure 2 shows a top-down view of how the
 pipeline with electrodes front-end electronics back-end processing unit
3
capacitance measurement module

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the multiplexer

.........................................................
communications
module

analogue signal
data collection
and control modules digital signal
excitation signal

Figure 1. Hardware system overview of ECT system [6].

4 3
pipeline
5 2

6 1
electrodes

outer
screen 7 12

guard
electrode 8 11
9 10

Figure 2. Top-down view of electrode layout on pipeline [9].

electrodes are arranged in a pipeline for a typical 12-electrode ECT system. Depending on the
application, the electrodes are either put in direct contact with the process or protected by a thin
non-conductive insulation layer. Possible cross talk which may occur between the electrodes is
eliminated by using safeguard shielding electrodes, which are placed between adjacent electrodes
(figure 2).

3. Front-end measurement electronics system

(a) Capacitance measurement circuits
Depending on the dielectric values of the medium and the dimensions of its field of view,
the value of capacitances between pair of electrodes can be of attofarad (aF, 10−18 F) order.
This is a challenging requirement that many researchers have tried to tackle within the fastest
possible data acquisition time. In order to achieve this measurement constraint, researchers have
tried integrating signal-modifying components, such as charge amplifiers and filters, in order to
amplify the signal and remove the noise so that the essence of the aF readings can be detected
properly. The front-end measurement system is controlled by the back-end unit, which initiates
the measurement process and receives data back for further processing. The following subsections
discuss some of the most recent designs which have been disclosed in the literature.

(i) Modified capacitance measurement circuit with clocking scheme

In [10], a synchronous capacitance measurement circuit was proposed. Its main feature is to
reduce the effect of stray capacitances by using two capacitance measurement modules that are
exactly the same. However, only one is connected to a sensor under measurement. Figure 3 shows
 capacitance 4
sensor measuring

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circuit
differential
amplifier
capacitance
measuring
circuit

Figure 3. Circuit configuration to eliminate stray capacitance [10]. (Online version in colour.)

Q3 Q4 Q6 bias

output

clk1 Q1 Q7

sensor
clk1
connection

clk2 Q2 Q5 C1
clk2

~50–100 ns

Figure 4. Measurement circuit diagram and clocking scheme of circuit [10]. (Online version in colour.)

the block diagram of this circuit configuration. The capacitance measurement circuit operates
synchronously according to an external clock signal, clk1 (figure 4). Another clock signal, clk2, is
used to reset the circuit for another measurement cycle.
As clk1 goes low, transistor Q1 switches on. This causes the sensor capacitance and any
associated stray capacitances to charge. The charging current then passes through the transistor
Q3, and is mirrored in Q4, which charges a reference capacitor, C1. The voltage across C1 will
be proportional to the sensor capacitance and associated strays. In order to eliminate the effect
of stray capacitances, a second, identical circuit is employed and then compared to the previous
circuit, using a differential amplifier, to detect and remove any stray capacitance that is present in
the measurement circuit. The second measurement circuit is not connected to a sensor; therefore,
the output of this circuit is proportional only to the stray capacitance. The outputs from both
these circuits are subtracted using a differential amplifier. If both circuits are identical and well
matched (a common assumption in integrated circuit design), then the stray capacitances should
be identical, and should cancel, leaving an output that is purely proportional to the sensor
capacitance [10]. When clk2 goes high, the circuit is reset and ready for the next measurement
signal. Figure 4 shows a block diagram representation of this circuit along with the clocking
scheme for clk1 and clk2, respectively.
Simulations have shown that the circuit is reasonably linear when the capacitance change is
between −0.6 and 0.9 fF [10]. The negative value of the capacitance is due to the flow of charge
in the opposite direction. The measurement sensitivity in the linear region was approximately
 capacitance 5
sensor measuring

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.........................................................
circuit
differential
amplifier
capacitance
sensor measuring
circuit

Figure 5. Configuration of sensors and capacitance measuring circuit connected to a differential amplifier [10]. (Online version
in colour.)

1.6 V fF−1 . This can be compared to the sensitivity predicted by the equation

W3 L4 (VDD − |VT |)
V = ±K C. (3.1)
L3 W4 CINT

The nonlinearity for larger capacitance changes is due to the differential amplifier. The circuit
settles very quickly, and thus operation at frequencies greater than 2 MHz is possible. Given
the gain of the differential amplifier and the capacitance of the reference capacitor, the predicted
sensitivity of the circuit is 1.75 V fF−1 , which is in good agreement with the simulation’s result [10].
Another design that is discussed in the same paper [10] is a potentially more useful
configuration where each sensor is connected to its corresponding capacitance measuring
circuit and then channelled to a differential amplifier for comparison. Figure 5 illustrates the
configuration of this circuit.
In this scenario, the effect of stray capacitance is subtracted from the output as well as the
standing sensor capacitance. This configuration is beneficial as it allows the circuit gain to be
increased, thus allowing small capacitance changes to be measured more accurately. However,
one problem is that the circuits involved in driving the signal from the chip can limit the operating
frequency of the device and therefore affect the accuracy of the capacitance readings. Another
issue with this design is that reference capacitors must be well matched (both geometrically and
physically) in order for the circuit to be implemented successfully [10]. This is because stray
capacitances have to be sufficiently similar in both circuits to cancel each other out. Extensive
research is still required to understand the integrity of this circuit further.

(ii) Sigma-delta converter circuit

In [11], another approach using a sigma-delta converter was suggested. A sigma-delta converter
is a one-bit analogue-to-digital converter formed by running the measurement signal through
an integrator and then a comparator. Feedback is routed to a summing node on the input to the
integrator to try and balance the input that leads to the comparator. The difference (delta) between
the reference and input signals is coded by the comparator. The output of the comparator is tied
to a counter to keep track of the number of times the comparator has a logic ‘1’ output that is
received [11]. Another counter is used to keep track of the number of clock cycles. This counter is
what gives the circuit the ‘sigma’ name, which represents the summing part the circuit. Figure 6
shows a diagram of the circuit for a simple sigma-delta converter.
The measurement of the input signal is the ratio of the two counters multiplied by the reference
voltage. Extensive digital signal processing is done on the output to remove noise and extend the
resolution of the signal. The benefit of this technology is that high resolutions are achievable, but
at the cost of slower acquisition rates. When receiving a voltage input, a sigma-delta converter
uses a reference capacitor in series with the reference voltage and another in series with the input
 feedback
6
phase

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.........................................................
VREF(+) CREF

VREF(–) CINT
clock clock

VIN(+) CIN
digital
VIN(–) filter
0100110
integrator comparator

Figure 6. Simple sigma-delta converter circuit for capacitance measurement [11]. (Online version in colour.)

Ss1 Ss3 Uex

Ss2
electrode

Rf

Cf
Sm1 2
Sm3 –
6 OUT
out
Sm2 3 +

Figure 7. Input circuit for charge amplifier connection [12].

signal. The conversion time for this circuit ranges from 11 to 122 ms depending on capacitive
input noise, voltage input noise and resolution.
The EVAL-AD7746 evaluation kit, which is a sigma-delta converter, from Analog Devices, was
used in this study for measuring and populating the capacitance matrix for the three-dimensional
ECT system [11]. The dynamic range of the AD7746 is ±4 pF, which is well suited for ECT
measurements. It can also compensate 17 pF of common mode capacitance. Both ranges can be
extended by adding a low-noise op amp and two 1% resistors to expand the ranges by a factor of
10.57, allowing for common mode compensation of 179.7 pF and a range of ±42.3 pF. In addition,
AD7746 is also capable of resolving down to 4 aF [7]. However, the downside of this chip is
that reducing the excitation voltage increases the noise by the same factor. In [11], a scenario
is discussed where the excitation signal is reduced by a factor of 10.57, and the noise is increased
by the same factor. As a result, the resolution changed from 4 to 42 aF. Compared to the approach
in paper [9], the sigma-delta converter has a much higher resolution and sensitivity; however, the
acquisition rate is much slower. Therefore, this circuit would not be ideal for applications that
require real-time monitoring and operations.

(iii) Improved AC-based electrical capacitance tomography hardware

An improved AC-based ECT hardware design is described in paper [12], which is a modification
of the hardware that was developed by He et al. [13]. Figure 7 shows the input circuit for the
charge amplifier connection and a modified charge amplifier with switching feedback.
In figure 7, six switches are split into two sets: Ssi and Smi, respectively (where i = 1, 2 or 3). The
switches are used to configure the attached electrodes to either excitation mode or measurement
 Rf 2
7
Csw

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.........................................................
Rf1 Sf1
Csw

Cf Sf 2
Csw
2 Sf 3
–
IN
out 6

3 OUT
+

Figure 8. Charge amplifier with switching feedback [12].

mode. In the former mode, the switches Sm1 and Sm3 are in OFF position and switches Ss1,
Ss2 and Ss3 are in ON position. In this configuration, the electrode is directly connected to the
power supply and is therefore being excited. When the electrode is set to measurement mode,
the above switches are set to the opposite positions, thus allowing the electrode to connect
with the charge amplifier. Finally, switches Sm2 and Sm3 allow the output voltage to decrease
significantly by minimizing the parasitic current flowing to the input of the charge amplifier [12].
In AC-based ECT hardware, the current-to-voltage conversion is performed by using a charge
amplifier because its sensitivity can be modified to be high. Usually, AC-based ECT circuits can
handle high-frequency signals of up to 10 MHz. Unfortunately, this causes relatively large stray
capacitances to be present in the circuit.
There are situations where the tomography is desired to work in other modes other than for
capacitance measurement; for example, to allow resistance or conductance measurements to be
done. The solution shown in figure 7 is not useful for this requirement because of the need to
significantly decrease the sensitivity of the input circuit [12]. Another solution that has been
proposed in [12] is to use additional switches to remove the coupling effect from the Csw . This
solution is shown in figure 8 with switches Sf 2 and Sf 3 being implemented.
This circuit can be used to switch feedback up to 14 MHz, and therefore allow the hardware to
change the sensitivity of the input circuit for all frequencies used in ECTs. The following plot in
figure 9 shows the frequency dependence of charge amplifier sensitivity, using different feedback
switching circuits [12].
As shown in figure 9, the frequency circuit for figure 8 (represented by the dashed curve in
figure 9) can be used to switch feedback up to 14 MHz, which is very promising. This also depends
on whether one feedback resistor is used or not, which is detailed in [12]. Although details on
this system are very promising, information such as response time, range of measurement and
accuracy were not provided. Extensive research should be taken to obtain this information in
order to understand more about the functionality and integrity of this system and how well it
would fit into ECT systems that are used in heavy industries.

(b) Multiplexing–demultiplexing circuits

In ECT systems, each electrode can operate in measurement mode, excitation mode or idle
mode (floating). The electrodes are connected to either a source of voltage or capacitance
measurement circuit through a set of switches that form multiplexing and demultiplexing
circuits. The capacitance measurement circuit in turn can process one or simultaneously several
channels to allow faster data acquisition, which usually comes at the expense of a more complex
multiplexing–demultiplexing hardware.
 8

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.........................................................
10

S (V pF–1)
10–1
feedback with one resistor Rf1
feedback with T-switch
feedback with simple switch
10–2

103 104 105 106 107

fex (Hz)

Figure 9. Frequency dependence of charge amplifier sensitivity, S, for circuits in figures 7 and 8 [12].

lock-in
amplifier 1
electrode control modules

2
1 3 lock-in
amplifier 2
8 4

7 5 DAQ
6 PCI
lock-in
amplifier 7

receiving lock-in
1 ~ 7 f1 amplifier 8
synchronization
waveform
8 (one channel)
excitation generator

Figure 10. Schematic diagram of SEMR system [15]. (Online version in colour.)

(i) Single-excitation capacitance multiplexer–demultiplexer

One approach to designing a multiplexing–demultiplexing circuit has been described in [14] that
focuses on a single-excitation capacitance measurement system. The single-excitation multiple-
receiving (SEMR) system focuses on exciting one electrode and then using the remaining floating
electrodes as detectors. The received signals are independently processed by the lock-in amplifiers
(LIAs) and pre-amplifier in each receiving channel. The individual inter-electrode capacitance is
calculated from the magnitude ratio of excitation signal to received signal. Figure 10 shows the
schematic diagram of an SEMR circuit used for capacitance measurement.
As shown in figure 10, all the electrodes are equipped with an electrode control module (ECM)
and an LIA. The latter is synchronized with the excitation source through its corresponding
wavelength. As a result, each of the electrodes selected as a receiving channel will extract
capacitance-related information in parallel [15]. Therefore, for an M-electrode ECT sensor, a
maximum of (M − 1) capacitance values can be measured simultaneously. An advantage of the
SEMR method is that it can reduce the total number of measurements to be recorded in each
 lock-in amplifier 1 9
lock-in amplifier 2

electrode control modules

lock-in amplifier 3

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8 to 4 analogue router

.........................................................
2
1 3 lock-in amplifier 4
8 4
LIA array A PCI

7 5
DAQ
6 LIA array B

LIA array C
receiving
5 ~ 8 f1 LIA array D
1 ~ 4 f2
excitation
f3
waveform synchronization
f4 (four channels)
generators

Figure 11. Schematic diagram of an MECaP system [15]. (Online version in colour.)

scanning cycle by a factor of (M − 1) × (M − 2)/2. This means that the reduction in the number of
measurements is proportional to the square of the parameter M, which is the number of electrodes.
As a result, with the increase of electrodes in the sensor, the scanning speed in frames per second
can be significantly increased [14].
The synchronization method has been extensively used in several research studies. One
study discusses the development and simulation of an ECT system that was used to cross-
correlate tomogram images between downstream and upstream planes [16]. The cross-correlating
technique is beneficial in this study and was used to measure the velocity field in the area of
multiphase flows.

(ii) Multiple-excitation capacitance polling

Another design approach of strong interest is the method of multiple-excitation capacitance
polling (MECaP) for enhanced ECT [14]. This is an apparatus that applies multiple excitation
signals to multiple electrodes at each time instant, thus enabling simultaneous measurement of
inter-electrode capacitance, and improving the efficiency of AC-based ECT systems [14]. Figure 11
shows a schematic illustration of an MECaP system.
For each of the electrode sensors, there is an ECM that controls the connection of a dedicated
ECT sensor either to one of the excitation sources or to the receiving channel. The diagram of this
specific module can be seen in figure 12.
Four function generators are used to create sinusoidal wave signals set at specific frequencies
to excite the electrodes. When the signal reaches the ECM modules for the desired electrodes, it
will set its state to be excited and thus apply a voltage to the electrodes simultaneously. The rest
of the electrodes will be set in the receiving state. The output signals detected by the receiving
electrodes are routed into the ECM module and then sent through a charge pre-amplifier that
amplifies the signal.
This amplified signal is then put into an 8 to 4 multiplexer that is used to route incoming mixed
signals before they are processed by the LIAs. The multiplexer also helps to avoid shortening of
the ECM’s output. From the multiplexer, the combined signal is then passed on to the LIA. The
LIA consists of a low-pass filter, phase shifter and an analogue multiplier that are designed to
filter the incoming signal according to its specified frequencies through synchronization with
the corresponding function generators. The LIA breaks down the signal into each component,
removes the noise, and then converts the AC signal amplitude to DC voltages that can then be
 ECM1, excitation ( f1,V ) ECM8, receiving 10
digital microcontroller digital Rf

to MUX
control logic (ATMEGA128L) control logic

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.........................................................
Cf

VECM
to MUX

pre-amplifier pre-amplifier
C18 C78
... ...
Ron i1 8 Ron
1 7
C28
... f1 2 6 f1 ...
f2 f2
... 3 5
to MUX

i8 ...
... 4
f8 f8
...
...
ECM2, excitation ( f2, V)
i2
... ...
ECM7, excitation ( f7, V)

Figure 12. Internal diagram of ECM for MECaP system [15]. (Online version in colour.)

sent to a PC via the data acquisition system (DAQ). The following sequence is used in the MECaP
system during the data acquisition [14]:

(1) Simultaneously applying k AC excitation signals, each of a different frequency, to N

respective electrodes in an ECT sensor with M electrodes (N ≤ M − 1).
(2) Detecting the signals from each of the N excited electrodes with one of the remaining
electrodes (M − N).
(3) Filtering the received signals with a bank of N band-pass filters whose central frequencies
are tuned to each of the different frequencies ( f1 , . . . , fN ).
(4) Calculating the individual inter-electrode capacitance from either the ratio of the
excitation signal magnitude to that of the received signal or phase changes in the received
signal [14].

Table 1 lists the scanning speeds for different measurement techniques and numbers of electrodes
that have been excited simultaneously (Nmax ). The maximum scanning speeds using MECaP and
traditional AC techniques are calculated using optimal time per measurement values [15]. In
table 1, Nmax refers to the number of excited electrodes that have been excited simultaneously.
As can be seen, when the number of simultaneously excited electrodes, N, approaches the upper
limit, Nmax = M − 1, the maximum scanning speed increases from about two to eight times that
of traditional AC techniques [14].
Based on the above design, the authors of paper [14] successfully created a MECaP system
that generated faster and accurate image results [15]. The MECaP system has a good sensitivity
that enabled it to measure values of capacitance in the range of picofarads (pF). The circuit was
designed to remove stray capacitance by placing the ECM modules very close to the electrodes.
The results show that the measurement error difference between the MECaP and traditional ECT
system was less than 6%. This shows that MECaP is generating similar images as the traditional
ECT system, but much faster than before.

(c) Back-end electronics in electrical capacitance tomography systems

In designing the back-end processing unit for the ECT system, focus is put on building and
implementing a robust algorithm that will process the input capacitance data and reconstruct an
Table 1. Maximum scanning speeds achieved with different ECT techniques [14].
11
M(K)

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.........................................................
8(0) 12(0) 16(0) 44(4)

H 28 66 120 66
traditional no. measurements/frame 28 66 120 66
...........................................................................................................................................................

method max. speed (frame s−1 ) 2357b 1000b 550b 1000b

..........................................................................................................................................................................................................

MECAP no. measurements/frame 15 34 61 44

...........................................................................................................................................................
−1
Nmax = 2 max. speed (frame s ) 4400 1941 1082 1500
...........................................................................................................................................................

increase (%) 187 194 196 150

..........................................................................................................................................................................................................

MECAP no. measurements/frame 11 23 41 33

...........................................................................................................................................................
−1
Nmax = 3 max. speed (frame s ) 6000 2870 1610 2000
...........................................................................................................................................................

increase (%) 254 286 293 200

..........................................................................................................................................................................................................

MECAP no. measurements/frame 9 18 32

...........................................................................................................................................................

Nmax = 4 max. speed (frame s−1 ) 7333 3667 2063

...........................................................................................................................................................

increase (%) 311 366 374

..........................................................................................................................................................................................................

MECAP no. measurements/frame 8 16 26

...........................................................................................................................................................
−1
Nmax = 5 max. speed (frame s ) 8250 4125 2530
...........................................................................................................................................................

increase (%) 350 413 460

..........................................................................................................................................................................................................

MECAP no. measurements/frame 7 11 15 33

...........................................................................................................................................................
−1
Nmax = M − 1 a
max. speed (frame s ) 9429 6000 4400 2000
...........................................................................................................................................................

increase (%) 400 600 800 200

..........................................................................................................................................................................................................
a For grouped electrodes, N
max = K − 1.
b The maximum scanning speeds for the traditional AC method were calculated by referring to reported optimal time per measurement values.

image of the pipe successfully. Software tools and programming languages, such as Matlab and
Microsoft Visual Studio C#, have been used to build and run these algorithms [7]. Many image
reconstruction algorithms, such as Linear Back Projection (LBP), Landweber (LW), Modified
Landweber (MLW) and Adaptive Differential Evolution (ADE), are used to take the capacitance
data and create an image matrix that can display the contents of the pipeline. These algorithms
are continuously being studied by researchers in order to assess the accuracy of the reconstructed
images, and find ways to improve these formulae to generate high-resolution images in real
time. However, owing to the overwhelming complexity of the computation involved for the
tomography algorithms, the execution of these algorithms is still relatively slow (of the order of a
few seconds) [7]. This is a major obstacle that hinders the system from generating real-time results.
A study was performed to compare three main methods for ECT forward problem modelling:
sensitivity distribution, multiple linear regression (MLR) and electric field strength (ELS) [17].
It was found that the ELS method was recommended due to its very short computational time.
However, MLR is found to give better results compared with the other two methods, although it
takes a little longer to compute compared with the ELS method [17].

(i) DSP-based electrical capacitance tomography systems

Very little research work has been undertaken on designing dedicated hardware architectures
for ECT tomography using either a digital signal processor (DSP) or field-programmable gate
 ECT excitation circuit 12
sensor FPGA DSP PC
array detection circuit

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Figure 13. Architecture of digital ECT system [18].

array (FPGA) technology [7]. In [18], a dedicated architecture based on the DSP processor,
TMS320C6701, operating at 133 MHz was suggested for the image reconstruction algorithm. The
system consisted of 12 electrodes and claimed to be able to reconstruct images of 480 pixels within
a throughput of 135 frames s−1 , when using the LBP algorithm. Similarly, in [19] a TMS3206416
processor was used in an LBP-based ECT system with 16 electrodes to achieve a throughput of
200 frames s−1 [7]. Figure 13 shows the architecture of the digitized ECT system.
The system shown in figure 13 has six main units. The FPGA is used for logical control
of the system and supports the excitation circuit and detection circuit. The ECT sensor array
consists of 16 rectangular electrodes that are symmetrically mounted outside an insulating pipe.
As described in paper [19], the length of the electrodes was set to 1.8 times the pipe semi-diameter
while the width was set to 0.040625 times the pipe’s perimeter [19]. The excitation circuit is
designed and implemented based on the DDS (direct digital synthesizer) block and generates a
specific excitation voltage signal that is implemented into the measured object via the electrodes.
The detection circuit detects the output voltage from other electrodes and sends the digitized
signal to the FPGA for digital demodulation. DSP is used for the reconstruction algorithm and
communicating with the PC. Since the main image reconstruction algorithms for ECT (e.g. LBP,
Landweber, etc.) use matrix multiplication, multiplication and accumulation have become the
main operations in the DSP unit. One way to achieve this requirement is to have a DSP unit
with multiply-and-accumulate (MAC) units. DSP is very efficient, and can execute an MAC in a
single cycle [19]. In this 16-electrode ECT system, LBP and Landweber iteration algorithms are
used. Each algorithm contains 230 400 MAC units. This only requires 192 µs calculated by DSP, in
contrast to 20 ms by PC [19]. Finally, the PC is mainly used to display images and to communicate
with the DSP.

(ii) FPGA-based electrical capacitance tomography systems

The use of FPGA instead of DSP processors has become more popular because FPGAs can
host a good set of control or data flow of the reconstruction algorithm without the need for a
series of sequential memory access [7]. A recent FPGA-based electrical impedance tomography
(EIT) system was discussed in [20]. The system is composed of several FPGA-based impedance
measurement modules (IMMs) comprising independent current sources and voltmeters that
communicate with each other through a reconfigurable FPGA-based controller [7]. This system
was found to produce a throughput of about 100 frames s−1 . However, since the IMMs are mainly
involved with data acquisition and electric current generation for electrodes, rather than in image
reconstruction, the system is found to have a relatively low performance. Another similar FPGA-
based ECT system was discussed in [20] where the device digitally modulates the amplitude and
phase of AC signals with various carrier frequencies and allows the receivers to band-pass filter
the transmitted signal to their allocated carrier frequency (figure 14). As a result, this allows for
simultaneous data acquisition and avoids using CMOS analogue switches [7].
In [7], a new architecture of ECT tomography algorithm was discussed using FPGA
technology. The architecture is flexible enough to host three computationally intensive
reconstruction algorithms (i.e. LBP, Landweber and MLW). It explores some of the new features
of recent FPGA devices such as the DSP blocks and the block RAM (BRAM) [7]. A simultaneous
matrix-level and bit-level design was conducted to finely reduce the hardware cost and power
consumption, while keeping the overall execution of the algorithms low. Extensive simulations
indicate that the proposed architecture achieved a speed-up of up to three orders of magnitude
 CPLD/ simplified 13

C/V converter
FPGA DDS DAC LPF

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control core
Dresult
USB 2.0 digital ADC PGA
controller demodulator

Figure 14. System configuration of the FPGA-based capacitance measurement circuit [21].

over the software version when the reconstruction algorithm runs on a 2.53 GHz-based Pentium
processor [7]. A throughput of 17.241 K frames s−1 for both the LBP and MLW algorithms and
8.475 K frames s−1 for the LW algorithm with 200 iterations could be achieved [7].
In [22], an FPGA processor for image reconstruction in ECT systems was discussed. The
processor device was tested and was found to work with an ECT system consisting of up to
eight electrodes. The computation of permittivity distribution from capacitance measurements is
carried out by the FPGA using a customized VHDL processor. The system was studied and was
able to achieve a measurement range from 0 to 10 pF. This system also achieved a sensitivity of
2.3919 fF mV−1 and a resolution of 2.9 fF [22].

4. Conclusion
In this paper, several different techniques and modifications to the traditional ECT system have
been discussed, which include the front-end electronics and back-end processing unit. Many
of these methods provide promising results when it comes to generating capacitance values
accurately and efficiently. Although ECT systems have proved to be successful due to their non-
invasiveness, there are several issues that hinder them from being completely reliable. One issue
is the slow data acquisition time, where it can take several milliseconds to acquire the required
data and convert it into a reconstructed image. Another issue is the accuracy of the capacitance
value, which can be compromised due to stray capacitance. Finally, another problem is that the
generated images are either blurry or not completely representative of the actual contents in the
pipeline or container.
For most of the methods discussed in the front-end electronics section, these issues have
been the underlying cause of the research work for improving ECTs. In particular, the improved
AC circuit and MECaP system have shown promising results in which improvements in the
ECT system generated better results. The improved AC circuit aims to mitigate the effects of
stray capacitance on the measured capacitance values by comparing the acquired data from the
sensor to a reference measurement of the capacitance value and removing the stray portion
from the dataset. The MECaP system was successful in being able to generate faster results
and reduce the overall acquisition speed of retrieving the capacitance values and generating the
image. Each of these methods has the benefit of solving one of the issues that the original ECT
system faces.
In addition to the front end, the back-end electronics was also discussed. DSP-based ECT
systems have been proved to be efficient due to the fast calculation times for large algorithms.
However, research has also showed that FPGA-based ECT systems are gaining popularity due to
their ability to control the algorithm without relying on the sequential memory access that can
impede their speed. More research is needed to find and create an ECT system that uses aspects
from all of these methods and to provide faster and accurate acquisition times, prevent stray
capacitance from interfering in the dataset, and also be able to display a more accurate image.
Authors’ contributions. I.S. drafted the whole paper. M.M. was mainly involved in reviewing and polishing of
the paper.
Competing interests. The authors declare that they have no competing interests.
Funding. We received no funding for this study.
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