IRFD9010, SiHFD9010

Vishay Siliconix

Power MOSFET

FEATURES
PRODUCT SUMMARY • For Automatic Insertion
VDS (V) - 50 • Compact, End Stackable
RDS(on) (Ω) VGS = - 10 V 0.50 • Fast Switching
• Low Drive Current
Qg (Max.) (nC) 11
• Easy Paralleled
Qgs (nC) 3.8 • Excellent Temperature Stability
Qgd (nC) 4.1 • P-Channel Versatility
Configuration Single • Compliant to RoHS Directive 2002/95/EC

DESCRIPTION
The HVMDIP technology is the key to Vishay’s advanced
line of power MOSFET transistors. The efficient geometry
S and unique processing of the HVMDIP design achieves
very low on-state resistance combined with high
HVMDIP transconductance and extreme device ruggedness.
The p-channel HVMDIPs are designed for application which
G require the convenience of reverse polarity operation. They
retain all of the features of the more common n-channel
HVMDIPs such as voltage control, very fast switching, ease
S
G
of paralleling, and excellent temperature stability.
P-channels HVMDIPs are intended for use in power stages
D D where complementary symmetry with n-channel devices
P-Channel MOSFET
offers circuit simplification. They are also very useful in drive
stages because of the circuit versatility offered by the
reverse polarity connection. Applications include motor
control, audio amplifiers, switched mode converters, control
circuits and pulse amplifiers.

ORDERING INFORMATION
Package HVMDIP
IRFD9010PbF
Lead (Pb)-free
SiHFD9010-E3
IRFD9010
SnPb
SiHFD9010

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS - 50
V
Gate-Source Voltage VGS ± 20
TC = 25 °C - 1.1
Continuous Drain Current VGS at - 10 V ID
TC = 100 °C - 0.68 A
Pulsed Drain Currenta IDM - 8.8
Linear Derating Factor 0.01 W/°C
Inductive Current, Clamped L = 100 µH see fig. 14 ILM - 8.8
A
Inductive Current, Unclamped (Avalanche Current) see fig. 15 IL - 1.5
Maximum Power Dissipation TC = 25 °C PD 1 W
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150
°C
Soldering Recommendations (Peak Temperature) for 10 s 300d
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = - 25 V, starting TJ = 25 °C, L = 52 mH, Rg = 25 Ω, IAS = - 2.0 A (see fig. 12).
c. ISD ≤ - 4.0 A, dI/dt ≤ 75 A/μs, VDD ≤ VDS, TJ ≤ 175 °C.
d. 1.6 mm from case.

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91405 www.vishay.com
S10-0998-Rev. A, 26-Apr-10 1
IRFD9010, SiHFD9010
Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - 120 °C/W

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 μA - 50 - - V
VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.091 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 μA - 2.0 - - 4.0 V
Gate-Source Leakage IGSS VGS = ± 20 V - - ± 500 nA
VDS = - 50 V, VGS = 0 V - - - 250
Zero Gate Voltage Drain Current IDSS μA
VDS = - 40 V, VGS = 0 V, TJ = 125 °C - - - 1000
On-State Drain Current ID(on) VGS = 10 V VDS > ID(on) x RDS(on) max. - 1.1 - - A
Drain-Source On-State Resistance RDS(on) VGS = - 10 V ID = - 0.58 Ab - 0.35 0.50 Ω
Forward Transconductance gfs VDS = - 20 V, ID = - 2.4 A 1.7 2.5 - S
Dynamic
Input Capacitance Ciss - 240 -
VGS = 0 V,
Output Capacitance Coss VDS = - 25 V, - 160 - pF
f = 1.0 MHz, see fig. 5
Reverse Transfer Capacitance Crss - 30 -
Total Gate Charge Qg - 7.2 11
ID = - 4.7 A, VDS = 0.8 V
Gate-Source Charge Qgs VGS = - 10 V - 2.5 3.8 nC
see fig. 6 and 13b
Gate-Drain Charge Qgd - 2.7 4.1
Turn-On Delay Time td(on) - 6.1 9.2
Rise Time tr VDD = - 25 V, ID = - 4.7 A - 47 71
Rg = 24 Ω, RD = 5.6 Ω, ns
Turn-Off Delay Time td(off) see fig. 10b - 13 20
Fall Time tf - 39 59

Internal Drain Inductance LD Between lead, D

- 4.0 -
6 mm (0.25") from
nH
package and center of G

Internal Source Inductance LS die contact - 6.0 -

S

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current IS MOSFET symbol D

- - - 1.1 A
showing the
integral reverse G

Pulsed Diode Forward Currenta ISM p - n junction diode S - - - 8.8

Body Diode Voltage VSD TJ = 25 °C, IS = - 0.7 A, VGS = 0 Vb - - - 5.5 V

Body Diode Reverse Recovery Time trr 33 75 160 ns
TJ = 25 °C, IF = - 4.7 A, dI/dt = 100 A/μsb
Body Diode Reverse Recovery Charge Qrr 0.090 0.22 0.52 μC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %.

www.vishay.com Document Number: 91405

2 S10-0998-Rev. A, 26-Apr-10
 IRFD9010, SiHFD9010
Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

10 3.0

RDS(on), Drain-to-Source on Resistance

- 10 V 80 μs Pulse Width
-8V ID = - 4.7 V

8 2.4
- ID, Drain Current (A)

(Normalized)
6 -7V 1.8

4 VGS = - 6 V 1.2

2 -5V 0.6
VGS = - 10 V
-4V
0 0
0 5 10 15 20 25 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160

- VGS, Drain-to-Source Voltage (V) TJ, Junction Temperature (°C)

Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature

10 500
80 μs Pulse Width VGS = 0 V, f = 1 MHz
- 10 V Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
8 400
Coss = Cds + Cgd
- ID, Drain Current (A)

-8V
Capacitance (pF)

6 300 Ciss
-7V

4 200
VGS = - 6 V
Coss

2 100
-5V Crss
-4V
0 0
0 1 2 3 4 5 1 10 100

- VGS, Drain-to-Source Voltage (V) - VGS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

10 20
80 μs Pulse Width
- VGS, Gate-to-Source Voltage (V)

VDS = 2 x VGS ID = - 4.7 A

16
- ID, Drain Current (A)

1
VDS = - 40 V

12
0.1 TJ = 150 °C
8
TJ = 25 °C
0.01
4
For Test Circuit
See Figure 13
0.001 0
0 3 4 6 8 10 0 3 6 9 12 15

- VGS, Drain-to-Source Voltage (V) Qg, Total Gate Charge (nC)

Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Document Number: 91405 www.vishay.com

S10-0998-Rev. A, 26-Apr-10 3
IRFD9010, SiHFD9010
Vishay Siliconix

100 2.0
- ISD, Reverse Drain Current (A)

1.6

- ID, Drain Current (A)

TJ = 150 °C
10
1.2

0.8
1 TJ = 25 °C

0.4

0.1 0
0 1 2 3 4 5 25 50 75 100 125 150

- VSD, Source-to-Drain Voltage (V) TC, Case Temperature (°C)

Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature

100
Operation in this Area Limited RD
by RDS(on) VDS

VGS
- ID, Drain Current (A)

10 10 μs
D.U.T.
100 μs Rg -
+VDD
1 ms
1
- 10 V
10 ms
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
100 ms
0.1
TC = 25 °C 1s
TJ = 150 °C Fig. 10a - Switching Time Test Circuit
DC
Single Pulse
0.01
1 10 100

- VDS, Drain-to-Source Voltage (V) td(on) tr td(off) tf

VGS
Fig. 8 - Maximum Safe Operating Area 10 %

90 %
VDS

Fig. 10b - Switching Time Waveforms

www.vishay.com Document Number: 91405

4 S10-0998-Rev. A, 26-Apr-10
 IRFD9010, SiHFD9010
Vishay Siliconix

1000
Thermal Response (ZDthJC)

100 0.5
0.2
0.1
10 0.05 PDM

0.02
t1
t2
1 0.01
Notes:
Single Pulse 1. Duty Factor, D = t1/t2
(Thermal Response) 2. Peak TJ = PDM x TthJC + TC
0.1
0.00001 0.0001 0.001 0.01 0.1 1 10 100

t1, Rectangular Pulse Duration (s)

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

L
VDS QG
Vary tp to obtain - 10 V
required IAS

Rg D.U.T QGS QGD

-
+ V DD
IAS
VG
- 10 V
tp 0.01 W

Charge

Fig. 12a - Unclamped Inductive Test Circuit Fig. 13a - Basic Gate Charge Waveform

Current regulator
Same type as D.U.T.
IAS
50 kΩ

12 V 0.2 µF
0.3 µF
VDS -

D.U.T. + VDS
VDD
tp VGS

- 3 mA
VDS
IG ID
Current sampling resistors

Fig. 12b - Unclamped Inductive Waveforms Fig. 13b - Gate Charge Test Circuit

Document Number: 91405 www.vishay.com

S10-0998-Rev. A, 26-Apr-10 5
IRFD9010, SiHFD9010
Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

D.U.T. +
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- - +

Rg • dV/dt controlled by RG +
• ISD controlled by duty factor "D"
- VDD
• D.U.T. - device under test

Compliment N-Channel of D.U.T. for driver

Driver gate drive

P.W.
Period D=
P.W. Period

VGS = - 10 V*

D.U.T. ISD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

* VGS = - 5 V for logic level and - 3 V drive devices

Fig. 14 - For P-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91405.

www.vishay.com Document Number: 91405

6 S10-0998-Rev. A, 26-Apr-10
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Vishay
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definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12 1 Document Number: 91000