Professional Documents
Culture Documents
Delay calculation :
Delay models are used for delay calculation which is needed because of the
complex input capacitance, Voltage drop, High impedance networks, timing
analysis .etc and it is stored in lookup table format.
Delay Models
wire_load (“wlm_conservative”) {
resistance: 6.0; # resistance per unit length of the interconnect
capacitance: 1.2; # capacitance per unit length of the interconnect
area: 0.07; # area overhead per unit length of the interconnect.
slope: 0.5; #extrapolation slope used for data points that are not specified in
the fan-out length table.
fanout_length (1, 2.6);
fanout_length (2, 3.1);
fanout_length (3, 3.6);
fanout_length (4, 4.1);
fanout_length (6, 5.1);
fanout_length (7, 5.6);
}
fanout_length (2, 2.9) means that for output pin with
fanout equal 2, the wire length will be 2.9. Then you need
to multiply this wire length with capacitance and
resistance to calculate RC values for all wires.
For extrapolation
Length = Length of Last fanout number given in the table + (The fanout
number we want – Last fanout number in WLM) * Slope
Capacitance = New calculated Length * Capacitance coefficient given in
the table
---------------------------------------------------------------------------------------------------------------------
Example3: for fan out of 5
For interpolation:
The units for the length, resistance, capacitance, and area are as specified in
the library.
The Elmore delay analysis model estimates the delay from a source (root) to
one of the leaf nodes as the sum of the resistance in the path to the i node
th
t p d = ∑ Ris C i
nMOS transistors are characterised with higher mobility than pMOS transistors. If the
transistor is velocity-saturated, its current and resistance does not depend on the
channel length.
Let’s consider a transistor with gate capacitance C. For a k unit cell, gate capacitance of
the transistor is kC. Diffusion capacitance usually depends on the size of drain/source,
but with the most common approximation it is also C.
Figure 1 shows the equivalent RC circuits for nMOS and pMOS transistors. Figure 2
shows a fanout-1 inverter and its equivalent circuit.