Enrollment No.

Experiment – 1: Logic Gates

Aim : To Study and Perform About Logic Gates

Requirements : Digital IC Trainer Kit, Patch cords.

Pre-Experiment Exercise

Brief Theory:

Logic Gate:
Logical circuits that perform the logical operations are known as logic
gates. Logic gates are basic building block of any digital system.
Truth Table:
 It is a table of all possible combinations of the variables showing the relation between
the values that the variables may take and the result of the operation.
 It is used to indicate the logical relationship between I/Ps and O/Ps.
 The name of logic gates:
(1) NOT (5) NOR
(2) OR (6) AND
(3) NAND (7) EX-OR
(4) EX-NOR (8) BUFFER [TRANSFER]

SR. Name of Gate Logic Symbol Truth Table

No. and Equation

1. NOT X F
0
F =X’ 1

2. OR X Y F
0 0
0 1
F=X+Y 1 0
1 1

3. X Y F
AND 0 0
0 1
1 0
F=XY 1 1

1
 Enrollment No.-

4. NOR X Y F
0 0
0 1
F= (X+Y)’ 1 0
1 1

5. NAND
X Y F
0 0
F=(X Y)’ 0 1
1 0
1 1

6. X-OR X Y F
(Exclusive OR) 0 0
0 1
F=XY 1 0
1 1

7. X-NOR
(Exclusive NOR) X Y F
0 0
F=XOY 0 1
1 0
1 1

8. BUFFER
X F
F=X
0
1

Laboratory Exercise:
Procedure
1. Connect the circuit for different gates.
2. Apply different combinations of input and verify the Truth Table.
3. Fill the outputs in above blank Truth Table.

Post Experiment Exercise:

Conclusion

2
 Enrollment No.-

Questions:

(a) Give the applications of Logic Gates.

Ans:

(b) List out different Characteristics of IC logic families.

Ans:

Reference
[1] M.Morris Mano, Digital logic & Computer Design, 3rd edition,
Prentice-hall, 2002.

3
 Enrollment No.-

Experiment – 2: D’ Morgan’s Theorem

Aim : To Study and Perform about D’ Morgan’s Theorem

Requirements : Digital IC Trainer Kit, Patch cords.

Pre-Experiment Exercise:

Brief Theory
[A] D’ Morgan’s Law:

(i) ( A + B )’ = A’.B’

(ii) ( A . B )’ = A’+ B’

 Statements of the D’ Morgan’s Law:

(i) “COMPLIMENTS OF SUM OF TWO OR MORE VAIABLE IS EQUAL TO

PRODUCT OF COMPLIMENTS OF EACH VARIABLES”

(ii) “COMPLIMENTS OF PRODUCTS OF TWO OR MORE VARIABLE IS

EQUAL TO SUM OF COMPLIMENTS OF EACH VARIABLES”

Laboratory Exercise:

Prove the following expression and fill the truth table.

(i) ( A + B )’ = A’.B’

(NOR GATE) (BUBBLED AND GATE)

 Truth Table:

A B A + B (A + B) A’ B’ A’. B’
0 0
0 1
1 0
1 1

(ii) (A B) = A’ + B’

4
 Enrollment No.-

(NAND GATE) (BUBBLED OR GATE)

 Truth Table:

A B A.B (A . B) A’ B’ A’ + B’
0 0
0 1
1 0
1 1

Post Experiment Exercise:

Conclusion

Questions

(a) Using Boolean algebra and De Morgan’s theorems show that

YZ+WXZ+WXYZ+WYZ=Z

(b) Prove the following identities using Boolean algebra and De Morgan’s theorems.

(i) AB+A+AB=0

5
 Enrollment No.-

Reference
[1] M.Morris Mano, Digital logic & Computer Design, 3rd edition,
Prentice-hall, 2002.

6
 Enrollment No.-

Experiment – 3: Universal Gates

Aim : To Study and Perform About Universal Gates

Requirements : Digital IC Trainer Kit, Patch cords.

Pre-Experiment Exercise:

Brief Theory
NAND and NOR gates are known as universal gates since any Boolean function/
Combinational circuits and sequential circuits as well can be constructed with these gates.

NAND Gate as an Universal Gate

1. NOT Gate using NAND Gate Truth Table NOT Gate

A
Y
0
1

2. OR Gate using NAND Gate Truth Table OR Gate

A B
Y
0 0
0 1
1 0
1 1
3. AND Gate using NAND Gate Truth Table AND Gate

A B
Y
0 0
0 1
1 0
1 1

NOR Gate as a Universal Gate

1. NOT Gate using NOR Gate Truth Table NOT Gate

7
 Enrollment No.-

A Y
0
1

2. OR Gate using NOR Gate OR Gate

Truth Table

A B Y
0 0
0 1
1 0
1 1

3. AND Gate using NOR Gate Truth Table AND Gate

A B Y
0 0
0 1
1 0
1 1

Laboratory Exercise:
Procedure
1. Connect the circuit for NOT gate by using only NAND gates on trainer kit.
2. Apply different combinations of input and verify the Truth Table.
3. Fill the outputs in above blank Truth Table.
4. Repeat the same procedure for other gates by NAND gates and NOR gates.

Post Experiment Exercise

Conclusion

Questions:

8
 Enrollment No.-

(a) How Ex-OR gate can be implemented by NAND gates?

(b) How Ex-OR gate can be implemented by NOR gates?

Reference
[1] M.Morris Mano , Digital logic & Computer Design, 3rd edition,
Prentice-hall, 2002.

Experiment – 4 : Half Adder And Full Adder

Aim : To Study and Perform About Half Adder and Full Adder

Requirements : Digital IC Trainer Kit, Patch cords.

Pre-Experiment Exercise

Brief Theory

HALF-ADDER :
A Combinational circuit that performs the addition of two bits is known as a
half-adder.

9
 Enrollment No.-

 It requires two binary inputs and two outputs. The input variables indicate augend and
addend bits;the output variables indicate the sum and carry.
 The truth-table can be given by this:

Addend Augend Sum Carry

(A) (B) (S) (C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

S = A’B + AB’
C = AB
 Logic Diagram :

FULL-ADDER :
A Combinational circuit that performs the addition of two significant bits and a previous
carry[three bits] is known as a full-adder.
 A full-adder can be implemented with two half-adders.
 It requires three binary inputs and two outputs. Two of the three input variables indicate
two significant bits to be added. The third input represents the carry from the previous
lower significant position.

I/Ps O/P
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

 Logic Diagram :

10
 Enrollment No.-

Laboratory Exercise:

Connect the circuits and fill the following truth table.

1] Truth table for the half adder

Input Output
A B SUM CARRY
0 0
0 1
1 0
1 1

2] Truth table for the full adder

Input Output
A B C SUM CARRY
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Post Experiment Exercise

Conclusion

11
 Enrollment No.-

Questions
A) Write down the difference between BCD adder and Binary adder?

Reference
[1] M.Morris Mano , Digital logic & Computer Design, 3rd edition,
Prentice-hall, 2002.

Experiment – 5: Half Subtractor and Full Subtractor

Aim : To Study and Perform About Half Subtractor and Full

Subtractor

Requirements : Digital IC Trainer Kit, Patch cords.

Pre-Experiment Exercise

Brief Theory
HALF-SUBSTRACTOR:
A Combinational circuit that performs the subtraction of two bits is known as a half-
sub tractor.
 It requires two binary inputs and two outputs. The input variables indicate augend and
addend bits; the output variables indicate the sum and carry.
 The truth-table can be given by this:

A B B D
0 0 0 0
0 1 1 1

12
 Enrollment No.-

1 0 0 1
1 1 0 0

D = A’B + AB’
B = A’B
 Logic Diagram :

FULL- SUBSTRACTOR :
A Combinational circuit that performs the subtraction of two significant bits and a previous
borrow[three bits] is known as a full-adder.
* A full-adder can be implemented with two half-adders.
* It requires three binary inputs and two outputs. Two of the three input variables indicate two
significant bits to be subtracted. The third input represents the borrow from the previous lower
significant position.

 Logic Diagram :

Laboratory Exercise:

Connect the circuits and fill the following truth table.

1] Truth table for the half subtractor

Input Output
A B DIFF BORROW

13
 Enrollment No.-

0 0
0 1
1 0
1 1

2] Truth table for the full subtactor

Input Output
A B C DIFF. BORROW
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Post Experiment Exercise

Conclusion

Questions
A) Draw different diagrams of full subtractor.

14
 Enrollment No.-

Reference
[1] M.Morris Mano , Digital logic & Computer Design, 3rd edition,
Prentice-hall, 2002.

Experiment – 6: R-S and D Flip flop

Aim : To Study and Perform about R-S and D flip flop

Requirements : Digital IC Trainer Kit, Patch cords.

Pre-Experiment Exercise

Brief Theory

FLIP-FLOP :
The memory elements used in clocked sequential circuits are called flip-flops.
 They are capable of storing one bit of information.
 A flip-flop circuit has two outputs; one for normal value and one for the complement
value of bit stored in it.
 It can maintain binary state indefinitely until detected by an input signal to switch states.
 The major differences between various types of flip-flops are in number of i/ps they
possess and in the manner in which inputs affect the output.
 The most common types of flip-flops are:
 CLOCKED RS-FLIP FLOP
 D-FLIP FLOP
 JK FLIP FLOP
 T FLIP FLOP
 MASTER-SLAVE FLIP FLOP
 EDGE TRIGGERED FLIP FLOP

R-S Flip- flop:

(i) Logic Diagram:

15
 Enrollment No.-

(ii) Graphical Symbol

 D Flip – flop:

(i) Logic Diagram:

(ii) Graphical Symbol

16
 Enrollment No.-

Laboratory Exercise:

Connect the circuits and fill the following truth table.

[1] Truth table for the R-S flip flop

Q S R Q(t+1)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

[2] Truth table for the D flip flop

Q D Q(t+1)
0 0
0 1
1 0
1 1

Post Experiment Exercise

Conclusion

Questions
A) What is the difference between combinational circuit and sequential circuit?

17
 Enrollment No.-

B) Write down the brief theory of D flip flop.

Reference
[1] M.Morris Mano , Digital logic & Computer Design, 3rd edition,
Prentice-hall, 2002.

Experiment – 7: J-K And T Flip Flop

18
 Enrollment No.-

Aim : To Study and Perform about J-K and T flip flop

Requirements : Digital IC Trainer Kit, Patch cords.

Pre-Experiment Exercise

Brief Theory

FLIP-FLOP :
The memory elements used in clocked sequential circuits are called flip-flops.
 They are capable of storing one bit of information.
 A flip-flop circuit has two outputs; one for normal value and one for the complement
value of bit stored in it.
 It can maintain binary state indefinitely until detected by an input signal to switch states.
 The major difference between various types of flip-flops is in number of i/ps they possess
and in the manner in which inputs affect the output.
 The most common types of flip-flops are:
 CLOCKED RS-FLIP FLOP
 D-FLIP FLOP
 JK FLIP FLOP
 T FLIP FLOP
 MASTER-SLAVE FLIP FLOP
 EDGE TRIGGERED FLIP FLOP

 J-K Flip- flop:

(i) Logic Diagram:

(ii) Graphical Symbol

19
 Enrollment No.-

 T Flip – flop:

(i) Logic Diagram:

(ii) Graphical Symbol

Laboratory Exercise

Connect the circuits and fill the following truth table.

1] Truth Q J K Q(t+1) table for the J-K flip flop

0 0 0
0 0 1
0 1 0
20 0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
 Enrollment No.-

2] Truth table for the T flip flop

Q T Q(t+1)
0 0
0 1
1 0
1 1

Post Experiment Exercise

Conclusion

Questions

A) Advantages of JK flip flop.

B) Explain Toggle condition.

21
 Enrollment No.-

C) Why T flip flop is called toggle flip flop?

22
 Enrollment No.-

Reference
[1] M.Morris Mano , Digital logic & Computer Design, 3rd edition,
Prentice-hall, 2002.
Experiment – 8: Master Slave Flip flop

Aim : To Study and Perform About Master Slave JK flipflop.

Requirements : Digital IC Trainer Kit, Patch cords.

Pre-Experiment Exercise

Brief Theory

The flip flops like RS, JK, T, D have the problem of ‘race around’, i.e, for some inputs the
output at the end of the clock pulse is uncertain. This problem can be eliminated by using the
master slave J-K flip flop configuration shown in given figure.

In this circuit the master flip flop responds to the input when the clock is present and the
slave flip flop responds when the clock is absent. Therefore, the out put Q will only change at the
falling edge of the clock pluse.

 Logic Diagram of Master – Slave Flip flop.

23
 Enrollment No.-

 Clocked Master- Slave J-K Flip-flop:

 Timing Diagram of the Master – Slave J-K Flip-flop:

24
 Enrollment No.-

Laboratory Exercise:

Procedure
1. Connect the circuit as shown in circuit in fig.
2. Apply CLR input at high level. The output will be zero level irrespective of J and
K inputs.
3. Now keep CLR input at high level. Apply J and K input as per above truth table.
Apply one clock pulse at a time at clock terminal by pressing pulsar switch once.
Observe the output. Apply second and subsequent clock pulse. Observe the
output.
4. For different combinations of J and K inputs, verify the truth table for JK
flipflop.

Post Experiment Exercise

Conclusion

Questions
A) What is race around condition?

25
 Enrollment No.-

Reference
[1] M.Morris Mano , Digital logic & Computer Design, 3rd edition,
Prentice-hall, 2002.

Experiment – 9: Decoder and Demultiplexer

Aim : To Study and Perform About Decoder and Demultiplexer

Requirements : Digital IC Trainer Kit, Patch cords.

Pre-Experiment Exercise

Brief Theory

DECODER:
 It is a combinational circuit that converts binary information from n input lines to
a maximum of 2n unique o/p lines.
 If the n-bit decoded information has unused or don’t care combinations, the
decoder o/p will have less than 2n o/ps.

DEMULTIPLEXER:
 It is a combinational circuit that receives information on a single line and transmits this
information on one of 2n possible o/p lines.
 The selection of a specific output line is controlled by bit values of n selection lines.
 A decoder with an enable input is referred to as a decoder/demultiplexer since both
operations can be obtained from the same circuit.
Any decoder without any enable input can’t work as a demultiplexer

Block diagram of Decoder and Demultiplexer

26
 Enrollment No.-

Laboratory Exercise

Connect the circuits and fill the following truth table.

1] Decoder

27
 Enrollment No.-

INPUT OUTPUT
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
2] Demultiplexer

INPUT OUTPUT
E A B D0 D1 D2 D3
1 X X
0 0 0
0 0 1
0 1 0
0 1 1

Post Experiment Exercise

Conclusion

Questions

28
 Enrollment No.-

A) Write about the Encoders

B) Write down the brief theory of Multiplexer.

29
 Enrollment No.-

Reference
[1] M.Morris Mano , Digital logic & Computer Design, 3rd edition,
Prentice-hall, 2002.

Experiment 10 : All Logic Gates with Three Selection Lines

Aim : To implement all logic gates with help of three selection lines.

Requirements : PC, Quartus II 5.0.

Laboratory exercise
Program
1. To implement all logic gates with help of three selection lines.

30
 Enrollment No.-

Post- Experiment Exercise

Questions
1. Explain Dataflow style of Modeling.

2. Explain behavioral style of Modeling.

Reference
1. CMOS Digital Integrated circuits – Analysis and Design by Sung – Mo kang, Yusuf
Leblebici, Third Edition. (TMH)
2. Basic VLSI Design By Puck Nell & Eshraghian, PHI, 3rd Ed.
3. Introduction to VLSI Systems by Mead C & Conway, Addison Wesley
4. Digital Integrated Circuits: A Design Perspective By Jan M. Rabaey, PHI
5. VHDL primer by J.Bhaskar, Addision Wesley, Pearson Ed.
6. VHDL by Douglas Perry (TMH)

31