Digital Logic Design Laboratory Hand Book

Experiment No. 12
IMPLEMENTATION & VERIFICATION OF LINE
MULTIPLEXER & DEMULTIPLEXER
OBJECTIVE
 Designing of 2-to-1, 4-to-1 line multiplexer and 8-to-1 line multiplexer
 Also implement 1-to-4 and 1-to-8 line de-multiplexer.
EQUIPMENT
 ePAL Trainer Board and Proteus for online LAB
 2 resisters 1K ohm
 Connecting wires
COMPONENTs
 IC Type 7408 Quadruple 2-input AND gates
 IC Type 7432 Quadruple 2-input OR gates
 IC Type 7404 Hex Inverters

THEORY
MULTIPLEXER
A multiplexer (sometimes spelled multiplexor and also known as a MUX) is defined as a
combinational circuit that selects one of several data inputs and forwards it to the output. The
inputs to a multiplexer can be analog or digital. Multiplexers are also known as data selectors .
Multiplex means “many into one”. Multiplexing is the process of transmitting a large number of
information units over a smaller number of channels or lines. A digital multiplexer (MUX) or
data
selector is a combinational circuit that selects digital information from several sources (2 n) lines
and transmits information on a single output line. The multiplexer has several data-input lines
and a single output line. The selection of a particular input line is controlled by a set of selection
lines.

irfanriazshohab@gcuf.edu.pk 1
MSISDN +923338369095
2 to 1 Multiplexer (2x 1 MUX)
A 2-to-1 multiplexer is the digital multiplexer circuit that has two data inputs D0 and D1, one
selects line S and one output Y.

Logic Symbol Switching Equivalence

2 to 1 Multiplexer (2x 1 MUX) Truth Table

Select input Data Input Data Input Output

S Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1
Truth Table 12.1 2-to-1 Multiplexer
3rd APPROACH K- MAP

\
D0 D1 S 0 = S’ 1=S

00 = D0’ D1’

01 = D0’ D1 1

11 = D0 D1 1 1

10 = D0 D1’ 1

3rd APPROACH
Select input Data Input Data Input Output
S Y

0 0 X 0

0 0 X 0

0 1 X 1

0 1 X 1

1 X 0 0

1 X 1 1

1 X 0 0

1 X 1 1

Select input Data Input Data Input Output

S Y

0 0 X 0

0 1 X 1

1 X 0 0
 1 X 1 1

Select input Data Input Data Input Output

S Y

0 X 0
0
1 X 1

X 0 0
1
X 1 1

Select input Data Input Data Input Output

S Y

0 X
0 D0
1 X

X 0
1 D1
X 1

Select input Output

S Y

0 = S’ D0

1=S D1

As shown in the above table that when select input S=0 then output Y=D0 and when S=1 then
Y=D1. We can increase the number of data inputs to be selected further and larger
Connection Diagram of 2 to 1 Multiplexer (2x 1 MUX)

Figure 12.1
4 to 1 Multiplexer (4x 1
MUX)
A 4-to-1 multiplexer is a digital multiplexer that has four data inputs, two select lines, and one
output.

Logic Symbol Switching Analogy

4 to 1 Multiplexer (4x 1 MUX) Truth Table

 6 Lines are inputs (4 are input lines and 2 are selection lines).
 Only 1 Line is output line.
 There are total 64 combinations because there are total 6 inputs.
 We can write total 64 combination but truth table will become complex.
 So we will reduce the table with don’t care. Each row have 3 don’t care so each row will
represent total 8 combinations. There are total 8 combination with don’t care.
 INPUT OUTPUT
S1 S0 D3 D2 D1 D0 Y
0 0 x x x 0 0
0 0 x x x 1 1
0 1 x x 0 x 0
0 1 x x 1 x 1

1 0 x 0 x x 0

1 0 x 1 x x 1

1 1 0 x x x 0

1 1 1 x x x 1
Table 12.2 a
INPUT OUTPUT OUTPUT
S1 S0 D3 D2 D1 D0 Y Y
x x x 0 0
0 0 D0
x x x 1 1
x x 0 x 0
0 1 1 1 D1
x x x
x 0 x x 0
1 0 D2
x 1 x x 1

0 x x x 0
1 1 D3
1 x x x 1
Table 12.2 b
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
4 to 1 Multiplexer Boolean Expression

Connection Diagram of 4 to 1 Multiplexer (4x 1 MUX)

Figure 12.2
8 to 1 Multiplexer (8 x 1 MUX)
An 8-to-1 multiplexer is a digital multiplexer that has 8 data inputs, 3 select lines, and one output.

8 to 1 Multiplexer (8x 1 MUX) Truth Table

S0 S1 S2 Y

0 0 0 D0

0 0 1 D1

0 1 0 D2
 0 1 1 D3

1 0 0 D4

1 0 1 D5

1 1 0 D6

1 1 1 D7
Truth Table 12.3 8-to-1 Multiplexer

8 to 1 Multiplexer Boolean Expression

Connection Diagram of 8 to 1 Multiplexer (8x 1 MUX)

Figure 12.3
DE-MULTIPLEXER
Demultiplex means one into many. Demultiplexing is the process of taking information from one
input and transmitting the same over several outputs. A demultiplexer is a logic circuit that
receives information on a single input and transmits the same information over several (2 n)
output lines. A demultiplexer is the opposite of a multiplexer in its operation. The functional
diagram for a demultiplexer is shown below. The circuit has one input signal, n control signals
and 2n output signals. The select input code determines to which output the DATA input will be
transmitted. As the serial data is changed to parallel data, the multiplexer is also called a
distributor or decoder.
A demultiplexer (also known as a demux or data distributor) is a circuit which can distribute
or deliver multiple outputs from a single input. It can perform as single input many output
switch.
De-Multiplexer is a combinational circuit that performs the reverse operation of Multiplexer. It
has single input, ‘n’ selection lines and maximum of 2 n outputs. The input will be connected to
one of these outputs based on the values of selection lines.Since there are ‘n’ selection lines,
there will be 2n possible combinations of zeros and ones. So, each combination can select only
one output. De-Multiplexer is also called as De-Mux.

Figure 8.1: Block diagrams of DMUX

1x4 De-Multiplexer
1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3, Y2, Y1
&Y0. The block diagram of 1x4 De-Multiplexer is shown in the following figure. The single
input ‘I’ will be connected to one of the four outputs, Y 3 to Y0 based on the values of selection
lines s1 & s0.
1 to 4 DE Multiplexer (1x 4 DMUX) Truth Table

Selection Inputs Outputs

S1 S0 I Y3 Y2 Y1 Y0

0 0 0 0 0 0 0

0 0 1 0 0 0 1

0 1 0 0 0 0 0

0 1 1 0 0 1 0

1 0 0 0 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 0 0

1 1 1 1 0 0 0

Selection Inputs Outputs

S1 S0 I Y3 Y2 Y1 Y0

0 0 0 0
0 0 I
1 0 0 0

0 0 0 0
0 1 I
1 0 0 0

0 0 0 0
1 0 I
1 0 0 0

0 0 0 0
1 1 I
1 0 0 0

1 to 4 De-Multiplexer Boolean Expression

Y0=S1′S0′I Y1=S1′S0I Y2=S1S0′I Y3=S1S0I

 Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

Truth Table 12.4

Connection Diagram of 1 to 4 De-Multiplexer (1 x 4 DMUX)

Figure 12.4
1x8 De-Multiplexer

The 1x8 De-Multiplexer has one input I, three selection lines s2, s1 & s0 and outputs Y7 to Y0.
1 to 8 De-Multiplexer (1x 8 DMUX) Truth Table

Selection Inputs Outputs

s2 s1 s0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 I

0 0 1 0 0 0 0 0 0 I 0

0 1 0 0 0 0 0 0 I 0 0

0 1 1 0 0 0 0 I 0 0 0

1 0 0 0 0 0 I 0 0 0 0

1 0 1 0 0 I 0 0 0 0 0

1 1 0 0 I 0 0 0 0 0 0

1 1 1 I 0 0 0 0 0 0 0

Table 12.5

1 to 8 De-Multiplexer Boolean Expression

Y0= S2′ S1′S0′I Y1= S2′ S1′S0I Y2= S2′ S1 S0′I Y3= S2′ S1 S0I
Y4= S2 S1′S0′I Y5= S2 S1′S0 I Y0= S2 S1 S0′I Y0= S2 S1 S0 I
Connection Diagram of 1 to 8 De-Multiplexer (1 x 8 DMUX)

Figure 12.5

CONNECTION DIAGRAM OF MUXs

Figure 2X1-input multiplexer Figure 4X1-input multiplexer

PROCEDURE

1. Connect the RIMS Trainer to the 220V AC supply for Hard / Physically Implementation
and run proteus for soft implementation.
2. Verify all gates of 74LS08, 74LS08 and 74LS32.
3. For 2x1 line multiplexer connect the circuit as shown in figure 12.1 and verify table 12.1
4. For 4x1line multiplexer connect the circuit as shown in figure 12.2 and verify table 12.2
5. For 8-to-1 line multiplexer connect the circuit as shown in figure 12.3 and verify table
12.3.
6. For 1x4 line de-multiplexer connect the circuit as shown in figure 12.4 and verify
table 12.4
7. For 1x8 line de-multiplexer connect the circuit as shown in figure 12.5 and verify
table 12.5

Multiplexer Integrated Circuits (ICs)

The available multiplexers integrated circuits (ICs), their functions, and the output state is listed
in the below table.

IC number Function Output State

74150 16:1 multiplexer Inverted output

74151 8:1 multiplexer Inverted output

Output is equal to
74153 Dual 4-to-1 multiplexer
input

74352 Dual 4-to-1 multiplexer Inverted output

Output is equal to
74157 Quad 2-to-1 multiplexer
input

74158 Quad 2-to-1 multiplexer Inverted output

DUAL 1-OF-4 DECODER/

74139 Inverted output
DEMULTIPLEXER

DUAL 1-OF-8 DECODER/

74138 Inverted output
DEMULTIPLEXER
 TASKS
Task No. 1
Construct a circuit of 2:1 Line Multiplexer.
Task No. 2
Construct a circuit of 4:1 Line Multiplexer.
Task No. 3
Construct a circuit of 8:1 Line Multiplexer.
Task No. 4
Construct a circuit of 8:1 Line Multiplexer with IC.
Task No. 5
Construct a circuit of 1:4 Line De-Multiplexer.
Task No. 6
Construct a circuit of 1:4 Line De-Multiplexer with IC.
Task No. 7
Construct a circuit of 1:8 Line De-Multiplexer.
RESULTS & TRUTH TABLES
Task No. 1
Select input Data Input Data Input Output
S Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1
Task No. 2

INPUT OUTPUT
S1 S0 D3 D2 D1 D0 Y
0 0 x x x 0 0
0 0 x x x 1 1
0 0 S1 S0 Y
0 1 x x x
0 0 D0
0 1 x x 1 x 1
0 1 D1
1 0 x 0 x x 0 1 0 D2
1 0 x 1 x x 1 1 1 D3

1 1 0 x x x 0

1 1 1 x x x 1
Task No. 3
S0 S1 S2 Y

0 0 0 D0

0 0 1 D1

0 1 0 D2

0 1 1 D3

1 0 0 D4

1 0 1 D5

1 1 0 D6

1 1 1 D7
Task No. 4
S0 S1 S2 Y

0 0 0 D0

0 0 1 D1

0 1 0 D2

0 1 1 D3

1 0 0 D4

1 0 1 D5

1 1 0 D6

1 1 1 D7
Task No. 5
Selection Inputs Outputs
S0 S1 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0
Task No. 6
Selection Inputs Outputs

S0 S1 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0
Task No. 7
Selection Inputs Outputs

s2 s1 s0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 I

0 0 1 0 0 0 0 0 0 I 0

0 1 0 0 0 0 0 0 I 0 0

0 1 1 0 0 0 0 I 0 0 0

1 0 0 0 0 0 I 0 0 0 0

1 0 1 0 0 I 0 0 0 0 0

1 1 0 0 I 0 0 0 0 0 0

1 1 1 I 0 0 0 0 0 0 0
CONCLUSION
I implement and verify multiplexer and de-multiplexer .I designed 2-to-1, 4-to-1 line multiplexer and 8-to-1 line
multiplexer .I also implement 1-to-4 and 1-to-8 line de-multiplexer. I implemented these circuits and record
these values in given truth table
 Rubrics Evaluation Criteria
PLO
Criteria Beginning (1) Developing (2) Accomplished (3) Exemplary (4)
No.
With instructor/
With instructor/
Apply Student is unable to apply supervisor’s Student is able to apply all
supervisor’s guidance,
1 Procedural described procedure to guidance, student is procedural knowledge to
student is able to apply
Knowledge perform activity despite able to apply all independently perform
some of the described
to perform instructor/ supervisor’s described procedure activity without instructor/
procedure to partially
an activity guidance. to fully perform supervisor’s guidance.
perform activity.
activity.
Student is able to Student is able to
Effectively
Student is unable to Student is able to partially effectively effectively and
document/
effectively document/ document/ communicate document/ independently document/
10 communicat
communicate performed performed activities with communicate communicate performed
e performed
activities despite guidance. guidance. performed activities activities form without any
activities
with guidance. guidance.

CLO-04: Apply Procedural Knowledge to Assemble, Manipulate the logic circuits and display the results
CLO-06: Demonstrate result of performed activities
PLO-01: Engineering Knowledge: An ability to apply knowledge of mathematics, science and engineering fundamentals and
an engineering specialization to the solution of complex engineering problems.
PLO-10: Communication: An ability to communicate effectively, orally as well as in writing on complex engineering activities
with the engineering community and with society at large, such as being able to comprehend and write effective reports and
design documentations, make effective presentations, and give and receive clear instructions.
 Activity Name  Experiment No. 12
Group No.  01

Student Roll No. 

5611

CL P Domain + Awarded Score (out of 4 for each cell)

No. O L Taxonomy Criteria
(Absent student will get zero mark)
O
Apply Procedural Knowledge to perform
1 4 1 P4
an activity
Effectively document/ communicate
2 6 10 A3 performed activities

Name of Lab. Instructor Signature Dated:

Engr. Irfan Riaz Shohab