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INSTRUMENTATION
AUTOMATION LOGIC
TRAINING MANUAL
Course EXP-MN-SI080
Revision 0
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Instrumentation
Automation Logic
INSTRUMENTATION
AUTOMATION LOGIC
CONTENTS
1. OBJECTIVES ..................................................................................................................6
2. THE NUMBERING SYSTEMS AND CODES ..................................................................7
2.1. REPRESENTATION OF NUMBERS.........................................................................8
2.2. BINARY-TO-DECIMAL CONVERSION.....................................................................9
2.3. DECIMAL-TO-BINARY CONVERSION.....................................................................9
2.3.1. Conversion of the integer part ...........................................................................9
2.3.2. Conversion of the fractional part......................................................................10
2.4. OCTAL NUMBERING SYSTEM..............................................................................11
2.4.1. Octal-to-Decimal Conversion...........................................................................11
2.4.2. Decimal-to-Octal Conversion...........................................................................12
2.4.3. Octal-to-Binary Conversion .............................................................................12
2.4.4. Binary-to-Octal Conversion .............................................................................13
2.5. HEXADECIMAL NUMBERING SYSTEM ................................................................14
2.5.1. Hexadecimal-to-Decimal Conversion ..............................................................15
2.5.2. Decimal-to-Hexadecimal Conversion ..............................................................15
2.5.3. Hexadecimal-to-Binary Conversion .................................................................16
2.5.4. Binary-to-Hexadecimal Conversion .................................................................16
2.5.5. Hexadecimal counting .....................................................................................16
2.5.6. Usefulness of the Hexadecimal system...........................................................17
2.6. BCD CODE .............................................................................................................18
2.6.1. Comparison between BCD code and binary numbers.....................................19
2.7. THE GRAY CODE OR REFLECTED BINARY CODE ............................................20
2.8. SUMMARY OF THE DIFFERENT CODES .............................................................22
2.9. ALPHANUMERICAL CODES..................................................................................23
2.9.1. ASCII code ......................................................................................................23
3. BINARY ARITHMETIC...................................................................................................26
3.1. REPRESENTATION OF POSITIVE INTEGERS.....................................................26
3.2. BINARY ADDITION.................................................................................................26
3.3. REPRESENTATION OF SIGNED INTEGERS .......................................................28
3.3.1. Notation in one's complement .........................................................................28
3.3.2. Two's complement notation .............................................................................29
3.3.3. Study of binary numbers signed with two's complement .................................30
4. COMBINATORIAL LOGIC .............................................................................................32
4.1. DEFINITIONS .........................................................................................................32
4.1.1. The logic states ...............................................................................................32
4.1.2. Positive logic and negative logic......................................................................32
4.1.3. The logic variables ..........................................................................................33
4.1.4. The logic functions ..........................................................................................33
4.2. LOGIC FUNCTIONS WITH ONE AND TWO VARIABLES......................................34
4.2.1. Functions with one variable .............................................................................34
4.2.2. Functions with two variables............................................................................34
4.3. TRUTH TABLE........................................................................................................35
Training Manual EXP-MN-SI080-EN
Last revised on: 14/11/2008 Page 2 / 137
Instrumentation
Automation Logic
5. THE BASIC LOGIC OPERATIONS ...............................................................................37

5.1. THE OR OPERATOR..............................................................................................37
5.1.1. The OR gate....................................................................................................37
5.2. THE AND OPERATOR ...........................................................................................38
5.2.1. The AND gate..................................................................................................38
5.3. THE NOT OPERATOR ...........................................................................................39
5.3.1. NOT inverter circuit..........................................................................................39
5.4. THE NOR and NAND GATES .................................................................................40
5.4.1. The NOR gate .................................................................................................40
5.4.2. The NAND gate ...............................................................................................41
5.5. EXCLUSIVE OR (XOR) and EXCLUSIVE NOR (XNOR) CIRCUITS ......................43
5.5.1. The Exclusive OR (XOR) gate.........................................................................43
5.5.2. The Exclusive NOR (XNOR) gate ...................................................................44
5.6. SYMBOLS USED FOR THE BASIC OPERATIONS ...............................................45
5.7. PUTTING LOGIC CIRCUITS INTO ALGEBRAIC FORM ........................................47
5.7.1. Circuit including INVERTERS..........................................................................48
5.8. MATERIALISATION OF CIRCUITS FROM BOOLEAN EXPRESSIONS................49
5.9. BOOLEAN ALGEBRA .............................................................................................50
5.9.1. Postulates........................................................................................................50
5.9.2. Boole's theorem for a variable .........................................................................50
5.9.3. Theorems for several variables .......................................................................51
5.9.4. DE MORGAN's theorem..................................................................................52
6. COMBINATORIAL LOGIC CIRCUITS ...........................................................................53
6.1. SUM OF PRODUCTS .............................................................................................53
6.2. SIMPLIFICATION OF LOGIC CIRCUITS................................................................54
6.3. ALGEBRAIC SIMPLIFICATION ..............................................................................54
6.4. DESIGNING COMBINATORIAL LOGIC CIRCUITS................................................55
6.5. THE KARNAUGH MAP METHOD...........................................................................57
6.5.1. Construction of the Karnaugh map..................................................................57
6.5.2. Group ..............................................................................................................59
6.5.2.1. Group of twos.............................................................................................59
6.5.2.2. Groups of four ............................................................................................60
6.5.2.3. Groups of eight...........................................................................................61
6.5.3. The complete simplification process................................................................61
6.5.4. "Don't Care" conditions....................................................................................62
6.6. THE STANDARD COMBINATORIAL FUNCTIONS ................................................63
6.7. MULTIPLEXER .......................................................................................................64
6.8. DECODER ..............................................................................................................67
6.9. COMPARATOR.......................................................................................................69
7. ELEMENTARY MEMORIES ..........................................................................................71
7.1. STUDY OF THE MEMORY FUNCTION .................................................................71
7.1.1. Terms of the problem ......................................................................................71
7.2. STABLE STATES GRAPH......................................................................................72
7.2.1. Definition: stable states, transient states. ........................................................72
7.2.2. Construction of the stable states graph. ..........................................................72
7.3. PRIMITIVE MATRIX................................................................................................74
7.4. PRIORITY RESETTING MATRIX ...........................................................................75
7.4.1. Contracted matrix ............................................................................................75

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Automation Logic
7.4.2. Secondary variable equation and output equation ..........................................75

7.4.3. Logic diagram of a priority resetting memory...................................................76
7.5. PRIORITY SETTING MEMORY..............................................................................77
7.5.1. Concentrated matrix ........................................................................................77
7.5.2. Secondary variable equation and output Q equation.......................................77
7.5.3. Logic diagram of a priority setting memory......................................................77
7.6. TRUTH TABLE FOR AN RS MEMORY ..................................................................78
7.7. SYNCHRONOUS MEMORY (RST OR RSH) .........................................................80
7.7.1. Logic diagram..................................................................................................80
7.7.2. Truth table .......................................................................................................80
7.7.3. Advantages of synchronous inputs..................................................................80
7.7.4. Drawbacks of RST memory.............................................................................81
7.8. D LATCH MEMORY................................................................................................82
7.8.1. Logic diagram..................................................................................................82
7.8.2. Truth table .......................................................................................................82
8. FLIP-FLOPS ..................................................................................................................83
8.1. FLIP-FLOP COMMAND MODES ............................................................................83
8.1.1. Master-Slave structure ....................................................................................83
8.1.2. Operation.........................................................................................................84
8.1.3. Triggering by the clock's wave edges..............................................................84
8.1.4. Combination of the master-slave structure and of operation on the edge (so-
called ‘DATA LOCK OUT’ flip-flop)............................................................................85
8.2. THE DIFFERENT FLIP-FLOPS...............................................................................86
8.2.1. RST (or RSH) flip-flops....................................................................................86
8.2.1.1. Description and symbol ..............................................................................86
8.2.1.2. The 'Master-Slave' RST flip-flop performs the counting function................86
8.2.1.3. Advantages and Drawbacks of the "Master-Slave" RST flip-flop ...............87
8.2.2. D flip-flop .........................................................................................................87
8.2.3. JK flip-flop........................................................................................................88
8.3. FLIP-FLOP APPLICATIONS ...................................................................................90
8.3.1. Shift registers ..................................................................................................90
8.3.2. Asynchronous counters ...................................................................................91
8.3.2.1. Full-cycle counters .....................................................................................91
8.3.2.2. Reversible (full-cycle) counter ....................................................................92
8.3.2.3. Incomplete-cycle counter ...........................................................................93
8.3.2.4. Advantages and drawbacks of asynchronous counters .............................94
8.3.3. Synchronous counters.....................................................................................96
8.3.3.1. Truth table for a JC flip-flop ........................................................................96
8.3.3.2. Full-cycle synchronous counters ................................................................97
8.3.3.3. Incomplete-cycle synchronous counters ..................................................100
9. INTEGRATED COUNTERS.........................................................................................103
9.1. 74192 AND 74193 ASYNCHRONOUS LOADING COUNTERS ...........................103
9.1.1. Logic symbols................................................................................................104
9.1.2. Putting several counters in series..................................................................105
9.1.3. Operating timing diagram ..............................................................................106
9.2. 74190 AND 74191 ASYNCHRONOUS LOADING COUNTERS ...........................108
9.2.1. Logic symbol .................................................................................................109

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Automation Logic
9.2.2.1. Putting in asynchronous series ................................................................110

9.2.2.2. Putting in synchronous series ..................................................................110
9.2.3. Operating timing diagrams ............................................................................112
9.3. 74160, 74162, 74162 AND 74163 SYNCHRONOUS LOADING COUNTERS......114
9.3.1. Logic symbols................................................................................................115
9.3.3. Modulo-N frequency divider...........................................................................117
9.3.4. 0 to N counter (N+1 states) ...........................................................................118
9.3.5. Counters going from N1 to N2.......................................................................119
9.3.6. Operating timing diagrams ............................................................................120
10. MEMORIES ...............................................................................................................122
10.1. GENERAL ...........................................................................................................122
10.1.1. Memory capacity .........................................................................................122
10.1.2. Organisation ................................................................................................123
10.1.3. Access mode...............................................................................................123
10.1.4. Speed ..........................................................................................................124
10.2. READ ONLY MEMORY (ROM)...........................................................................125
10.2.1. ROM architecture ........................................................................................125
10.2.2. Different types of ROM ................................................................................127
10.2.2.1. Mask Read Only Memories (MROM) .....................................................127
10.2.2.2. Programmable Read Only Memories .....................................................127
10.2.2.3. Erasable and Programmable Read Only Memories (EPROM)...............127
10.2.2.4. Electrically Erasable and Programmable Read Only Memories (EEPROM)
..............................................................................................................................128
10.2.3. Recap of the different types of Read Only Memory.....................................128
10.3. RANDOM ACCESS MEMORIES (RAM).............................................................129
10.3.1. RAM architecture.........................................................................................129
10.3.2. Different types of RAM ................................................................................130
10.3.2.1. Static RAMs ...........................................................................................130
10.3.2.2. Dynamic RAMs ......................................................................................131
10.3.3. Creation of address selection circuits ..........................................................131
11. TABLE OF FIGURES.................................................................................................135
12. SOMMAIRE DES TABLES ........................................................................................137

Instrumentation
Automation Logic
1. OBJECTIVES
The purpose of this course is to ensure the future instrumentation specialist has a basic
knowledge of automation logic on a predominantly oil-oriented industrial site.
At the end of the course, in the area of automation logic, the trainee should:
Know the binary, octal, decimal and hexadecimal numbering systems,
Know how to convert the various numbering systems,
Have an understanding of combinational logic, which is essential for programming

PLCs and DCSs.
Know the basics of sequential logic.

Instrumentation
Automation Logic
2. THE NUMBERING SYSTEMS AND CODES

The binary numbering system is the most important system used in digital circuits,
because it is the only one that those circuits are capable of using. However, the
importance of the other systems must not be overlooked.
The decimal system is just as important because it is used universally to represent values
in the everyday world.
It will therefore sometimes be necessary to convert decimal values into binary values
before they can be processed in a digital circuit.
Example: when you key in a decimal number on your calculator (or the keyboard of your
computer), the internal circuits convert this decimal number into a binary value.
Likewise, there will be situations where the binary values given by a digital circuit will have
to be converted into decimal values so they can be read.
Example: your calculator (or your computer) calculates the answer to a problem using the
binary system and then converts those answers into decimal values before displaying
them.
We know the binary and decimal systems, so let us now look at the other numbering
systems very widely used in digital circuits. These are the octal (base 8) and
hexadecimal (base 16) numbering systems that are both used for the same purpose: to
provide an efficient tool for representing large binary numbers.

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Automation Logic
2.1. REPRESENTATION OF NUMBERS
The number of symbols used characterises the number of the base.
Example:
In base 10, we have the 10 symbols (0,1,…,9)
In base 2, we have the 2 symbols (0,1)
In base 3, we have the 3 symbols (0, 1, 2)
In base 16, we need 16 symbols, so we use the 10 digits plus the letters A to F, that
is to say : 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Remark:
It must be noted that the choice of digit symbols makes the task much easier, simply
because we are above all used to dealing with the decimal system (10 symbols).
The weight of a digit depends on its position in the number. We use the term positional
representation, that is:
A number in a positive base ‘b’ is written:
Nb = an . an-1 … a1 . a0 , a-1 … a-m

which corresponds to the following operations:
NB = an . bn + an-1 . bn-1 + a1 . b1 + a0 . b0 + a-1 . b-1 … a-m . b-m

The subscript b indicates the base in which the number is calculated.
Remark: The formula above gives N in the base in which we are carrying out the
operations (in this case base B). For us, this will generally be the base 10.
A digit is called a ‘bit’ (contraction of binary digit). The bit associated with the lowest
weight in the base is the LSB (Least Significant Bit), and the one associated with the
greatest weight is the MSB (Most Significant Bit)

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Automation Logic
2.2. BINARY-TO-DECIMAL CONVERSION
1 1 0 1 1 Binary
1.24 + 1.23 + 0.22 + 1.21 + 1.20
16 + 8 + 0 + 2 + 1 = 2710 Decimal
Let's look at another example with a larger number of conversions:
1 0 1 1 0 1 0 1 Binary
1.27 + 0.26 + 1.25 + 1.24 + 0.23 + 1.22 + 0.21 + 1.20
128 + 0 + 32 + 16 + 0 + 4 + 0 + 1 = 18110 Decimal
You will note that the method consists of finding the weights (the powers of 2) for each
position of the number where there is 1, and then of adding them all up.
You should also note that the Most Significant Bit has a weight of 27 even if it is the eighth
bit; this is because the Least Significant Bit is the first bit and its weight is always 20.
2.3. DECIMAL-TO-BINARY CONVERSION
The method that is best suited to small numbers consists of adopting an approach based
on the positional representation in binary code. The decimal number is simply expressed
as a sum of powers of 2, and we then write 1s and 0s opposite the appropriate binary
positions.
Here is an example:
4510 = 32 + 8 + 4 + 1 = 25 + 0 + 23 + 22 + 0 + 20 = 1 0 1 1 0 12
Note that there is a 0 opposite positions 21 and 24, because these positions are not used to
find the sum in question. This is a trial-and-error method.
2.3.1. Conversion of the integer part
This method is best suited to large decimal numbers; it consists of repeating the division
by 2.
The integer part of a number can be expressed as follows:

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Automation Logic
NB = an . bn + an-1 . bn-1 + … +a1 . b1 + a0 . b0

If we divide NB by the base b, we obtain the following expression:
NB / b = (an . bn-1 + an-1 . bn-2 + … + a1 . b0) … et … (a0)

a0 appears as the remainder of the division of integer N by b; a1 is the remainder of the
division of the quotient by b. We therefore proceed with successive divisions by b.
This conversion method is illustrated for the number 2510. We use repeated divisions by 2
of the decimal number to be converted. At each division, we obtain a quotient and a
remainder.
We must continue dividing until we obtain a null quotient.
It is important to note that the resulting binary number is obtained by writing the first
remainder at the position of the Least Significant Bit (LSB) and the last at the position of
the Most Significant Bit (MSB).
Example:
25 / 2 = 12 Remainder 1 LSB
12 / 2 = 6 Remainder 0
6/2 = 3 Remainder 0
3/2 = 1 Remainder 1
1/2 = 0 Remainder 1 MSB
2510 = 1 1 0 0 12
2.3.2. Conversion of the fractional part
The conversion of the fractional part is carried out using the reverse operator, that is to say
by multiplication.
The fractional part of a number can be expressed as follows:
NB = a-1 . b-1 + a-2 . b-2 + … + a-m-1 . b-m-1 + a-m . b-m

If we multiply NB by the base b, we obtain the following expression:
NB . b = a-1…(a-2 . b-1 + … +a-m-1 . b-m-2 + a-m . b-m-1)

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Automation Logic
a-1 appears as the integer part of the multiplication of fractional N by b; a-2 is the integer
part of the multiplication of the remainder by b; a-3 is the integer part of the multiplication of
the new remainder by b.
We therefore proceed by successive multiplications by b.
This conversion method is illustrated below for the number 0.37510. We use successive
multiplications by 2 of the decimal number to be converted. We obtain an integer part and
a remainder at each multiplication.
It is important to note that the resulting binary number is obtained by writing the first digit at
the position of the Most Significant Bit (MSB).
Example:
0.375 x 2 = 0.75 Integer part = 0 Remainder = 0.75 MSB

0.75 x 2 = 1.5 Integer part = 1 Remainder = 0.5
0.5 x 2 = 1.0 Integer part = 1 Remainder = 0
N10 = 0.372 corresponds to N2 = 0.011

It should be noted that a finite number in one base could lead to an infinite number in a
different base.
2.4. OCTAL NUMBERING SYSTEM
The octal numbering system is a base eight system, which means that it uses eight
possible symbols, that is 0, 1, 2, 3, 4, 5, 6 and 7. So, each digit in an octal number has a
value of between 0 and 7.
Here is the weight of each of the positions in an octal number:
…. . ….
83 82 81 80 8-1 8-2 8-3
2.4.1. Octal-to-Decimal Conversion
We convert an octal number into its decimal equivalent by multiplying each octal digit by its
positional weight.

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Example:
. . .
3728 = 3 (8²) + 7 (81) + 2 (80)
. . .
= 3 64 + 7 8 + 2 1
= 25010
2.4.2. Decimal-to-Octal Conversion
It is possible to convert a decimal integer into its octal equivalent using the same repeated
divisions method as we used for the decimal-to-binary conversion, but dividing by 8 rather
than by 2.
Example:
266 / 8 = 33 Remainder 2
4/8 = 0 Remainder 4
26610 = 4128
Note that the first remainder becomes the Least Significant Bit digit of the octal number
and that the last remainder becomes the Most Significant Bit digit.
If you use a calculator to carry out divisions, the result will be a number with a fractional
part rather than a remainder.
However, the remainder is calculated by multiplying the decimal fraction by 8. For

example, with the calculator, the answer for the division 266 / 8 is 33.25.
By multiplying the decimal part by 8, you will get a remainder of 0.25 x 8 = 2.
Likewise, 33 / 8 gives 4.125, hence a remainder of 0.125 x 8 = 1.
2.4.3. Octal-to-Binary Conversion
The main advantage of the octal numbering system lies in the ease with which it is
possible to go from an octal number to a binary number.
This conversion is made by transforming each digit of the octal number into its 3-digit
binary equivalent.

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Automation Logic
In the table below, you can see the eight octal symbols expressed in binary.
Octal digit 0 1 2 3 4 5 6 7
Binary equivalent 000 001 010 011 100 101 110 111
Table 1 : The octal symbols expressed in binary
Using this table, you can convert any octal number by transforming each of the digits. For
example, the conversion of 4728 goes like this:
4 7 2
100 111 010
So, the octal number 4728 is equivalent to the binary number 100111010.
2.4.4. Binary-to-Octal Conversion
The conversion of a binary number into an octal number is quite simply the reverse of the
previous operation.
You just have to make groups of three bits with the binary number, starting from the LSB
digit, then convert these triplets starting from the LSB digit, and finally convert these
triplets into their octal equivalent (see table 1 ‘Octal symbols expressed in binary’).
To illustrate this, let's convert 10001110102 into octal:
100 111 010

4 7 28
Sometimes the binary number will not form an exact number of groups of three. In this
case, you can add one or two zeros to the left of the MSB to form the last triplet (if you
read from right to left).
Example: The binary number 11010110:
011 010 110

3 2 68
Note that by adding a zero to the left of the MSB you will obtain an exact number of
triplets.
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2.5. HEXADECIMAL NUMBERING SYSTEM
The hexadecimal system is a base 16 system, which means that there must be 16
possible digit symbols which, in this case, are the ten digits 0 to 9 plus the upper case
letters A, B, C, D, E and F.
The table below shows the relationship between the hexadecimal, decimal and binary
systems. You can see that the binary equivalent of each hexadecimal digit is a group of 4
bits.
Hexadecimal Decimal Binary
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
A 10 1010
B 11 1011
C 12 1100
D 13 1101
E 14 1110
F 15 1111
Table 2 : Relationship between hexadecimal, decimal and binary
Hexadecimal representation is mainly used to represent a binary number in a more

compact form. A hexadecimal number has 4 times fewer digits.

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Automation Logic
2.5.1. Hexadecimal-to-Decimal Conversion
A hexadecimal number can be converted into its decimal equivalent based on the fact that
a weight is assigned to each position of a hexadecimal digit; in this case, the number 16 is
raised to a certain power.
The LSB digit has a weight of 160 = 1, the digit immediately to the left has a weight of
161 = 16, the next digit immediately to the left has a weight of 162 = 256, and so on.
Example:
35616 = 3.162 + 5.161 + 6.160

= 768 + 80 + 6
= 85410
2AF16 = 2.162 + 10.161 + 15.160

= 512 + 160 + 15
= 68710
2.5.2. Decimal-to-Hexadecimal Conversion
You may remember that for the decimal-to-binary conversion we used a repetition of
divisions by 2, that for the decimal-to-octal conversion, a repetition of divisions by 8.
So, to convert a decimal number into a hexadecimal number you just have to proceed in
the same way, but dividing by 16 instead.
You will note how the remainders of the divisions become digits in the hexadecimal
number; and also how the remainders greater than 9 are expressed by the letters A to F.
Example:
Conversion of the number 42310 into hexadecimal:
423 / 16 = 26 Remainder 7
26 / 16 = 1 Remainder 10
42310 = 1A716

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2.5.3. Hexadecimal-to-Binary Conversion
Like the octal numbering system, the hexadecimal numbering system serves as an
abbreviated way of representing binary numbers. There is really nothing difficult about
converting a hexadecimal number into a binary number, because each hexadecimal digit
is replaced by its 4-bit binary equivalent (see ‘table of codes’).
Example:
Conversion of the number 9F216 into binary:
9F216 = 9 F 2
= 1001 1111 0010
= 1001111100102
2.5.4. Binary-to-Hexadecimal Conversion
This conversion is quite simply the reverse of the previous conversion. You divide the
binary number into groups of four bits, and then you replace each group with its equivalent
hexadecimal digit. If necessary, you add zeros to the left to obtain a final group of 4 digits.
Example:
11101001102 = 0011 1010 0110

= 3 A 6
= 3A616
To go from a hexadecimal number to its binary equivalent, you must know the sequence of
4-bit binary numbers (0000 to 1111) and the corresponding number in hexadecimal.
Once this correspondence has become an automatic reflex, you will be able to make the
conversions quickly without any calculations. This explains why the hexadecimal system is
so practical for representing large binary numbers.
2.5.5. Hexadecimal counting
When you count using the hexadecimal system, the value in the number's position
increases in steps of 1 from 0 to F.

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When the digit in one position is F, the next digit in that position is 0 and the digit
immediately to the left increases by 1. This is what we can see in the following sequences
of hexadecimal numbers:
1st sequence of numbers: 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 40, 41, 42
2nd sequence of numbers: 6F8, 6F9, 6FA, 6FB, 6FC, 6FD, 6FE, 6FF, 700
Note that the digit that follows 9 in any given position is A.
2.5.6. Usefulness of the Hexadecimal system
The ease with which conversions between the binary and hexadecimal systems can be
made explains why the hexadecimal system has become an abbreviated way of
expressing large binary numbers. It is not rare in a computer to find binary numbers up to
64 bits long.
These binary numbers, as we will see, are not always numerical values but may
correspond to a certain code representing non-numerical information. In a computer, a
binary number may be:
a real number,
a number corresponding to a location (address) in memory,
an instruction code,
a code corresponding to an alphabetical or non-numerical character,
a group of bits indicating the status of the computer's internal and external devices.
When you have to work with a large number of very long binary numbers, it is a better idea
to write those numbers in hexadecimal rather than in binary.
However, do not forget that digital circuits and systems only function in binary and that it is
purely for the sake of convenience for the operators that we use hexadecimal notation.

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Automation Logic
2.6. BCD CODE
The action of making a special group of symbols correspond to numbers, letters or words
is called coding and the group of symbols, a code.
One of the codes you know best is, perhaps, Morse code where we use a series of dots
and dashes to represent the letters of the alphabet.
We have seen that any decimal number can be converted into its binary equivalent. It is
possible to consider the group of 0s and 1s in the binary number as a code that represents
the decimal number.
When you convert a decimal number into its binary equivalent, we say that you are doing
pure binary coding.
Digital circuits function with binary numbers expressed in one form or another during their
internal operations, despite the fact that the outside world is in decimal. This means that
conversions between the binary and decimal systems have to be made frequently.
We know that for large numbers conversions of this type may be very long and laborious.
This is why, in certain situations, we use a coding of decimal numbers that combines
certain characteristics of the binary system and of the decimal system.
This is called Binary Coded Decimal (BCD). If you represent each digit of a decimal
number by its binary equivalent, you obtain this BCD code.
As the highest decimal digit is 9, you will need 4 bits to code the digits.
Example:
Let us take the decimal number 874 and replace each digit with its binary equivalent, this
gives:
8 7 4 Decimal
1000 0111 0100 BCD
Once again, we can see that each digit has been converted into its pure binary equivalent.
Note that we always make 4 bits correspond to each digit.
BCD code therefore establishes a correspondence between each digit of a decimal

number and a 4-bit binary number.
Of course, only the binary groups 0000 to 1001 are used. BCD code does not use the
groups 1010, 1011, 1100, 1101, 1110 and 1111.

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In other words, only ten of the 16 combinations of 4 bits are used. If one of the
"unacceptable" combinations appears in a machine that uses BCD code, it is generally a
sign that an error has occurred.
2.6.1. Comparison between BCD code and binary numbers
It is important to realise that BCD code is not a numbering system like octal, decimal or
hexadecimal systems. In fact, this code is the decimal system whose digits have been
converted into their binary equivalent. Furthermore, you must understand that a BCD
number is not a pure binary number. When you code using the pure binary system, you
take the decimal number as a whole and convert it into binary, without splitting it up.
When you code in BCD, each individual digit is replaced by its binary equivalent.
Example:
Let us take the number 137 and find its pure binary number and then its BCD equivalent:
13710 = 100010012 (binary)
13710 = 0001 0011 0111 (BCD)
BCD code requires 12 bits to represent the number 137 whereas in pure binary only 8 bits
are needed. You need more bits in BCD than in pure binary to represent decimal numbers
with more than one digit.
As you know, this is because BCD code does not use all the possible combinations of
groups of 4 bits; it is not a particularly efficient type of code.
The main advantage of BCD code lies in the relative ease with which you can go from this
code to a decimal number and vice versa. You only have to remember the groups of 4 bits
for the digits 0 to 9.
This is a non-negligible advantage from the hardware viewpoint, because in a digital

system it is the logic circuits that are responsible for making these conversions.

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2.7. THE GRAY CODE OR REFLECTED BINARY CODE
This code is constructed in such a way that the transition from one value to the next only
requires the modification of a single bit. We say that two values that only differ by a single
bit are adjacent.
Natural Reflected
Decimal
Binary Binary
0000 0 0000
0001 1 0001
0010 2 0011
0011 3 0010
0100 4 0110
0101 5 0111
0110 6 0101
0111 7 0100
1000 8 1100
1001 9 1101
1010 10 1111
1011 11 1110
1100 12 1010
1101 13 1011
1110 14 1001
1111 15 1000
Table 3 : Gray code table
In the table above, you can see that two adjacent values are not necessarily side by side
but are always symmetrical with respect to one of the axes.
This code cannot be used to carry out arithmetic operations. However, we will find Gray
code very useful later on for making simplifications on logic functions.

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But Gray code is also very often used in situations where other codes, such as Binary
code, can produce incorrect results at the time of transitions causing a change of several
bits in the code.
For example, in natural binary code when you go from the value 0111 to the value 1000,
the 4 bits change at the same time. But at the level of a real device this situation is virtually
impossible. Several transient states will therefore be generated.
Example:
0111→1111→1011→1001→1000
These transient states may be taken into account and cause the device to function
incorrectly. However, this situation is impossible if you use Gray code because only a
single bit is changed at a time during a transition.
These codes are used in the angular position sensors that are used in servo-control
systems. These sensors may be made up of a light source and a disk on which a pattern is
etched so that photosensitive cells reproduce the desired combination directly.

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2.8. SUMMARY OF THE DIFFERENT CODES
Natural Reflected
Decimal Octal Hexadecimal
Binary Binary
0000 00 00 0 0000
0001 01 01 1 0001
0010 02 02 2 0011
0011 03 03 3 0010
0100 04 04 4 0110
0101 05 05 5 0111
0110 06 06 6 0101
0111 07 07 7 0100
1000 08 10 8 1100
1001 09 11 9 1101
1010 10 12 A 1111
1011 11 13 B 1110
1100 12 14 C 1010
1101 13 15 D 1011
1110 14 16 E 1001
1111 15 17 F 1000
Table 4 : Table summarising the different codes

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2.9. ALPHANUMERICAL CODES
A computer would not be of much use if it wasn't capable of processing non-numerical

information. By that, I mean that a computer must be able to recognise codes
corresponding to numbers, letters, punctuation signs and special characters.
Codes of this type are called alphanumerical. A complete set of characters must include
the 26 lower case letters, the 26 upper case letters, the ten digits, the seven punctuation
signs and between 20 and 40 special characters such as +, /, #,%.
It could be said that an alphanumerical code reproduces all the characters and
miscellaneous functions found on a standard computer keyboard.
2.9.1. ASCII code
The best-known and most widely used alphanumerical code is of course ASCII code
(American Standard Code for Information Interchange), which is used in most
microcomputers and mobile phones, etc.
Standard ASCII code (pronounced "aski") is a code on 7 bits, so using it we can therefore
represent 27 = 128 coded elements. This is largely sufficient for reproducing all the usual
letters on a keyboard and the control functions such as <RETURN> and LINEFEED.
The table below gives the standard ASCII code. In this table, we have also given the
hexadecimal equivalent in addition to each character's binary group.

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0..3 0 1 2 3 4 5 6 7
0 NUL DLE Space 0 Nat P ` p
1 SOH DC1 ! 1 A Q a q
2 STX DC2 ‘’ 2 B R b r
3 ETX DC3 # 3 C S c s
4 EOT DC4 $ 4 D T d t
5 ENQ NAK % 5 E U e u
6 ACK SYN & 6 F V f v
7 BEL ETB ‘ 7 G W g w
8 BS CAN ( 8 H X h x
9 HT EM ) 9 I Y i y
A LF SUB * : J Z j z
B VT ESC + ; K Nat k Nat
C FF FS , < L Nat l Nat
D CR GS - = M Nat m Nat
E SO RS . > N ^ n ~
F SI US / ? O _ o DEL
Table 5 : Partial list of ASCII code
The major shortcoming with ASCII code, when used in Europe, is that it does not include
accented characters. Certain computer hardware manufacturers have modified ASCII
code, replacing certain characters that are not widely used with accented characters.
IBM preferred to add an eighth bit to ASCII code, where the accented characters then
corresponded to codes higher than 128; IBM code, which is used in all PC and compatible
computers, also makes it possible to represent small drawings, some Greek letters and
semi-graphic characters (horizontal and vertical bars, etc.).

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SOH Start Of Header US Unit Separator

STX Start of Text RS Record Separator
ETX End of Text GS Group Separator
EOT End Of Transmission FS File Separator
ENQ Enquiry BEL Bell
ACK Acknowledgement of receipt SO Shift Out
DLE Data Link Escape SI Shift In
Negative Acknowledgement of
NAK CAN Cancel
receipt
SYN Synchronisation EM End of Medium
ETB End of Transmission Block SUB Substitute
BS Back Space ESC Escape
HT Horizontal Tabulation SP Space
LF Line Feed NUL Null
CR Carriage Return DEL Delete
DC1 Device Control 1 DC2 Device Control 2
DC3 Device Control 3 DC4 Device Control 4
NAT National Use
Table 6: ASCII code key

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3. BINARY ARITHMETIC
The various arithmetic operations performed in computers and calculators concern
numbers expressed in binary notation. As such, numerical arithmetic can be a very
complex subject, particularly if you wish to understand all the calculation methods and the
theory on which they are based.
Fortunately, technicians do not have to learn the complete arithmetical theory, at least not
until you have become experienced programmers.
In this chapter, we are going concentrate our efforts on the basic principles that will enable
you to understand how computers perform basic arithmetic operations. We will only look at
the representation of integers.
Firstly, we will see how to carry out the binary arithmetic operations by hand, we will then
look at real logic circuits that materialise some of the operations in a digital system.
3.1. REPRESENTATION OF POSITIVE INTEGERS
Computers work in base 2 (binary). We must therefore represent decimal numbers in

binary.
For positive integers, we will use their equivalent representation in binary. As computers
have finite physical dimensions, there will be a maximum possible number of bits (logic
variables) depending on the machine, which will limit us in the size of the numbers.
In the case of a representation on 8 bits, we can represent 256 values, that is to say the
numbers 0 to 255.
In the general case of a representation on N bits, we have:
number of value 2N,
from 0 to 2N-1.
3.2. BINARY ADDITION
The addition of two binary numbers is just the same as the addition of two decimal
numbers. In fact, binary addition is simpler as fewer cases have to be learned.

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Let's start by going back to decimal additions:
376
+ 431
= 807
We start by adding the LSB column digits, which gives 7. We then add the second column
digits, which gives the sum of 10, that is 0 with 1 carried over to the third column. For the
third column, the sum of the two digits plus the 1 carried over gives 8.
The same rules apply to binary addition. However, only four cases can occur when you
add two binary digits, whatever their column.
These four cases are as follows:
0+0 = 0
1+0 = 1
1+1 = 10 = 0 + 1 carried over to the column to the left
1+1+1 = 11 = 1 + 1 carried over to the column to the left
The last case only occurs when, for a given column, we add two 1s plus a 1 carried over
from the column to the right.
Here are some examples of binary additions:
011 (3) 1001 11,011

+ 110 (6) + 1111 + 10,110
= 1001 (9) = 11000 = 110,001
There is no point studying additions with more than two binary numbers, because in all
digital systems the adder circuits do not process more than two numbers to be added; they
find the sum of the first two and then add that sum to the third number, and so on.
This isn't really a drawback, because, in general, modern digital machines can complete
an addition in a few nanoseconds.
Addition is the most important arithmetic operation in digital systems. The subtraction,
multiplication and division operations performed by computers are, essentially, simple
variations of the addition operation.

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3.3. REPRESENTATION OF SIGNED INTEGERS
We must define a convention for representing the sign in binary notation, as most
computers process negative numbers as well as positive numbers.
The first solution consists of adding a bit to the number. This is called the sign bit.
The simplest convention consists of assigning 0 state to the positive sign and 1 state to the
negative sign. This convention is known as sign-magnitude representation.
We use the sign bit to indicate whether the memorised binary number is positive or
negative.
Example:
A6 A5 A4 A3 A2 A1 A0
0 1 1 0 1 0 0 = + 5210
Sign bit Magnitude = 5210
A6 A5 A4 A3 A2 A1 A0
1 1 1 0 1 0 0 = - 5210
Sign bit Magnitude = 5210
The numbers reproduced in the example above are made up of a bit sign and six
magnitude bits. The latter correspond to the exact binary equivalent of the decimal value
presented.
Although the magnitude sign notation is direct, computers and calculators do not usually
use it because of the complexity of performing arithmetic operations with this notation. The
two's complement notation tends to be used more in these machines to represent signed
binary numbers.
Before examining how this works, we must see how to obtain the equivalent of a binary
number in one's equivalent and in two's equivalent.
3.3.1. Notation in one's complement
One's complement of a binary number is obtained by replacing each 0 with a 1 and each 1
with a 0. In other words, by complementing each bit in the number.

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Example:
101101 Initial binary number

010010 Complement of each bit to obtain one's complement
We say that one's complement of 101101 is 010010.
One's complement of a number is therefore the inversion of each bit using the NOT logic
function.
We can therefore express one's complement by means of the equation below:
One's complement of N: C1 (N) = not N
3.3.2. Two's complement notation
Two's complement is very widely used because it is the natural representation of negative
numbers. If we do the subtraction 2-3 we immediately obtain -1 represented in two's
complement.
0010 Number 2 in binary on 4 bits

-0011 Number 3 in binary on 4 bits
=1111 Result of the subtraction, there is a borrow
We are going to see that ‘1111’ is the representation of the number -1 on 4 bits.
Two's complement of a binary number is obtained by simply taking one's complement of

that number and adding 1 to the bit in its LSB column.
Example:
Conversion for 1011012 = 4510:
101101 Binary equivalent of 45

010010 Inversion of each bit to obtain one's complement
+ 1 Addition of 1 to obtain two's complement
= 010011 Two's complement of the initial binary number
Two's complement of a number is therefore the inversion of each bit by means of the NOT
function, followed by the addition of 1.
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We can therefore express two's complement by means of the equation below:
Two's complement of N: C2 (N) = C1 (N) + 1 = not N+1
Here is the value of the number -1 on 4 bits. We start by expressing the number 1 on 4
bits, than we apply the two's complement calculation rule.
0001 Binary equivalent of 1 on 4 bits

1110 Inversion of each bit to obtain one's complement
+ 1 Addition of 1 to obtain two's complement
= 1111 Two's complement of the number 1, that is: – 1
3.3.3. Study of binary numbers signed with two's complement
Here is how we write signed binary numbers using two's complement notation.
If the number is positive, its magnitude is the exact binary magnitude and its sign bit is a
0in front of the MSB. That is what we can see in the example above for + 4510.
Example :
0 1 0 1 1 0 1 = +4510
Sign bit Exact magnitude
1 0 1 0 0 1 1 = -4510
Sign bit Two's complement
If the number is negative, its magnitude is two's complement of the exact magnitude and
its sign bit is a 1 to the left of the MSB; you can see this in the representation of the
number -4510 above.
Two's complementation of a signed number transforms a positive number into a negative

number and vice versa.
Two's complement notation is used to express signed binary numbers because, as we will
see later on, using this notation we can do a subtraction when in reality we do an addition.

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This is important in the case of computers because, using the same circuits, we can do
subtractions and additions.
In many situations, the number of bits is defined by the length of the registers that contain
the binary numbers, hence the need to add 0s to obtain the required number of bits.
Example:
We are going to express +2 by means of 5 bits:
+2 = 00010
11101 One's complement
+ 1 Add 1
= 11110 Two's complement of the digit -2 on 5 bits

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4. COMBINATORIAL LOGIC
4.1. DEFINITIONS
4.1.1. The logic states
Boolean algebra is essentially different from ordinary algebra due to the constants and
variables that can only take two possible values: 0 and 1. A Boolean variable is a
magnitude which can, at different moments, take the value 1 or 0.
Boolean variables are often used to represent a system's state. We can say that a light is
either on or off.
We will materialise this by indicating that the light is either at 1 (for on) or at 0 (for off). This
is the same thing with a switch which is either open (0) or closed (1). So the Boolean
values 0 and 1 do not represent real numbers but, rather, the logic state of a variable. In
the area of numerical logic, we use other expressions that are synonymous with 0 and 1.
Logic level 0 Logic level 1
False True
Off On
Low High
No Yes
Open Closed
Table 7 : The different names of logic states
4.1.2. Positive logic and negative logic
By convention, when the active level 1 is greater than level 0 we say that we are using the
positive logic convention, otherwise we say that we are using the negative logic
convention.
Example:
Let us take a binary variable represented by a voltage that can take two values (0V, +5V),
it is possible to define the logic levels as shown in the tables below.

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Voltage Logic level
0V Low 0
+5 V High 1
Table 8 : Positive logic (1)
Voltage Logic level
0V High 1
+5 V Low 0
Table 9 : Negative logic (2)
4.1.3. The logic variables
A logic variable is a magnitude that can only take the two logic states. They are mutually
exclusive.
We will symbolise them by 0 or 1.
4.1.4. The logic functions
A logic function is a logic variable whose value depends on other variables.
Boolean algebra is a tool that makes it possible to express the effects that the various
digital circuits have on the logic variables and handle them with a view to determining the
best way of materialising a certain logic function.
Because there are only two possible values, Boolean algebra is more easy to use than
ordinary algebra.
In Boolean algebra, there are no fractions, decimal parts, negative numbers, square roots,
cubic roots, logarithms, imaginary numbers, etc.
In fact, in this algebra, there are only three basic operations:
The OR logic function, we will use the (+) symbol,
The AND logic function, we will use the (.) symbol,
The NOT inversion logic function.

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4.2. LOGIC FUNCTIONS WITH ONE AND TWO VARIABLES
The fact that the input variables have a finite number of possible values means that there
are a finite number of functions for a given number of variables.
We are going to start by examining the possible logic functions with one variable and then
with two variables.
By studying these two cases, we will discover all the basic operators in Boolean algebra,
and therefore the logic systems.
4.2.1. Functions with one variable
One variable, as we have seen earlier on, has two logic states (0 and 1) and enables us to
obtain 4 possible functions with that single variable (22).
Variable Functions F1.0 = constant = 0

A F1.0 F1.1 F1.2 F1.3 F1.1 = A
0 0 0 1 1 F1.2 = not A = not A = A
1 0 1 0 1 F1.3 = constant = 1
Table 10 : Functions with one variable
4.2.2. Functions with two variables
In the case of two variables, we have 4 possible combinations. We therefore obtain 16

possible functions with those two variables (24).
Variables Functions F2.x

A B 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Table 11 : Functions with two variables

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4.3. TRUTH TABLE
Many logic circuits have several inputs but only one output.
A truth table informs us of a logic circuit's reaction (its output value) to various
combinations of logic levels applied to the inputs.
B A X
0 0 ?
0 1 ?
1 0 ?
1 1 ?
Table 12 : Two-input truth table
C B A X
0 0 0 ?
0 0 1 ?
0 1 0 ?
0 1 1 ?
1 0 0 ?
1 0 1 ?
1 1 0 ?
1 1 1 ?
Table 13 : Three-input truth table

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D C B A X
0 0 0 0 ?
0 0 0 1 ?
0 0 1 0 ?
0 0 1 1 ?
0 1 0 0 ?
0 1 0 1 ?
0 1 1 0 ?
0 1 1 1 ?
1 0 0 0 ?
1 0 0 1 ?
1 0 1 0 ?
1 0 1 1 ?
1 1 0 0 ?
1 1 0 1 ?
1 1 1 0 ?
1 1 1 1 ?
Table 14 : Four-input truth table
In each of these tables, all the possible combinations of 0 and 1 for the inputs (D, C, B, A)
appear on the left, whereas output X's resulting logic level is given on the right. For the
moment there are only "? " in these columns, because the output values are different for
each circuit.
Remark:
Note that in the two-input truth table, there are four lines, in the three-input table there are
eight lines and in the four-input table there are sixteen.
You will have understood that for a table of N inputs, there are 2N lines. Furthermore, you
will no doubt note that the succession of combinations corresponds to the binary counting
sequence, in such a way that all the combinations can be determined directly and that you
cannot forget any of them.

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5. THE BASIC LOGIC OPERATIONS
5.1. THE OR OPERATOR
Let us take two independent logic variables, A and B. When we combine A and B by
means of the OR logic function, the result X is expressed using the following expression:
X=A+B
In this equation, the + sign indicates a logical OR. The output function is active if A OR B is
active. The following truth table defines how this operator functions:
A B X=A+B
0 0 0
0 1 1
1 0 1
1 1 1
Table 15 : OR operator truth table
5.1.1. The OR gate
Figure 1: Symbol for a two-input OR gate
A two-input OR gate is a circuit whose output is active if one or other of the inputs is
active.
Generally speaking, the output function from an n-input OR gate is active (level 1) if only
one input is active (logic level 1). The output function is inactive (logic level 0) if all the
inputs are inactive (logic level 0).

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5.2. THE AND OPERATOR
Let us take two independent logic variables, A and B. When we combine A and B by
means of the AND logic function, the result X is expressed symbolically using the following
expression:
X=A.B
In this expression, the (.) sign indicates the Boolean AND operation, whose operating rules
are given in the truth table below:
A B X=A.B
0 0 0
0 1 0
1 0 0
1 1 1
Table 16 : AND operator truth table
According to this table, you can easily deduce that the AND logic function corresponds to a
multiplication in binary. When A or B is 0, the product is null; when A and B are at 1, their
product is 1. We can therefore state that in the AND operation the answer is 1 only if all
the inputs are at 1, and that in all other cases it will be 0.
5.2.1. The AND gate
Figure 2: Symbol for a two-input AND gate
The figure above shows us a two-input AND gate. The output from this gate is equal to the
logic AND of the two inputs, that is to say X = A. B
In other words, the AND gate is a logic circuit that activates its output (logic level 1) only
when all its inputs are active (1). In all other cases, the output from the AND gate is
inactive (logic level 0).

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Generally speaking, the output function from an n-input AND gate is active (logic level 1)
only when all the inputs are active (logic level 1).
The output from an AND gate is inactive (logic level 0) if only one of the inputs is inactive
(logic level 0).
5.3. THE NOT OPERATOR
The NOT operator, unlike the AND and OR operators, only concerns one input variable.
For example, if variable A is submitted to a NOT operation, the result is given by the
following expression:
X=A
The NOT operation is also called the inversion or complementation operation. A different
sign is used to indicate an inversion: an exclamation mark (!). So:
!A = A
A X=A
0 1
1 0
Table 17 : NOT operator truth table
5.3.1. NOT inverter circuit
The figure below shows the symbol used for a NOT circuit, more commonly called
inverter. This type of circuit always has only one input, and its output takes the logic level
opposite to the input's logic level.
Figure 3: Symbol for a NOT gate

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5.4. THE NOR and NAND GATES
In digital systems, there are very often two other types of logic gate: the NOR gate and the
NAND gate.
In fact, these two gates correspond to combinations of basic AND, OR and NOT
operations, and it is relatively easy to describe them using the Boolean algebra functions
that you already know.
5.4.1. The NOR gate
Figure 4: Symbol for a NOR gate
In the figure above, you can see the symbol for the two-input NOR gate. You will note that
it is the symbol of an OR gate, but with a little circle at its tip. This little circle corresponds
to an inversion operation. NOR gate operation is therefore similar to that of an OR gate
followed by an INVERTER.
The output expression from a NOR gate is: X = A + B
The truth table below shows us that the output from a NOR gate is exactly the reverse of
the output from an OR gate for all the input combinations.
A B X = A+ B
0 0 1
0 1 0
1 0 0
1 1 0
Table 18 : NOR operator truth table
In general, the output function from an n-input NOR gate is only active (logic level 1) when
all the inputs are inactive (logic level 0). The output from a NOR gate is inactive (logic level
0) if only one of the inputs is active (logic level 1).
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With De Morgan's theorem, we can show that the NOR gate is equivalent to:
W = A+ B = A×B
5.4.2. The NAND gate
Figure 5: Symbol for a NAND gate
You can see that this is the symbol for an AND gate, but with a little circle at its tip.
Once again, this little circle corresponds to an inversion operation. NAND gate operation is
therefore similar to that of an AND gate followed by an INVERTER.
The output expression from a NAND gate is: X = A × B
A B X = A× B
0 0 1
0 1 1
1 0 1
1 1 0
Table 19: NAND gate truth table
The truth table above shows us that the output from a NAND gate is exactly the reverse of
the output from an AND gate for all the input combinations.

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In general, the output function from an n-input NAND gate is only active (logic level 1) if
only one input is inactive (logic level 0). The output from a NAND gate is inactive (logic
level 0) only when all the inputs are active (logic level 1).
With De Morgan's theorem, we can show that the NAND gate is equivalent to:
X = A× B = A + B

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5.5. EXCLUSIVE OR (XOR) and EXCLUSIVE NOR (XNOR) CIRCUITS
There are two special logic circuits, which are often used in digital systems: the exclusive
OR circuit and the exclusive NOR circuit.
5.5.1. The Exclusive OR (XOR) gate
Figure 6: Symbol for an exclusive OR gate
The output from an Exclusive OR gate is high only when the two inputs are at different
logic levels. Exclusive OR gates always have two inputs only. By that, we mean that
Exclusive OR gates with three or four inputs do not exist.
These two inputs are combined so that: X = A B + AB
This expression is abbreviated as follows: X = A ⊕ B
A B X = A⊕ B
0 0 0
0 1 1
1 0 1
1 1 0
Table 20 : Exclusive OR operator truth table
In general, the output function from an exclusive OR gate indicates the difference between
the two input signals. The output is active (logic level 1) if the inputs have different logic
states.

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5.5.2. The Exclusive NOR (XNOR) gate
Figure 7 : Symbol for an Exclusive XNOR gate
The operation of an exclusive XNOR circuit is the exact opposite of that of an exclusive
OR circuit. The output from an Exclusive XNOR gate is at its high level only when the two
inputs are at the same logic levels.
This is expressed as follows: X = AB # AB
This expression is abbreviated: X = A ⊕ B
A B X = A⊕ B
0 0 1
0 1 0
1 0 0
1 1 1
Table 21 : Exclusive NOR operator truth table
In general, the output from an exclusive NOR gate indicates that the two input signals are
equal. The output is active (logic level 1) if the logic state of the two inputs is identical.
This gate's operation corresponds to a one-bit comparator.
The exclusive NOR operator has a special property. The output inversion can be applied
to one or other of the inputs, that is to say:
A⊕ B = A ⊕ B = A⊕ B
We can demonstrate this property using Boolean algebra.

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5.6. SYMBOLS USED FOR THE BASIC OPERATIONS
Logic function European symbol American symbol Truth table
IO
YES
00
I=O
11
NO IO
01
O=I 10
abO
AND
000
010
O=a.b
100
111
abO
OR
000
011
O=a+b
101
111
abO
NAND
001
011
O = a×b 101
110
abO
NOR
001
010
O =a+b 100
110

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Logic function European symbol American symbol Truth table
abO
Exclusive OR
(EXOR) 000
011
O = a⊕b 101
110
abO
Exclusive NOR
(EXNOR) 001
010
O = a⊕b 100
111
Table 22 : Table summarising the logic gate symbols

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5.7. PUTTING LOGIC CIRCUITS INTO ALGEBRAIC FORM
Any logic circuit, whatever its complexity, can be described by means of the Boolean
operations that have already been described, because the AND gate, OR gate and NOT
gate are the basic component circuits of digital systems.
By using the Boolean expression for each of the gates, we can easily find the equation
corresponding to the output.
Example:
Figure 8: Example of a circuit made with an AND gate and an OR gate
The output from the AND gate is expressed as: A. B
This combination is an input to the OR gate, whose other input is the signal C.
The effect of the latter gate is to add its inputs logically, which gives the output expression:
X = A. B + C (this equation could also have been written X = C + A. B, because the order
of the terms in an OR function is immaterial).
By convention, in an expression containing AND and OR operators, it is the AND

operators that are applied first, except if there are brackets; in which case you must
evaluate the expression in brackets before everything else.
This rule for determining the order of the operations is the same as the rule used in
ordinary algebra.
Figure 9: Example of a logic circuit where the expression of the output is in brackets
Here is another example, the result of the OR gate is simply A + B. The output from this
gate is sent to the input of the AND gate, and the latter's other input receives signal C.
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The expression of the output from the AND gate is therefore: X = (A + B) . C
You can see that by using brackets you can indicate that the OR operator applies first of
all to A and B.
The AND operator is then applied to the output from the OR gate and input C.
Without the brackets, our interpretation would be incorrect, because X = A + B . C means

that A is joined in an OR gate with the product B . C
The AND operator (.) takes priority over the OR operator.
5.7.1. Circuit including INVERTERS
Whenever you have an INVERTER in the diagram of a logic circuit, its equation is simply
the expression of its input with a line above it.
Examples:
Figure 10: Example with an inverter on input A to the OR gate
In this example, input A passes through an INVERTER whose output is A . This output
from the inverter is joined together with B in an OR gate, so that the output equation from
this gate is equal to A + B
Figure 11: Example with an inverter on the output from the OR gate
In this example, the output from the OR gate equals A + B, and this output is fed into an
INVERTER. Output X from the latter therefore becomes ( A + B) , because the complete
expression is inverted.

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5.8. MATERIALISATION OF CIRCUITS FROM BOOLEAN EXPRESSIONS
If the operation of a circuit is defined by a Boolean expression, it is possible to draw a logic

diagram directly from that expression.
For example, if you need a circuit such that X = ABC, you immediately know that you need
a three-input AND gate. The reasoning that we used for these simple cases can be
extended to other more complex circuits.
Example:
Let us suppose that we wish to build a circuit whose output is Y = AC + BC + A BC
This Boolean expression consists of three terms ( AC , BC , A BC ) which are added together
logically. From this we can deduce that we need an OR gate with 3n inputs to which the
AC, BC, ABC signals are applied respectively.
Each input to the OR gate is a logic product, which means that we needed three AND
gates fed by the appropriate inputs to produce these terms.
From this, we can therefore easily deduce the logic circuit that we will have to make.
Figure 12: Example of the construction of a logic circuit deduced from a Boolean
expression

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5.9. BOOLEAN ALGEBRA
We have seen how Boolean algebra can be used to analyse a logic circuit and express
that circuit in mathematical form. We are going to start with the two postulates governing
BOOLEAN algebra.
5.9.1. Postulates
We have two postulates:

A+ A =1
A× A = 0
These two postulates materialise the fact that the inverse of a variable can never take the
same value as the variable.
We will see later on that a violation of these postulates is possible at the time of the
transient states in the circuits.
This violation may cause random behaviour on the functions that depend on those
variables.
5.9.2. Boole's theorem for a variable
Boole's theorem is a rule that makes it possible to simplify logic expressions and, at the
same time, logic circuits.
According to the following theorems, X is a logic variable that takes either the value 0, or
the value 1:
X ×0 = 0
X ×1 = 1
X×X = X
X×X =0
X +0 = X
X +1 = X
X+X =X
X + X =1
Before introducing you to Boole's other theorems, we must mention that in the theorems
above, the variable X may correspond to an expression that includes more than one
variable.

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For example, if we have AB( AB), we can say that, by posing X = AB and according to the
theorem, the equation is equal to 0.
5.9.3. Theorems for several variables
The following theorems concern more than one variable:
Theorem No. 1: X + Y = Y + X
Theorem No. 2: X . Y = Y . X
Theorem No. 3: X + ( Y + Z ) = (X + Y) + Z = X + Y + Z
Theorem No. 4: X ( YZ ) = ( XY ) Z = XYZ
Theorem No. 5: X ( Y + Z ) = XY + XZ
Theorem No. 6: ( W + X ) . (Y + Z ) = WY + XY + WZ + XZ
Theorem No. 7: X + XY = X
Theorem No. 8: X + XY = X + Y
Theorems 1 and 2 show that AND and OR are commutative composition laws
(commutativity), so the order of the multiplication or logic addition of the two variables is
immaterial, the result will be the same.
Theorems 3 and 4 show that AND and OR are associative composition laws
(associativity), which means that we can group together, in any way we want, the
variables in a multiplication or logic addition expression.
Theorems 5 and 6 show us that the logic multiplication is distributive with respect to the
logic addition, that is to say we can develop an expression by multiplying it term by term,
just like in ordinary algebra. This theorem also demonstrates that an expression can be
factorised. By that, we mean that if we have a sum of terms, each of which includes a
common variable, it is possible to factorise that variable, just as you can in ordinary
algebra.
Theorems 1 to 6 are easy to remember because they are identical to those in ordinary
algebra. But theorems 7 and 8, however, are not found in ordinary algebra. They can be
demonstrated by verifying all the possibilities of X and Y.
All these theorems are extremely useful for simplifying a logic expression, that is to say to
obtain an expression with fewer terms. The simplified expression makes it possible to
make a circuit that is less complex than the one corresponding to the original expression.
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5.9.4. DE MORGAN's theorem
We owe two of the most important theorems in Boolean algebra to the mathematician De
Morgan. De Morgan's theorems are extremely useful for simplifying expressions that
include sums or products of complemented variables.
Here are the two theorems:
1st theorem: ( X + Y ) = X × Y
2nd theorem: ( X × Y ) = X + Y
De Morgan's 1st theorem states that the complemented logical sum of two variables is
equal to the logical product of the complements of those two variables.
Likewise, the 2nd theorem stipulates that the complemented logical product of two
variables is equal to the logical sum of the complements of those two variables.
These two theorems can be demonstrated simply by verifying all the possibilities of X and
Y.
Although these theorems were formulated for the simple X and Y variables, they remain
equally true for the cases where X and Y are expressions including several variables.
To illustrate this, let us apply these theorems to the following expression:
( AB + C ) = ( AB ) × C
The result you obtain can be simplified once more, because there is still a complemented
logical product. By virtue of the 2nd theorem, we obtain:
AB × C = ( A + B) × C
As B = B , the definitive result is then:
AB × C = AC + BC

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6. COMBINATORIAL LOGIC CIRCUITS

In the previous chapter, we looked at all the basic logic gates and, using Boolean algebra,
we managed to describe and analyse circuits materialised by combinations of logic gates.
We can say that these logic circuits are combinatorial because at any moment the logic
level collected at the output only depends on the logic levels applied to the inputs.
A combinatorial circuit does not have any storage mechanism (memory); consequently, its
output only reacts to the signals present at its inputs.
In this chapter, we are therefore going to study combinatorial circuits. Firstly, we are going
to place the accent on the simplification (minimisation) of circuits. To do this, we are going
to use two methods:
Boolean algebra and a graphic technique,
Karnaugh maps.
6.1. SUM OF PRODUCTS
The methods for simplifying and designing logic circuits that we are going to examine
mean that we have to express the logic equations in the form of a sum of products, some
examples of which are given here:
ABC + ABC
AB + A BC + C D + D
A B + CD + EF + GK
Each of these three expressions of a sum of products is made up of at least two terms of a
logical product (AND term) in relation with the OR operator.
Each AND term includes one or more variables expressed in its normal form or in its
complemented form.
For example, in the sum of products ABC + A BC , the first logical product consists of the
non-complemented variables A, B and C, whereas the second product includes the non-
complemented variable B and the complemented variables A and C. You must note that in
a sum of products, the complementation sign cannot be placed above more than one
variable in a term (for example, you cannot have ABC ).

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6.2. SIMPLIFICATION OF LOGIC CIRCUITS
Once you have the expression of a logic circuit, it may be possible to minimise in order to
obtain an equation counting fewer terms or fewer variables per term.
This new equation can then serve as a model for constructing a circuit that is entirely
equivalent to the original circuit but which requires fewer gates.
Example of the simplification of logic circuits:
Figure 13: Example of the simplification of logic circuits
We have simplified the first circuit, given that they produce the same logical decisions. It
goes without saying that the simpler circuit is preferable because it has fewer gates; it is
also smaller and less costly to produce.
In the following chapters, we will see two different ways of simplifying logic circuits. The
first way is based on the application of Boolean algebra theorems; this way, as we will see,
depends very greatly on instinct and experience.
The other way (Karnaugh maps), on the contrary, follows a systematic approach, similar to
a recipe.
6.3. ALGEBRAIC SIMPLIFICATION
The Boolean algebra theorems studied in the previous chapter can be of great help for
simplifying the expression of a logic circuit. Unfortunately, it is not always easy to know
which theorems you should use to obtain the best result. Furthermore, there is nothing to
say that the simplified expression is in its most minimised form and that there are no other
possible simplifications.

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For all these reasons, algebraic simplification is often a process of successive

approximations.
There are, however, two essential steps:
Successive applications of De Morgan's theorems with a view to obtaining a sum of

products,
Finding common variables so they can be factorised.
Example:
Z = ABC + AB ( A C )
Z = ABC + AB ( A + C ) : De Morgan's theorem
Z = ABC + AB ( A + C ) : Cancellation of the double complementation
Z = ABC + AB A + AB C : Distribution of the AND
Z = ABC + AB + AB C
Z = AC ( B + B ) + AB : Simplification by factorisation
Z = AC (1) + AB
Z = AC + AB
6.4. DESIGNING COMBINATORIAL LOGIC CIRCUITS
Frequently, the expression of requirements for a logic circuit to be designed is given in text
form (e.g. a functional analysis). This form cannot be used to determine a circuit's
equation. The truth table is used to specify how the circuit operates.
This first phase corresponds to the circuit's design. The following steps will allow us to
determine the logical diagram. This then concerns the reinitialisation steps.
The first design step will be seen in the exercises. Here, we are going to give all the
development steps allowing us to go from the circuit's truth table to its logic diagram.
The truth table specifies the output's logic level for each combination of inputs. We can
then determine the circuit's Boolean expression from this truth table.

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Here is the general procedure that brings us to the expression of the output from a truth
table:
For each case in the table that gives 1 as output, we write the logical product (AND
term) that corresponds to it.
We must find all the input variables in each AND term either in direct form or in
complemented form. In one particular case, if the variable is 0, then its symbol is
complemented in the corresponding AND term,
We then logically sum (OR operator) all the logical products obtained, which gives
the definitive expression of the output.
The truth table enables us to establish the expression of the output in the form of a sum of
products. It is then possible to construct the circuit using AND, OR and NOT gates. You
need an AND gate for each logical product and an OR gate whose inputs are the outputs
from the AND gates.
Generally, it is possible to simplify the expression obtained. The goal is to make the
simplest circuit possible. It will be cheaper and often faster!
Example:
N° C B A X Minterm equation
0 0 0 0 0
1 0 0 1 0
2 0 1 0 1 CB A
3 0 1 1 1 C BA
4 1 0 0 0
5 1 0 1 0
6 1 1 0 0
7 1 1 1 1 CBA
In this example, we can see that there are three combinations that produce a value 1 for
output X. The AND terms for each of these combinations are given on the right of the truth
table. We use the term minterm equation for this.
The complete expression is obtained by doing logic ORs for these three minterms, which
gives us:
X = C BA + C BA + CBA

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We can write this logic expression in a compact form by indicating only the number of the
minterms that are at 1, that is:
X = ∑ 2,3,7
We now have a non-simplified logic equation. The first solution is to use Boolean algebra
to look for the simplest expression. This requires a great deal of experience and practice.
But there is an effective graphic method: the Karnaugh map.
6.5. THE KARNAUGH MAP METHOD
The Karnaugh map is a graphic tool that makes it possible to simplify a logic equation in a
methodical way. We can then obtain the optimum diagram corresponding to the
combinatorial logic circuit.
Although the Karnaugh maps can be used for problems with any number of input
variables, in practice, they are not particularly useful when there are more than 6 variables.
In addition, in this section of the course, we are not going to look at problems with more
than four inputs.
Cases of circuits with five or six inputs pose major problems. Above that, it is advisable to
solve Karnaugh maps with a computer programme.
6.5.1. Construction of the Karnaugh map
Just like the truth table, the Karnaugh map is an instrument that evidences the
correspondence between the logic inputs and the output you want to obtain.
The figure below shows us three examples of Karnaugh maps for two, three and four
variables, along with the corresponding truth tables.
B A X
0 0 1 BA B
0 1 0 A 0 1
1 0 0 0 1 0
1 1 1 BA 1 0 1
Figure 14: Example of a truth table with its associated Karnaugh map

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The truth table gives the value of the output X (figure on the left), but the Karnaugh map
organises the information in a different way. For each line of the truth table, there is a
corresponding box in the Karnaugh map.
But the boxes in the Karnaugh map are not in the same order.
For example, in the figure above, the truth table's B A = 0 0 line corresponds to the box
situated at the intersection of B = 0 and A = 0 in the Karnaugh map.
B A X
0 0 1 BA B
0 1 0 A 0 1
1 0 0 0 1 0
1 1 1 BA 1 0 1
Given that for this line X equals 1, we write 1 in this box. Likewise, we associate the box
whose coordinates are B = 1 and A = 1 with the B A = 1 1 line. As X equals 1 in this case,
we will find 1 in that box.
The construction of the Karnaugh map guarantees that only one variable changes
between two adjacent boxes.
Example:
In the table below, we are going to see the case of the box situated at the intersection of
C B = 1 1 and A = 0 which corresponds to the minterm = CBA
C B A X CB
0 0 0 1 CBA A 00 01 11 10
0 0 1 1 C BA 0 CBA CB A CB A CBA
0 1 0 1 CB A 1 C BA C BA CBA C BA
0 1 1 0
1 0 0 0 CB
1 0 1 0 A 00 01 11 10
1 1 0 1 CB A 0 1 1 1 0
1 1 1 0 1 1 0 0 0

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We have three adjacent boxes, that is: C BA
adjacent box to the right C B = 10 and A = 0, minterm = CB A variable B changes;
adjacent box to the left C B = 0 1 and A = 0, minterm = C BA variable C changes,
adjacent box below C B = 1 1 and A = 1, minterm = CBA variable A changes.
We can therefore see another property of the Karnaugh map, each box has as many
adjacent boxes as there are variables.
6.5.2. Group
It is possible to simplify the expression of output X by combining, according to precise

rules, the boxes in the Karnaugh map that contain 1s. This combination process is known
as a group.
6.5.2.1. Group of twos
CB
A 00 01 11 10
0 0 1 0 0
1 0 1 0 0
Figure 15: Example of groups of twos in the Karnaugh map
The example above reproduces the Karnaugh map corresponding to a certain truth table
with three variables. In this map, there are two vertically adjacent 1s.
These two terms can be grouped (combined), which results in the variable A being
eliminated.
The same principle always applies for any vertically or horizontally adjacent pairs of 1s.
The top line is considered to be adjacent to the bottom line, and ditto for the leftmost
column and the rightmost column.
We can simplify variable A using Boolean algebra. The logic equation of the grouping
corresponds to the logical sum of the two minterms, that is:
Minterm for the top box: C BA

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Minterm for the bottom box: C BA
Hence the equation: C BA + C BA = C B × ( A + A) = C B × 1 = C B
6.5.2.2. Groups of four
DC
BA 00 01 11 10
00 0 0 0 0 CB
01 0 0 0 0 A 00 01 11 10
11 1 1 1 1 0 0 0 1 1
10 0 0 0 0 1 0 0 1 1
a) X = BA b) X = C
DC DC
BA 00 01 11 10 BA 00 01 11 10
00 0 0 0 0 00 1 0 0 1
01 0 1 1 0 01 0 0 0 0
11 0 1 1 0 11 0 0 0 0
10 0 0 0 0 10 1 0 0 1
c) X = CA d) X = C A
Figure 16: Example of groups of four
A Karnaugh map may contain four adjacent 1s. The figure above shows several examples
of groups of four.
In a), the four 1s are adjacent horizontally, whereas in b), they are adjacent vertically.
The table in c) has four 1s arranged in a square that are considered to be adjacent to each
other.
The 1s in d) are also adjacent because, as we have already said, in a Karnaugh map, the
top and bottom lines and the right and left columns are considered to be adjacent.

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6.5.2.3. Groups of eight
When eight adjacent 1s are grouped together, we say that there is a group of eight. In the
figure below, we can see two examples of groups of eight. A group of eight in a Karnaugh
map with four variables gives rise to the elimination of three variables.
DC DC
BA 00 01 11 10 BA 00 01 11 10
00 0 0 0 0 00 1 0 0 1
01 1 1 1 1 01 1 0 0 1
11 1 1 1 1 11 1 0 0 1
10 0 0 0 0 10 1 0 0 1
a) X = A b) X = C
Figure 17: Example of a group of eight
6.5.3. The complete simplification process
We have just seen how groups of two, four and eight adjacent 1s in a Karnaugh map lead
to a simplified expression.
It is clear that the more 1s that are grouped together, the greater the number of variables
eliminated will be. More precisely, a group of two 1s causes the elimination of one
variable, a group of four 1s, the elimination of two variables and a group of eight 1s, the
elimination of three variables and so on.
The group of 2n 1s makes it possible to simplify n variables. Here are the steps for
simplifying a Boolean expression using the Karnaugh maps method:
Draw the Karnaugh map and place the 1s in the squares corresponding to the lines
in the truth table whose output is 1. Place a 0 in the other squares,
Examine the Karnaugh map and identify the possible groups. Find the largest ones,
Then start by circling the so-called isolated 1s that belong to a single group. That
means that for those 1s, there is only one grouping possibility,
Then continue to take the largest groups that include 1s (a single one at least) that
do not belong to another group,
You must take all the 1s in the Karnaugh map. It is permitted to use the same 1
several times,
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Perform logic ORs between all the terms resulting from the groupings.
6.5.4. "Don't Care" conditions
Certain logic circuits can be designed for certain combinations of inputs that do not
correspond to any particular logic state for the output. The main reason is often that these
combinations of inputs will never occur. In other words, there are certain combinations of
inputs for which it does not really matter whether the output is HIGH or LOW.
Example:
CB
C B A Z A 00 01 11 10
0 0 0 0 0 0 0 1 X
0 0 1 0 1 0 0 1 1
0 1 0 0 Z=A
0 1 1 X
1 0 0 X CB
1 0 1 1 A 00 01 11 10
1 0 0 1 0 0 0 1 1
1 0 1 1 1 0 0 1 1
Figure 18: Example of a Karnaugh application with different states
In this table, none of the states of output Z is present for the combinations C B A = 100
and C B A = 0 1 1. On the contrary, we have written an X. This X means a "don't care"
condition.
There are several reasons that can explain the presence of "don't care" conditions, the
most common being that, in certain situations, these input combinations can never occur
and so there is no point indicating an output value for those combinations.
In the presence of "don't care" conditions, we must indicate which output X is replaced by
a 0 and which X is replaced by a 1. The choice is given by looking for the most efficient
way of grouping together the adjacent 1s in the Karnaugh map. The goal is to obtain the
simplest expression.

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6.6. THE STANDARD COMBINATORIAL FUNCTIONS
When the problem to be solved includes more than four or five inputs, the methodology
using the truth table and the Karnaugh map no longer applies.
We have seen that the use of Karnaugh maps is limited to 4 or 5 variables. It will also be
difficult to establish a truth table when the number of inputs is high. If we have a system
with 10 inputs, the truth table will have 1024 lines! We must therefore adapt our
methodology.
It will be a question of breaking our problem down. We must be capable of identifying sub-
functions.
We then need to examine the main standard combinatorial functions. These functions are
also called MSI functions for ‘Medium Scale Integration’. These are functions that are more
complex than simple logic gates.
These functions were very quickly integrated into circuits in the TTL and CMOS families.
They have the advantage of being less costly in the form of an electronic circuit. The most
commonly used functions have been integrated.
Here is a list of the main standard combinatorial functions:
multiplexing (MUX)
decoding (X/Y)
priority encoder
comparator (COMP)
arithmetic operators (addition, subtraction, etc.)
transcoding of numbers: BIN→BCD, BCD→BIN, BCD→7SEG, etc……

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6.7. MULTIPLEXER
A multiplexer is a combinatorial system that puts its only output at the value of one of its 2n
data inputs, the number of the selected input being provided on the n command inputs.
Here we show the truth table for a 2 to 1 multiplexer, its logic diagram and the IEC
symbols for this function:
Sel In1 In0 Output

0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
compact TDV
Sel Output
0 In0
1 In1
Figure 19: The multiplexer, its truth table, logic diagram and symbol

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Figure 20: The diagram for circuit ALS157 containing four 2 to 1 multiplexers, IEC symbol
Note that we have 4 multiplexers with the same command block in the standard circuit
(74ALS157). Multiplexers are symbolised by superimposed rectangles, with the first one
marked MUX.
The command block is shown as a rectangle with notches on top of 4 blocks. An additional
EN (ENable) input appears. The output from multiplexers is only active if the EN input = 1,
which is equivalent to saying that terminal 15 is at its low level.
In the multiplexing block, the input marked 1 indicates that the output takes the value of B
if the selection input G1, terminal 1, takes the value 1 (high level). Input A will be taken into
account for G1 = 0. The numbers in brackets are the numbers of the circuit's terminals.

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Figure 21: Diagrams of some common multiplexers

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6.8. DECODER
A decoder is used to identify which combination is active. It includes an input with n bits to
be decoded (selection), a validation input (enable), and 2n outputs. The output whose
number corresponds to the coded value given at input will be active if the enable is active.
All the other outputs are inactive. The decoder only has one active output at a time.
If the validation input is inactive, all the outputs will be inactive.
EN Sel Output1 Output0

0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 0
Figure 22: 1 to 2 decoder with enable input
You will see that decoders often have low active outputs.
Figure 23: Example of a standard circuit with two 2-to-4 decoders

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The figure below shows a 2-to-4 decoder. The selection signal is comprised of 2 bits.
There will then be 4 outputs because there are 22 possible combinations for the selection.
This decoder also has an activation signal (enable). When it is inactive (logic state 1, low
active), all the outputs are inactive (state 0). When the authorisation signal (enable) is
active, the output corresponding to the selection code is active.
EN Sel1 Sel0 Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Figure 24: 2-to-4 decoder with enable
Here is a decoder with 3 selection bits, it makes it possible to decode the 8 combinations
of a 3-bit vector.
Figure 25: Decoder with 3 selection bits
In circuit ALS138, activation of the outputs depends on EN, which is the result of AND
between the inputs ( G1, G 2 A, G 2 B ).
EN = G1 × G 2 A × G 2 B

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6.9. COMPARATOR
The function for making a comparison between two binary numbers is very frequently
used. A comparator is a circuit that indicates whether two binary numbers are higher,
equal or lower. In the case of a modular circuit, there are three inputs in order to determine
whether the previous bits are higher, equal or lower.
Figure a) below gives us the IEC symbol of an "equals" comparator with the ‘=’ input for
the chaining.
Figure b) gives us the IEC symbol of a 4-bit modular comparator with the three ‘<’, ‘=’, ‘>’
outputs.
Figure 26: The comparator
The function for comparing N bits can be broken down with several 1-bit comparators.
This breakdown may be done in series or in parallel; the figure below shows us the series
breakdown of the comparison.
We start with the Least Significant Bits.
This breakdown requires less in terms of hardware, but the propagation time through the
complete comparator is longer.
The propagation time is: tp COMPn = N × tp COMP1

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Figure 27: Series breakdown of the comparison
Figure 28: Parallel breakdown of the comparison
The figure above shows the parallel breakdown of the comparison. Each bit is compared
then an AND gate calculates the result. This breakdown requires an AND gate with N
inputs.
The advantage is that you will have a much shorter propagation time, i.e.:
tp COMPn = 1 × tp COMP1 + tp ET

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7. ELEMENTARY MEMORIES
Until now, the systems studied were combinatorial systems, that is to say that
there is one and one only combination of output variables for each combination of
input variables. Combinatorial logic quickly reaches its limits and not many systems that
use this method. Indeed, in most cases it is difficult to keep the combination of input
variables corresponding to one action.
Let us take the simple case of a bench-mounted drill: in combinatorial logic, in order to
make the spindle rotate, the operator must keep the "spindle rotation" pushbutton held
down, otherwise the spindle will stop rotating. He will therefore not be able to hold the
part to be drilled and lower the drill to carry out the drilling operation.
To overcome this problem, we simply need the machine "to remember" that the spindle
rotation button has been pressed, in other words the machine must have a memory
function.
A logic system based on the utilisation of the memory function introduced here will be
called sequential logic.
7.1. STUDY OF THE MEMORY FUNCTION
7.1.1. Terms of the problem
We propose here to look for the logical diagrams of a sequential circuit with two inputs and
one output.
This circuit's operating conditions are as follows:
R and S cannot change simultaneously.
the combination R S = 01 leads to Q =1.
the combination R S =10 leads to Q = O.
the combination R S = 0.0 keeps the previous state.
the combination R S = 1.1 leads to either Q =1 (priority closing) or Q = 0 (priority

opening).

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R is the resetting or clearing variable (R -> Reset).
S is the setting or write variable (S -> Set).
Furthermore, we assume that the time separating two consecutive changes of state of
R and of S is longer than the memory's overall response time.
7.2. STABLE STATES GRAPH
7.2.1. Definition: stable states, transient states.
A sequential circuit is in a stable state when all of that circuit's component parts are
themselves in a stable state. This state will be characterised by a perfect knowledge of:
the state of the input variables corresponding to that state,
and of the state of the output functions generated by that state.
From here on, we will identify a stable state with a letter or number (arbitrary) in a
circle.
The diagrams that we are seeking to establish are going to be materialised by

technological components. But, it is natural to think that these components have a non-
null response time; that is to say that between the moment when they receive an exciter
state and the moment when they take the corresponding new state, a time t – called the
response time – elapses.
During this time t the circuit is no longer in a stable state because it is in the process of
changing: it is said to be in a transient state. From here on, we will identify them with a
non-circled letter or number, which characterises the stable state towards which the
change will be made.
7.2.2. Construction of the stable states graph.
It is constructed in the following way:
the initial phase (rest state) is numbered 1,
the possible stable phases are numbered in turn, with each number circled.
links, joining these different phases, indicate the possible transitions from one
stable phase to the other. The transition direction is indicated by an arrow,

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We write:
close to each circle, the combination of input stable states and the
corresponding state (or states) of the output function,
after each link, the combination of input variables that cause and characterise the
transition;
We give it a shape that reveals the possible symmetries to the best. The diagram of our
problem's stable states will therefore be as follows:
Figure 29: Stable states graph

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7.3. PRIMITIVE MATRIX
This is in fact a table with the same presentation as the Karnaugh maps. It is constructed
in the following way:
The number of columns is equal to the number of combinations that can be made
with the independent input variables at your disposal (primary variables).
The number of lines is equal to the number of stable phases to which the problem
posed leads.
Each stable phase is entered in the chronological order of occurrence in the column
corresponding to the combination of primary input variables that gave rise to it.
Each unstable phase (transient) preceding each stable phase is entered in the
same column as the phase following it, on the previous line.
RS
00 01 11 10 Q
c 2 - 4 0
3 d 5 or 6 - 1
e 2 - 4 1
1 - 5 or 6 f 0
- 2 g 4 0
- 2 h 4 1
Figure 30: Primitive matrix
The non-determination corresponding to the combination R S = 1 1 reveals two states 5

and 6, hence the choice of 5 or 6 on lines 3 and 4 and the stable states 5 and 6 on lines 5
and 6.
In this primitive matrix we can see that for the combination R S = 0 0 output Q may be
equal to 1 (line 3) or equal to 0 (line 0).
In order to differentiate between these two lines, input variables R and S alone are
insufficient; to do this we need to introduce a secondary variable (or internal variable).

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7.4. PRIORITY RESETTING MATRIX
In this first case, we do not take into account line 6 (R S = 1→ Q = 1), and we only keep
lines 1, 2, 3, 4 and S.
7.4.1. Contracted matrix
Contracting a primitive matrix is equivalent to merging the matrix's lines to obtain a

reduced matrix, and the number of lines in the reduced matrix determines the number of
secondary variables to be used.
We can only merge two lines if they do not have a stable state in the same column.
Figure 31: Contracted matrix
7.4.2. Secondary variable equation and output equation
The secondary variables are encoded by taking as value for Q's unstable states the same
value as that of the corresponding stable state.
Figure 32: Secondary variable equation and output equation

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7.4.3. Logic diagram of a priority resetting memory
Figure 33: Logic diagram of a priority resetting memory

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7.5. PRIORITY SETTING MEMORY
In this second case, we do not take into account line 5 (R S = 1 1 -> Q = 0), we only keep
lines 1, 2, 3, 4 and 6.
7.5.1. Concentrated matrix
Figure 34: Concentrated matrix
7.5.2. Secondary variable equation and output Q equation
Figure 35: Secondary variable equation and output Q equation
7.5.3. Logic diagram of a priority setting memory
Figure 36: Logic diagram of a priority setting memory

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7.6. TRUTH TABLE FOR AN RS MEMORY
R S Qn Remarks
0 0 Qn-1 Memory state
0 1 1 Set to 1 (S = Set)
1 0 0 Reset to 0 (R = Reset)
1 1 -
Table 23: A memory's truth table
Qn-1: Q's previous state
Qn: Q's next state after action on inputs R and S
By prohibiting the use of this combination for inputs R and S, we have a single implication
table for the RS memories.
Furthermore this combination may pose problems if we attempt to pass directly from the
latter to the combination R S = 0 0, we arrive at a random type of memory operation.
In fact it will then be impossible to know the state of output Q (Q can equal 1 or 0) because
two variables cannot simultaneously change state, there will always be one that changes
state before the other, but which one?
Remark:
Given their drawbacks, RS memories are not commercialised, however RS memories are
found (usually called a "latch"), the most common application of this memory being the
anti-bounce circuit.
R S Q1n Q2n
0 0 - -
0 1 0 1
1 0 1 0
1 1 Q1n-1 Q2n-1
Figure 37: Logic diagram for an R S memory

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Example:
Let us examine what happens when we close a switch (end-of-travel sensor, etc.).
Each time the sensor (PB) is operated, there is a

bounce before the contact is definitively held.
Figure 38: Example of RS memory
For an ordinary contact, there may be as many as ten

bounces in a few milliseconds.
For the command of devices with a relatively high time

constant, these bounces are not harmful for operation
(relays, lamps, etc.); however, integrated circuits react
in a few nanoseconds. Everything therefore takes
place with the bounces, as if we acted several times on the sensor instead of just once. It
is therefore necessary to use a device that makes it possible to eliminate these bounces.
Figure 39: Bounces
One solution for dealing with this situation is

to use an RS memory mounted as shown in
the figure opposite:
Figure 40: RS memory setup
In this case, if the switch bounces, the blade

leaves one or other of the positions (closed
or open), the state of inputs Tt S is equal to
11 which corresponds to the memory's
position.

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7.7. SYNCHRONOUS MEMORY (RST OR RSH)
7.7.1. Logic diagram
Figure 41: Logic diagram of a synchronous memory
7.7.2. Truth table
As column tn indicates Q's state just after the command edge of clock T (or H), we have
the following implication table for the synchronous RS memory:
tn-1 tn
T (or H) R S Qn
0 φ φ Qn-1
0 0 Qn-1
0 1 1
1 0 0
1 1 -
Table 24: Synchronous memory truth table
7.7.3. Advantages of synchronous inputs
Prepare the R and S commands without disturbing the memory (T = 0) and only
validate them at the desired moment (T = 1).
Protect the memory against disturbances occurring in R and in S as long as we

have T = O.

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Figure 42: Synchronous inputs
7.7.4. Drawbacks of RST memory
For T = 1: the inputs are sensitive to disturbances but because they must be
sensitive to the command signals, this situation is inevitable.
The memory stores anything when T varies at the same time as R and/or S.
The combination R S = 1 1 always poses a problem.

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7.8. D LATCH MEMORY
7.8.1. Logic diagram
Figure 43: Logic diagram of a D Latch Memory
7.8.2. Truth table
tn-1 tn
T (or H) D Qn
0 φ Qn-1
0 0
1 1
Table 25: D Latch Memory truth table

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8. FLIP-FLOPS
The memorisation of information is an essential, but not sufficient, operation in all
processing systems (measuring apparatus, computer, etc.). Besides counting (pulses) we
want to copy at the rate of a clock (levels 1 and 0), transmit in series on a wire (and at
precisely known instants) information stored in parallel permanently in a memory.
In any case, we need a periodic clock and a single item of information per period to enable
the receiver to recognise the items of information without any ambiguity. But when the
clock equals 1, RST (or RSH) and DT (or D latch) memories are sensitive to disturbances
that may cause a modification of the transmitted information.
To make up for this drawback, the solution is to open the emitting memory's input for a
time just sufficient to allow it to enter the information to be transmitted during the following
clock period and close it during the rest of the period. This brings us to three solutions,
including the circuits called flop-flops:
Reduce the time during which we have T = 1 at the minimum value and at the limit,
for the length of one edge,
Make a transmitter circuit that is not sensitive to T's level 1s but, rather, to its edges
(either rising or falling but not to both types),
Give the transmitter circuit a so-called "master-slave" structure.
8.1. FLIP-FLOP COMMAND MODES
8.1.1. Master-Slave structure
The "master-slave" structure is obtained by placing two identical memories in cascade in a

single circuit, as shown in the figure below (for example with RST memories):
Memory (1) is called "master" whereas

memory (2) is called "slave".
Figure 44: Structure of a flip-flop

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8.1.2. Operation
Let us suppose we have the following initial state: R = S = 0; T = 0 and Q = O. From that
state, let us place inputs R and S in such a way that R = 0 and S = 1.
For T = 0, nothing changes at the output from the system, indeed the "master" memory is
isolated from its outputs; consequently outputs Qm and QM cannot take another value,
whereas the inputs of the "slave" memory, although it is active (T = 0 -* T2 = 1), do not
change state.
When T = 1, the "slave" memory is isolated from its inputs and therefore Q remains equal
to 0; however as the "master" memory becomes active it stores the variations of R and S
leading to Qm = 1 and Qm = 0. This state remains stable as long as T = 1 and that inputs
R and S do not change state.
When T returns to 0 the "master"

memory is once again isolated
from its inputs and at the same
time the "slave" memory becomes
active and stores the previous
variations of outputs Qm and Qm
from the "master" memory leading
to Q =1 and Q = O. We therefore
have a transfer at the output on the
clock's falling wave edge.
Figure 45: Flip-flop operation
8.1.3. Triggering by the clock's wave edges
We have seen that the RST or DT memories are open to disturbances as long as signal T
is at 1, and during that time any variation in the inputs makes the state of the outputs
change.
"Master-slave" operation improves the situation slightly because any disturbance occurring
at the inputs when T is at 1, does not make the output change but it is stored in the
"master" memory and appears at the output as soon as T switches to 0.
Therefore, the longer the time we have T 1, the greater the risk of receiving disturbances.
So we have thought of shortening this time as much as possible and, as the shortest time
is the time of an edge, we arrive at the solution of flip-flops operating on the edges (rising
or falling) of clock T.

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The figure below shows the structure of a self-blocking flip-flop:
Figure 46: Structure of a self-blocking flip-flop
The flip-flop stores the information present on its inputs at the time of the clock's active
edge and then it blocks itself, and its output displays the stored information.
8.1.4. Combination of the master-slave structure and of operation on the edge

(so-called ‘DATA LOCK OUT’ flip-flop)
This is a delayed action system: the information is taken into account at the instant of the
clock's rising edge, but the output only delivers the information when the clock returns to
its 0 level.
The "master" memory has a self-blocking system that allows it to operate on the clock's
active edges (rising), the "slave" memory – locked when T = 1 – copies the memory's state
when T = 0.
It can be locked either when T = 1 and open when T = 0 (case of commercially available
flip-flops), or a flip-flop that operates on the falling edge which copies the "master's" state
at the time of this falling edge (not currently available commercially).

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8.2. THE DIFFERENT FLIP-FLOPS
8.2.1. RST (or RSH) flip-flops
8.2.1.1. Description and symbol
This flip-flop is only sold in "master-slave" RST form.
Figure 47: Symbol of the RST flip-flop
RAU and RAZ are inputs that force to 1 or to 0; active

on the low levels. They take priority (to the outputs) over
the inputs R, S and T.
Mode RAU RAZ T S R Qn +1 Q n +1 Remark

0 1 X X X 1 0 Forcing to 1
Asynchronous
0 0 X X X 1 1 "Prohibited"
1 1 0 X X Qn Qn Memory
1 1 0 0 Qn Qn Memory
1 1 1 0 1 0 Set to 1
Synchronous
1 1 0 1 0 1 Reset to 0
1 1 1 1 1 1 "Prohibited"
X: indifferent
Table 26: RST flip-flop
8.2.1.2. The 'Master-Slave' RST flip-flop performs the counting function
A modulo n counter is a system which, under the action of input signals (clock), can
successively occupy n different stable states.
To obtain the counting function (modulo-2 counter) you just have to wire the inputs so that
S=Q and R–Q.

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Figure 48: "Master-Slave" RST flip-flop
8.2.1.3. Advantages and Drawbacks of the "Master-Slave" RST flip-flop
Its advantages are:
All the properties of memories,
The counting function with the appropriate connections,
The output only takes into account one item of information per clock pulse.
But it does have some drawbacks:

The S = R =1 prohibited combination can occur when there are disturbances on
the input wires,
When T = 1, the flip-flop's outputs are open and can be disturbed by

disturbances that it stores in memory immediately after (and in the place of) the
correct information,
This flip-flop is not commonly used at present.
8.2.2. D flip-flop
This flip-flop is only commercialised in the "edge triggered D flip-

flop" form.
Figure 49: D flip-flop symbol

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Mode RAU RAZ T D Qn +1 Q n +1 Remark

0 1 X X 1 0 Forcing to 1
Asynchronous 1 0 X X 0 1 Forcing to 0
0 0 X X 1 1 "Prohibited"
1 1 1 1 0 Set to 1
1 1 0 0 1 Reset to 0
Synchronous
1 1 X Qn Qn Memory
1 1 X Qn Qn Memory
Table 27: D flip-flop
REMARK:
The rising edge triggered D flip-flop also makes it possible to perform the counting
function; you just have to connect input D to output Q to obtain this function.
8.2.3. JK flip-flop
The "master-slave" RST flip-flop can be used to perform the counting function, but then it
cannot perform any other function because, in that configuration, it does not have any
other available inputs.
By modifying the input circuit it is possible to have other accessible inputs, while keeping
the counting function, you then have a new type of flip-flop, called a JK flip-flop.
Figure 50: JK flip-flop symbols

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Although the JK flip-flop is derived from the "master-slave" RST flip-flop, it is not
necessarily "master-slave", in fact the JK flip-flop is commercialised not only for "master-
slave" operation but also for edge triggered (rising or falling) operation and "data look out"
operation.
The operating mode does not change in any way the effect of inputs J and K on outputs Q
and –Q, only the moment when the result appears changes.
Consequently, we can give a single implication table that is suited to the different types of
JK flip-flop.
Mode RAU RAZ T J K Qn +1 Q n +1 Remark

Asynchronous 1 0 X X X 0 1 Forcing to 0
0 0 X X X 1 1 "Prohibited"
1 1 * 0 0 Qn Qn Memory
1 1 * 1 0 1 0 Set to 1
Synchronous
1 1 * 0 1 0 1 Reset to 0
1 1 * 1 1 Qn Qn counting
For "Data Lock
Out" flip-flops
* Depending on the command mode: a pulse, rising edge or falling edge
Table 28: JK flip-flop

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8.3. FLIP-FLOP APPLICATIONS
8.3.1. Shift registers
A shift register consists of n flip-flops. It can therefore store n bits of information. These
flip-flops are interconnected in such a way that the logic state of the rank i flip-flop is
transmitted to the rank i+1 flip-flop when the clock signal is applied to the system.
The information present in the last flip-flop of such a register is always physically
accessible. This is the output from the shift register.
The information can be introduced into this register in two ways:
Series input: the information is presented bit-by-bit to the input of the first flip-flop
and is introduced there at each clock pulse. At the same time, the clock's state is
transmitted to the next flip-flop. This operating mode makes it possible, among
other things, to make the digital delay line. This type of shift register is said to have
a series input and output.
Parallel input: the n-bit information is introduced in a single go into the shift
register, which is necessarily made up of n stages. To do this we have access to
the input of each flip-flop making up the register. Generally, an inhibit gate will be
used to make the transfer and ensure the isolation required between the register
and the exterior once the transfer has been made. This register is said to have a
parallel input and series output. This type of register is used in the parallel-series
transformation. Lastly, we can design an output parallel; to achieve that, the
outputs from the register's flip-flops must simply be accessible.
In the end, a shift register consists of:
a clock input which, in shift mode, will push the binary information from one
flip-flop to the next.
a loading/shift input.
a "series data" input that introduces information bit after bit into the first flip-flop.
a "parallel data" input " made up of n accesses.
a validation input for each of these 2 input modes.
a register reset input.
possibly, a shift to the left / shift to the right command.
And lastly, the output from the register, which is the last flip-flop; access to the
outputs from intermediate flip-flops also being possible to ensure a parallel output.

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Figure 51: Organisation of a universal 4-bit shift register
8.3.2. Asynchronous counters
A modulo N counter is a system with N stable states that can go from one to another under
the influence of pulses applied to its input.
A counter is said to be synchronous or asynchronous depending on whether the switching

of the various stages it is made of are rigorously synchronous or not with the command
clock signal. In the first case all the switchings are carried out simultaneously, in the
second case the stages intervene in cascade one after the other.
8.3.2.1. Full-cycle counters
These consist of flip-flops mounted as dividers-by-two (counting function), placed in series

so that the output signal from one controls the input to the next one.
Remark:
The rank n-1 flip-flop will be connected to the rank n flip-flop in the following way:
If the flip-flops used are flip-flops that act on the rising edge, then output from the
rank n-1 flip-flop will be connected to input T (or H) of the rank n flip-flop.
In the case of flip-flops acting on falling edges or of "master-slave" flip-flops, output

Q from the rank n-1 flip-flop will be connected to input T (or H) of rank n.
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Figure 52: Example of a modulo 8 counter
8.3.2.2. Reversible (full-cycle) counter
A reversible counter is a system capable of counting up or down depending on the value of

the command signal.
It is easy to make the transformation from a counter into a down-count counter: in the case
of falling edge triggered or master-slave flip-flops, you just have to apply to the flip-flops’
clock inputs (T), instead of to outputs Q, the signals from outputs Q. In the case of rising
edge triggered flip-flops, you apply outputs Q to the clock inputs (T) instead of outputs Q.

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8.3.2.3. Incomplete-cycle counter
For n flip-flops these circuits have N states with 2n -1 <N <2n.
An incomplete-cycle counter must "skip" all the unwanted states; these may be
consecutive, for example 10, 11, ..., 15 for a decimal counter (making a decade in BCD),
or disjointed for signal generators.
We obtain the required operation by

reducing the problem to the calculation of
the combinatorial functions (decoder) meant
to act on the resets (priority) or (and) on the
setting to one (priority) of certain flip-flops
after certain counter states; the other
connections make the counter function
normally outside these circumstances
Figure 53: Incomplete-cycle counter
Example: modulo 10 counter.
There are several

possible ways of making
a reset circuit (decoder):
one consists of detecting
state 10 and resetting all
the flip-flops.
Figure 54: Counting

cycle
Although short-lived, state 10 (transient state) exists, which means precautions must be
taken when analysing the counter's states.
Equation F for the combinatorial resetting circuit will be given in the following Karnaugh
map (Be careful! The flip-flops' reset input is active on a low):
BA
DC 00 01 11 10
00 1 1 1 1
01 1 1 1 1
11 X X X X
10 1 1 X 0

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F = BD
which gives us the following logic diagram:
Figure 55: Counting cycle logic diagram
REMARK:
The lengths of the RESET and Set to One actions are quite dispersed; as soon as one flip-
flop changes state before the others, the output signal from the RESET and Set to One
decoder changes state and no longer acts on the other flip-flops which have not yet
changed state. It is it is therefore necessary to place a delay r on the output from the
decoder to maintain the RESET or Set to One signal for a sufficient length of time.
8.3.2.4. Advantages and drawbacks of asynchronous counters
Drawbacks
Limit on the operating speed:
If you look at how an asynchronous counter acts just after the command pulse
edge, you will see that each flip-flop (except the first one) must wait for the one
preceding it to have changed state so that it can, where applicable, change state
itself. Consequently, the switching times are added to each other, which limits the
counter's operating speed.
Transient states

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The propagation of the flip-flop trigger signals, such as is required in this type of
counter, causes transient states that are undesirable because they are present for a
non-negligible lapse of time.
Let us take the case of a four-bit asynchronous counter (modulo-16 counter), we

can draw the timing chart for each transition case. For example, the figure below
shows the different states through which the counter will pass to switch from
position 0111 to 1000.
Figure 56: Transient states
For this, we have assumed that each flip-flop has the same response time: tr.
In this particular case, the time required by the counter to stabilise at its final value
(1000) is 4 tr and, even more seriously, it passes through successive error states
that it keeps for time tr (of the order of 20 ns for a fast flip-flop). This represents a
prohibitive drawback when the counter is used by fast devices.
A good example is address decoding which, as it uses fast circuits, would make
stray decodings correspond with each intermediate state.
Advantages
Very simple design.
There are not many links between the flip-flops.
Speed
It could be assumed that the operating speed is only limited by the maximum
frequency that the first flip-flop can receive. But this advantage is limited by the
counter's stabilisation time if you have to use all or some of its states.
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8.3.3. Synchronous counters
In a synchronous counter (or a down-count counter), the flip-flops that must change state
do so at the same time, triggered by an active edge of a clock pulse.
Figure 57: Synchronous counter
The figure shows that:
Clock H (or T) is the same for all the flip-flops;
Combinatorial circuits provide the inputs (D and JK) of each of the flip-flops with the
levels corresponding to the states that they must take at the time of the clock
pulse's active edge.
The combinatorial circuit is designed from the implication table expressing, according to
the flip-flops' outputs A, B, ..., N, the counter's states in the order in which they occur.
The flip-flops' D or JK commands will then have to be expressed according to these

signals.
We will use examples to explain all this.
8.3.3.1. Truth table for a JC flip-flop
The implication table for flip-flop JK is shown below. Let us J K Qn

deduce another table called the excitation table, making it Qn −1
0 0
possible to determine the input commands J and K to be
applied in order to obtain the desired output when the output 0 1 0
before the clock pulse is known.
1 0 1
1 1 Q n −1
Table 29: JC flip-flop implication table

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1st case: Qn = 0, we want Qn+1
Assume that J = 0 and K = 1 command Qn+1 = 0 and J = K = 0 command Qn+1 = Qn = 0

Hence the excitation to be applied: J = 0, whatever the value (0 or 1) of K.
2nd case: Qn = 0, we want Qn+1 =1
Assume that J = 1 and K = 0 command Qn+i = 1 and J = K = 1 command Qn+1 = Q n = 1

Hence the excitation to be applied: J =1 whatever the value (0 or 1) of K.
3rd case: Qn =1, we want Qn+1 = 0
Assume that J = 0 and K = 1 command Qn+i = 0 and J = K =1 commands Qn+1 = Qn = 0.

Hence the excitation to be applied: K = 1, whatever the value (0 or 1) of J.
4th case: Qn = 1, we want Qn+1 = 1
Assume that J = 1 and K = O command Qn+1 = 0 and J = K = 1 commands Qn+1 = Qn = 1.

Hence the excitation to be applied: K = 0, whatever the value (0 or 1) of J.
Hence the truth or excitation table for a flip-flop JK:
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Table 30: Truth table for flip-flop JK
8.3.3.2. Full-cycle synchronous counters
Example: let us construct a modulo-16 synchronous counter using natural binary as code.
The method consists of looking for the command equations for each flip-flop's inputs J
and K.
To do this we complete an implication table (table below) by writing in front of each state
the value that inputs J and K must take in order to obtain the next state.

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N° D C B A JA KA JB KB JC KC JD KD
0 0 0 0 0 1 X 0 X 0 X 0 X
1 0 0 0 1 X 1 1 X 0 X 0 X
2 0 0 1 0 1 X X 0 0 X 0 X
3 0 0 1 1 X 1 X 1 1 X 0 X
4 0 1 0 0 1 X 0 X X 0 0 X
5 0 1 0 1 X 1 1 X X 0 0 X
6 0 1 1 0 1 X X 0 X 0 0 X
7 0 1 1 1 X 1 X 1 X 1 1 X
8 1 0 0 0 1 X 0 X 0 X X 0
9 1 0 0 1 X 1 1 X 0 X X 0
10 1 0 1 0 1 X X 0 0 X X 0
11 1 0 1 1 X 1 X 1 1 X X 0
12 1 1 0 0 1 X 0 X X 0 X 0
13 1 1 0 1 X 1 1 X X 0 X 0
14 1 1 1 0 1 X X 0 X 0 X 0
15 1 1 1 1 X 1 X 1 X 1 X 1
Table 31: Implication table for full-cycle synchronous counters
To determine the equations for the necessary combinatorial circuits, the Ji and Ki in the
table above are then carried over to the Karnaugh maps:

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Figure 58: Karnaugh maps for full-cycle synchronous counters
We can then draw this counter's logic diagram, however it must be noted that there are
two possible ways of wiring the four flip-flops:
Figure 59: Series carry counter
Figure 60: Parallel carry counter

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8.3.3.3. Incomplete-cycle synchronous counters
Like in the previous paragraph, we are going to take an example to explain the design
method.
Example: construction of a modulo-10 counter using BCD 8421 as code.
You just have to modify the circuits looping back to the Ji and Ki in order for the setup to
recycle on the tenth pulse. The previous table remains unchanged until the ninth pulse, but
the Ji and Ki on line no. 9 must have a different value.
No. D C B A JA KA JB KB JC KC JD KD
0 0 0 0 0 1 X 0 X 0 X 0 X
1 0 0 0 1 X 1 1 X 0 X 0 X
2 0 0 1 0 1 X X 0 0 X 0 X
3 0 0 1 1 X 1 X 1 1 X 0 X
4 0 1 0 0 1 X 0 X X 0 0 X
5 0 1 0 1 X 1 1 X X 0 0 X
6 0 1 1 0 1 X X 0 X 0 0 X
7 0 1 1 1 X 1 X 1 X 1 1 X
8 1 0 0 0 1 X 0 X 0 X X 0
9 1 0 0 1 X 1 0 X 0 X X 1
10 1 0 1 0 1 X X 0 0 X X 0
11 1 0 1 1 X 1 X 1 1 X X 0
12 1 1 0 0 1 X 0 X X 0 X 0
13 1 1 0 1 X 1 1 X X 0 X 0
14 1 1 1 0 1 X X 0 X 0 X 0
15 1 1 1 1 X 1 X 1 X 1 X 1
Table 32: Incomplete-cycle synchronous counter implication table
States 10 to 15 are now unused, but if further to a stray pulse one of these states was
reached, the system, after a few pulses, would have to resume its normal operation. This
could be, obtained, for example, if Ji and Ki then all equalled 1 or took the same values as
in the full-cycle counter, which ensures a reset when state 15 has been passed.

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By adopting this second solution, only box 9 is modified in the above Karnaugh maps.
Furthermore, by comparing line 9 with the old one, we can see that only the values of JB
and KD have changed, which gives us the following as the new equations for JB and KD:
J B = AC + AD and K D = ABC + ABC
This counter's logic diagram will therefore be as follows:
Figure 61: Logic diagram for an incomplete-cycle synchronous counter
Remark:
By systematically writing "don't cares" (X) in all the unused boxes (10 to 15), we obtain a
simpler system (this is possible because the 10 to 15 states are no longer used):
Figure 62: Karnaugh maps for a simplified incomplete-cycle synchronous counter

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Figure 63: Logic diagram for a simplified incomplete-cycle synchronous counter
But you must check that from the abnormal states (10 to 15) you return to the permitted
states.
N° D C B A JA KA JB KB JC KC JD KD
10 1 0 1 0 1 1 0 0 0 0 0 0
One pulse will only act on A and fall to:
11 1 0 1 1 1 1 0 1 1 1 0 1
The following pulse gives:
4 0 1 0 0 Which is a normal state
From 12
12 1 1 0 0 1 1 0 0 0 0 0 0
The following pulse acts on A only, that is:
13 1 1 0 1 1 1 0 1 0 0 0 1
From this state we fall to:
4 0 1 0 0 Which is a normal state
From 14 :
14 1 1 1 1 1 1 0 0 0 0 0 0
Gives:
15 1 1 1 1 1 1 0 1 1 1 1 1
0 0 0 0 0 State 0
Table 33: Verification of the abnormal states
The counter therefore never remains blocked on an abnormal state.

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9. INTEGRATED COUNTERS
The commercially available integrated counters are:
Loadable, we also use the term "programmable",
Reversible (they count up and down) or non-reversible (they count up),
Asynchronously loadable or synchronously loadable,
Put in series by the synchronous mode only or put in series by the asynchronous or
synchronous modes.
Putting into
Loading Reversible Type
series
74 190 DCB
Asynchronous
or synchronous
74 191 0, 1, …, 15
Asynchronous Yes
74 193 0, 1, …, 15
Asynchronous
74 192 DCB
74 161
0, 1, …, 15
74 163
No
74160
DCB
74162
Synchronous Synchronous
74 168 DCB
Yes
74 169 0, 1, …, 15
Table 34: Integrated counters
9.1. 74192 AND 74193 ASYNCHRONOUS LOADING COUNTERS
These circuits are reversible synchronous counters (up/down-count counter). The 74192
circuits are BCD counters (decimal) and the 74193 circuits are 4-bit binary counters.
Synchronisation is obtained by the simultaneous triggering of all the flip-flops enabling the
outputs to change logic level at the same time, in accordance with the command logic.
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This operating mode eliminates the counting transient states on the outputs, a disturbance
phenomenon inherent to asynchronous counters.
The four master-slave flip-flops are triggered by the rising edge on one of the clock inputs.
There is no up-count (down-count) counting direction command in these counters, this

direction is determined by the "COUNT UP" (or "COUNT DOWN") input received by the
clock, the other input must be at 1. These counters are fully programmable, which means
that each output can be set to any logic level by presenting the data on the programming
inputs (A, B, C, D loading inputs).
The information present in these two counters on the loading inputs (A, B, C, D) is
transferred to outputs QA, QB, QC, QD when the loading command (LOAD) is at low (0),
as this action is independent from the clock and the counter's previous state: this is
asynchronous loading. This property makes it possible to use these counters as modulo-
N dividers simply by modifying the counting cycle by means of the programming inputs.
The reset input (CLEAR) is active on a high level (1); it is independent from the LOAD
input states and from the clock's inputs to count up (COUNT UP) or down (COUNT
DOWN): this CLEAR input is asynchronous and takes priority over the LOAD input.
9.1.1. Logic symbols
The logic symbols for 74193 and 74192 counters are shown in the figure below:
Figure 64: Logic symbols for 74192 and 74193 counters

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9.1.2. Putting several counters in series
These counters are designed in such a way they can be juxtaposed without the need for
any external logic.
Figure 65: Putting counters in series
The "CARRY" and "BORROW" outputs make it possible to sequence down-counting and
up-counting functions. The "BORROW" output delivers a pulse whose length is equal to
one clock cycle, when the counter is in negative overflow.
Likewise, the "CARRY" output delivers a pulse whose length is equal to one clock cycle on
the up-counting input when the counter is in positive overflow. The circuits can easily be
juxtaposed by connecting the "BORROW" and "CARRY" outputs to the next counter's
"COUNT DOWN" and "COUNT UP" inputs (immediately higher weight).
Remark:
The "CARRY" counting output produces a pulse when the counter reaches its last
state (9 for the 74192, and 15 for the 74193),
The "BORROW" counting output produces a pulse when the count-down counter
reaches its 0 state.
Operation is obviously asynchronous.

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9.1.3. Operating timing diagram
Figure 66: Operating timing diagram for a 74192 counter

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Figure 67: Operating timing diagram for a 74193 counter

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9.2. 74190 AND 74191 ASYNCHRONOUS LOADING COUNTERS
These circuits are reversible synchronous counters (count up/count down). 74190 circuits
are BCD counters (decimal) and 74191 circuits are 4-bit binary counters.
Synchronous operation is due to the simultaneous commanding of all the flip-flops whose
output logic levels change at the same time in accordance with the command logic.
This operating mode eliminates the counting transient states on the outputs that are
inherent to asynchronous counters (clock transmitted from one flip-flop to another).
The four master-slave flip-flops are triggered by a rising edge on the clock input (CLOCK)
if the validation input ( ENABLE ) is at its low level. If the validation input ( ENABLE ) is at its
high level, counting is stopped.
The changes of logic level on the validation input ( ENABLE ) must only occur when the
clock input is at its high level.
The counting direction is determined by the state of the DOWN / UP counting direction
input.
When the input is at its low logic level, the counter counts up, and when it is at its high
logic level, the counter counts down.
If the count up/count down input changes state when the clock input is at its low logic level,
a triggering may occur that is equivalent to a stray clock pulse.
If during a loading pulse, the count up/count down input is at its high logic level with the
clock and the validation input at low logic level, the incorrect carry may be transmitted.
These counters are fully programmable, which means that the outputs can be set at any
logic level by forcing the LOAD loading input to the low logic level and applying the data to
the programming inputs (A, B, C, D).
These items of data will be copied to the outputs independently from the state of the clock
input, this loading is asynchronous. This property means it is possible to use these
counters as modulo-N dividers simply by modifying the counting cycle via the
programming inputs.

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9.2.1. Logic symbol
The logic symbols for 74190 and 74191 counters are given in the figure below:
Figure 68: logic symbols for 74190 and 74191 counters
In order to facilitate their extension, these counters have two outputs: a "clock
propagation" ( RIPPLECLOCK ) output and a "maximum/minimum counting" (Max / Min)
output.

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The latter delivers a pulse lasting about one complete clock cycle, when the counter is in
overflow in one direction or the other. The "maximum/minimum counting" output provides a
degree of anticipation that is required for high-speed operation.
The "clock propagation" ( RIPPLECLOCK ) output delivers a negative pulse with a length
equal to that of a clock low logic level under the same conditions.
9.2.2.1. Putting in asynchronous series
Putting in asynchronous series: each RIPPLECLOCK output from a counter is connected

to the next counter's clock input; this RIPPLECLOCK output is only validated when the
DOWN / UP command is at its low level (0) and the clock is at its low level (0). The DOWN
/ UP command input must therefore not vary when the clock is at its low level and must
not vary either so long as the pulse to be counted has not been propagated to the last
stage.
Figure 69: Putting in asynchronous series
9.2.2.2. Putting in synchronous series
Putting in synchronous series: the first counter is permanently validated ( ENABLE = 0) and
its ( RIPPLECLOCK ) output commands the second counter's validation input, etc.. All the
clock inputs are commanded simultaneously: the counter is therefore synchronous, but the
validation commands, as they propagate from one circuit to the next, reduce the clock's
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maximum frequency. Like with putting in asynchronous series, the DOWN / UP command
signal must not vary when the clock is in its low state.
Figure 70: Putting in synchronous series

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9.2.3. Operating timing diagrams
Figure 71: 74190 counter operating timing diagram

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Figure 72: 74191 counter operating timing diagram

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9.3. 74160, 74162, 74162 AND 74163 SYNCHRONOUS LOADING

COUNTERS
These programmable synchronous counters include carry look-ahead circuitry, which

means they can be used in very fast counting systems. 74160, 74LS 160A, 74162 and
74LS 162A circuits are decimal counters (BCD) and 74161, 74LS 161 A, 74163 and 74LS
163A circuits are 4-bit binary counters.
Synchronous operation is due to the fact that all the flip-flops are triggered simultaneously.
The outputs change logic level at the same time in accordance with the validation inputs
(ENABLE T and ENABLE P) and the internal logic.
This operating mode eliminates the counting transients that appear on the outputs from the
asynchronous counters (clock propagation).
Triggering of the four flip-flops is carried out during the clock's positive transition.
These counters are fully programmable, which means that the outputs can be set to any
logic level.
As programming is synchronous, the fact of imposing a low level on the loading input
( LOAD ) inhibits the counter and after the positive transition of the next clock the data
present on the programming inputs (A, B, C, D) are copied to the outputs, independently
from the logic levels of the validation inputs (ENABLE T and ENABLE P). This loading is
therefore synchronous.
The positive transition on the loading input ( LOAD ) of the 74160 and 74163 circuits must
take place when the clock input is at its low logic level with the validation inputs (ENABLE
T and ENABLE P) at their high logic level. This restriction does not apply to the 74 LS
160A, 74 LS 161 A, 74 LS 162A and 74 LS 163A circuits.
Resetting of the 74160, 74161, 74LS 160A and 74LS 161 A circuits is asynchronous and a
low logic level applied to the CLEAR input sets the outputs of the four flip-flops to the low
logic level independently from the clock's logic levels, from the loading input or from the
validation inputs, resetting takes priority.
Resetting of the 74162, 74163, 74LS 162A et 74LS 163A circuits is synchronous and a low
logic level on the CLEAR input sets the outputs from the four flip-flops to the low logic level
after the clock's next rising edge, independently from the logic levels of the validation
inputs.
This synchronous resetting makes it possible to modify the length of the counting cycle by
encoding the desired maximum counting value with an external NAND gate. The output
from this gate connected to the resetting input ( CLEAR ) resets the outputs (low logic level
on the four outputs).

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The rising edge on the reset input ( CLEAR ) of the 74162 and 74163 circuits must take
place when the clock's input is at low logic level with the validation and loading inputs at
the high logic level.
The carry look-ahead circuit enables synchronous counting on N bits without any
additional logic. The "RIPPLE CARRY" output and the two counting validation inputs
(ENABLE T and ENABLE P) are intended for this application.
The two counting validation inputs (ENABLE T and ENABLE P) must be at the high logic
level to enable counting and the ENABLE T input is used to validate the carry output. Once
it has been validated, this output delivers a positive pulse whose duration is more or less
the same as that of the QA output's high logic level.
This pulse, which indicates a counting overflow on the counter, can be used to validate the
various successive stages. The negative transitions on the validation inputs (ENABLE T
and ENABLE P) of the 74160 and 74163 circuits must only occur when the clock is at its
high logic level. This restriction does not apply to the 74LS 160A and 74LS 163A circuits,
which have a totally independent clock circuit.
The modifications of logic level which occur on the command inputs (ENABLE T; ENABLE
P and CLEAR) and which would modify functioning, do not have any effect during the
active edge of the clock signal.
Counter operation (validated, not validated, being loaded or being counted) is only
determined by the conditions encountered during the stable states.
9.3.1. Logic symbols
Figure 73: Logic symbols for synchronous loading counters

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Counters can be put in series in a fully synchronous way without any external components
thanks to the internal logic circuits that create the RIPPLE CARRY signal. The
authorisation to count is given by the AND: ENABLE T. ENABLE P.
For the second counter we have ENABLE P. ENABLE T =1 during state 15 (74161, 74LS
161 A, 74163 and 74LS 163 A) or 9 (74160, 74LS 160A, 74162 and 74LS 162A) of the first
counter and this makes it possible to increment the second counter by 1. The figure below
shows how these counters are connected in cascade (10 at the most because the fan-out
from the RIPPLE CARRY terminal = 1): a counter can only be incremented when all the
counters preceding it are at 15 (or 9).
Figure 74: Putting counters in series
Remark:
A RIPPLE CARRY output must not be used to command an asynchronous logic circuit
because this output can deliver stray pulses due to the differences between the flip-flop A,
B, C, D propagation times.

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9.3.3. Modulo-N frequency divider
We load the counter with the value 16 - N each time the RIPPLE CARRY output passes to
1 (counter in state 15 =1111) figure 10.8. This setup can be extended to several circuits.
Figure 75: Frequency divider

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9.3.4. 0 to N counter (N+1 states)
We decode the output information so that state N commands the synchronous resetting
(CLEAR) of the counter, when state N is detected; resetting takes place on the next clock
pulse; so the counter's state is N+1.
Figure 76: 0 to N counter

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9.3.5. Counters going from N1 to N2
Once the counter arrives in state N2, it is decoded and commands the loading of state N1
at the time of the next clock pulse. The figure below shows a counter that counts from 7 to
12. This setup can be extended to n stages.
Figure 77: Counters going from N1 to N2

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9.3.6. Operating timing diagrams
Figure 78: Operating timing diagrams for 74LS160A and 74LS162A counters

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Figure 79: Operating timing diagrams for 74LS161A and 74LS163A counters

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10. MEMORIES
10.1. GENERAL
A memory is a device capable of storing and then restoring an item of information.
Figure 80: Memories
The address bus
Access to an item of information is gained via the address bus. The address bus
is always one way.
The data bus
The information is delivered on the data bus. The data bus can be two way if you
can read and write in memory or one way if you can only read it.
The control bus
The control bus contains the various signals making it possible to manage
memory operations such as reading and writing.
10.1.1. Memory capacity
The capacity of a memory defines the amount of information it can store, that is to say the
number of cells it contains. The capacity is expressed in bits or in bytes.

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1 byte = 8 bits
210 bytes = 1024 bytes = 1 kb (kilobyte)
220 bytes = 1024 kb = 1 Mb (Megabyte)
230 bytes = 1024 Mb = 1 Gb (Gigabyte)
1 kbit = 1024 bits 1 kb = 8 kbits

1 Mbit = 1024 kbits 1 Mb = 8 Mbits
1 Gbit = 1024 Mbits 1 Gb = 8 Gbits
Conclusion:
To pass from the byte to the kilobyte, we divide by 1024.
To pass from the byte to the bit, we multiply by 8.
10.1.2. Organisation
A memory is made up of data (or words) made up of 8, 16, 32 or 64 bits, or even more.
For example, we say that a memory is organised in 256 words of 16 bits.
If a memory has n address lines, it contains 2n items of data.
10.1.3. Access mode
There are two different types of access to the information contained in a memory:
Random or direct access: each word can be accessed directly and individually by
means of its address,
Sequential access: the information is identified by its position in a queue of

elements, it is the order of recording that is kept (e.g. magnetic tape).

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10.1.4. Speed
The access time (Tacc) is the time that elapses between the instant when the address is
set and the moment when the data item is available.
Figure 81: Memory speed

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10.2. READ ONLY MEMORY (ROM)
10.2.1. ROM architecture
The internal architecture, that is to say the structure of a ROM memory package is highly
complex, but it is not essential to know all the details. However, it may be worthwhile
examining a simplified diagram of the internal architecture as shown in the figure below.
Figure 82: Architecture of a 16 x 8 ROM
It has three component parts:
A register matrix (R): the register matrix is the set of elements that really memorise
the data in the ROM. Each register is made up of a certain number of memory cells
equal to the length of the word.

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In the present case, each register contains an 8-bit word. The registers are
arranged in a square matrix as is common in semi-conductor memory chips. It is
possible to indicate the position of each register by giving its row and its column.
The 8 data outputs from each register are connected to an internal bus which "runs"
through the whole circuit.
Each register has two validation inputs E, which must both be high in order for the
data item in the addressed register to be placed on the bus.
An address decoder: address A3 A2 A1 AO applied to the inputs determines the

register in the matrix that will be validated and whose 8-bit word will be placed on
the bus. The bits at address A&10 arrive on a 1-out-of-4 decoder (row selection)
that activates a row selection line and the bits at address A3 A2 arrive at a second
1-out-of-4 decoder (column selection) that activates a selection line. As there will be
only one register whose column and row will be chosen by the address inputs, that
is the one that will be validated.
An output buffer register: the register that is validated by the address inputs places
its data item on the data bus. This item of data feeds output buffers that will deliver
it to the external data outputs if CS is high. If CS is low, the output buffers are in
their high-impedance state, and the data outputs are "floating".
Figure 83: ROM circuit
Seen from the outside, a ROM will be considered as a circuit comprising:
n address inputs making it possible to address 2n internal registers
p data outputs
a CS (Chip Select) validation input

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A ROM will be characterised by:
its size or capacity: it is always a power of 2 (11c, 2k, 4k, 8k, 16k bytes), 1 k bytes
=1024 bytes (0 to 1023), and determines the number of registers contained in the
memory and, consequently, the width of the address bus (A_bus).
1 k → A_Bus of width 10 (210)

2 k → A_Bus of width 11(2.210 = 21.210)
4 k → A_Bus of width 12 (4.210 = 22 210)
8 k → A_Bus of width 13 (8.210 = 23.210)
the data format: it is always a power of 2 and determines the width of the data bus
(D Bus)
the access time in nanoseconds (time it takes to read or write an item of data
depending on the type of memory).
10.2.2. Different types of ROM
10.2.2.1. Mask Read Only Memories (MROM)
In this type of ROM, the data are written in the memory locations (programming) by the
manufacturer according to the customer's specifications. We use the negative of a
photographic contact print, called mask, to establish the electrical interconnections in the
chip.
A special mask is required for each different set of information to be stored in memory.
Because these masks are costly to make, this type of memory is only economically viable
for very large production runs.
10.2.2.2. Programmable Read Only Memories
These memories only differ from the previous ones in that they can be programmed by the
user. You must note that like for MROMs, they cannot be erased or programmed.
10.2.2.3. Erasable and Programmable Read Only Memories (EPROM)
EPROMs can be programmed by the user, but it is also possible to erase and reprogram
them as often as desired.
To erase an EPROM you just have to expose it to Ultra Violet light, which penetrates
through a window on the chip for about 30 minutes.

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10.2.2.4. Electrically Erasable and Programmable Read Only Memories

(EEPROM)
The difference with respect to an EPROM lies in the way the data are cleared by applying
a signal, which has the advantage, on the one hand, of being faster and on the other hand
of making it possible to select the information to be erased. This can be done either on a
programming console or directly by the application in which the memory is located.
10.2.3. Recap of the different types of Read Only Memory
ROM – Read Only Memory
It is programmed by the manufacturer at the time of manufacture. It is used in large

series in industry.
PROM – Programmable ROM
This is a ROM that the user can program once only.
EPROM – Erasable PROM (PROM erasable by UV light)
These have a window above their package that makes it possible to expose the
chip to UV light for 10 to 20 min. It can be reprogrammed several times.
The operating principle means that the data is slightly less secure than in a ROM or a
PROM. If the window is not blocked off after programming or if the ambient
temperature is high, there is a risk of one or more bits being spontaneously erased.
EEPROM – Electrically EPROM
The data is erased electrically. This can therefore be done without removing the
package from its support. They enable the selective erasing of data.

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10.3. RANDOM ACCESS MEMORIES (RAM)
A Random Access Memory (RAM) is a memory in which you can write or read data, and
that is its difference with respect to a Read Only Memory.
10.3.1. RAM architecture
A RAM can be considered as an assembly of registers storing an item of data and which
has an exclusive address. Typically RAMs have a capacity of 1k, 4k, 8k, 16k or 64 kbytes
and word lengths of 1, 4 or 8 bits.
The figure below shows the simplified architecture of a RAM. With a view to having as few
pins as possible on an integrated circuit package, the manufacturers often combine the
data input and output functions on the input/output (I/O) pins. The input L / E
commands the function of the I/O pins.
Figure 84: RAM architecture

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Seen from the outside, a RAM will be considered as a circuit comprising:
n address inputs making it possible to address 2n internal registers
p data inputs/p data outputs
a read/write input
a CS (Chip Select) validation input
Figure 85: RAM circuit
A RAM will be characterised by:
its size or capacity
the data format
the access time
10.3.2. Different types of RAM
10.3.2.1. Static RAMs
Static Random Access Memories are memories that keep the data as long as the chip is
powered. The cells in these memories are essentially flip-flops that remain in a given state
(storage of one bit) indefinitely as long as the circuit remains powered.

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10.3.2.2. Dynamic RAMs
The major difference between static and dynamic RAMs lies in the fact that dynamic
memory cells only keep their data for a limited time, typically 2ms, after which they must be
refreshed at regular time intervals to ensure the memory keeps the data.
The need to refresh the data is a significant drawback for dynamic memories.
However, they do have the advantage of dissipating very little power and of being very
economical, which is a direct consequence of the cell's simplicity.
10.3.3. Creation of address selection circuits
In a micro-computerised system, all the memories are mounted in parallel on the various
buses. So, when an address is sent to the address bus (A_bus) all the interfaces and all
the memories will receive that address.
Only one chip is concerned, so it is necessary to create a chip selection circuit which,
according to the address emitted, only validates one memory at a time.
Figure 86: Address selection circuit
Each circuit (memory or interface) has one or more chip selection inputs (CS: Chip Select),
and very often these inputs are active on a low (0 logic) but this is not always the case.
In order to create the command signals (CS), you have to elaborate a combinatorial circuit,
called address decoder. To simplify the creation of this circuit we use decoders/

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demultiplexers (1-out-of-n decoder). The interest being that decoders/demultiplexers are

commercialised in the form of ready-to-use integrated circuits.
Example : 3 to 8 decoder / demultiplexer (74 LS 138)
Figure 87: Decoder / demultiplexer inputs and outputs
Figure 88: Decoder / demultiplexer symbol
The problem is therefore to determine which wires of the address bus must be connected
to the decoder/demultiplexer's various inputs, as well as the outputs from the
decoder/demultiplexer that will have to be used to select the required chip.
We are going to take two examples to illustrate the method for creating the CSs.

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Example 1:
Let us make the circuit for selecting two memories: one ROM 4K x 8 base addresses
$1000 and one RAM 8K x 8 base addresses $2000.
To create the CSs, on each component we must look for all of the bits in the address bus
that remain unchanged whatever the memory cell targeted in the memory concerned.
Base High
Memory A15 A14 A13 A12
address address
ROM $1000 $1FFF 0 0 0 1
RAM $2000 $3FFF 0 0 1 X
From this table we can determine the type of decoder/demultiplexer that must be used. In
our case we need a 3-to-8 (or 1-out-of-9) decoder/demultiplexer. Once the
decoder/demultiplexer has been chosen, you have to determine the selection circuit's
logic diagram.

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Example 2 :
Create the selection circuit for four memories:
M1: 4K x 8 at $1000
M2: 4K x 8 at $2000
M3: 16K x 8 at $8000
M4: 16K x 8 at $0000
Table of invariable bits on the address bus for each memory:
Base High
Memory A15 A14 A13 A12
address address
M1 $1000 $1FFF 0 0 0 1
M2 $2000 $2FFF 0 0 1 0
M3 $8000 $BFFF 1 0 X X
M4 $C000 $FFFF 1 1 X X
There are no invariable bits for selecting the memories, so we must use a 4-to-16 (or 1-
out-of 16) decoder/demultiplexer.

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11. TABLE OF FIGURES

Figure 1: Symbol for a two-input OR gate..........................................................................37
Figure 2: Symbol for a two-input AND gate........................................................................38
Figure 3: Symbol for a NOT gate .......................................................................................39
Figure 4: Symbol for a NOR gate.......................................................................................40
Figure 5: Symbol for a NAND gate ....................................................................................41
Figure 6: Symbol for an exclusive OR gate........................................................................43
Figure 7 : Symbol for an Exclusive XNOR gate .................................................................44
Figure 8: Example of a circuit made with an AND gate and an OR gate ...........................47
Figure 9: Example of a logic circuit where the expression of the output is in brackets ......47
Figure 10: Example with an inverter on input A to the OR gate .........................................48
Figure 11: Example with an inverter on the output from the OR gate ................................48
Figure 12: Example of the construction of a logic circuit deduced from a Boolean
expression ..................................................................................................................49
Figure 13: Example of the simplification of logic circuits ....................................................54
Figure 14: Example of a truth table with its associated Karnaugh map .............................57
Figure 15: Example of groups of twos in the Karnaugh map .............................................59
Figure 16: Example of groups of four.................................................................................60
Figure 17: Example of a group of eight ..............................................................................61
Figure 18: Example of a Karnaugh application with different states ..................................62
Figure 19: The multiplexer, its truth table, logic diagram and symbol ................................64
Figure 20: The diagram for circuit ALS157 containing four 2 to 1 multiplexers, IEC symbol
...................................................................................................................................65
Figure 21: Diagrams of some common multiplexers..........................................................66
Figure 22: 1 to 2 decoder with enable input .......................................................................67
Figure 23: Example of a standard circuit with two 2-to-4 decoders....................................67
Figure 24: 2-to-4 decoder with enable ...............................................................................68
Figure 25: Decoder with 3 selection bits ............................................................................68
Figure 26: The comparator ................................................................................................69
Figure 27: Series breakdown of the comparison................................................................70
Figure 28: Parallel breakdown of the comparison..............................................................70
Figure 29: Stable states graph...........................................................................................73
Figure 30: Primitive matrix .................................................................................................74
Figure 31: Contracted matrix .............................................................................................75
Figure 32: Secondary variable equation and output equation............................................75
Figure 33: Logic diagram of a priority resetting memory ....................................................76
Figure 34: Concentrated matrix .........................................................................................77
Figure 35: Secondary variable equation and output Q equation ........................................77
Figure 36: Logic diagram of a priority setting memory .......................................................77
Figure 37: Logic diagram for an R S memory ....................................................................78
Figure 38: Example of RS memory ....................................................................................79
Figure 39: Bounces............................................................................................................79
Figure 40: RS memory setup .............................................................................................79
Figure 41: Logic diagram of a synchronous memory .........................................................80
Figure 42: Synchronous inputs ..........................................................................................81
Figure 43: Logic diagram of a D Latch Memory .................................................................82
Instrumentation
Automation Logic
Figure 44: Structure of a flip-flop........................................................................................83

Figure 45: Flip-flop operation .............................................................................................84
Figure 46: Structure of a self-blocking flip-flop...................................................................85
Figure 47: Symbol of the RST flip-flop ...............................................................................86
Figure 48: "Master-Slave" RST flip-flop .............................................................................87
Figure 49: D flip-flop symbol ..............................................................................................87
Figure 50: JK flip-flop symbols...........................................................................................88
Figure 51: Organisation of a universal 4-bit shift register...................................................91
Figure 52: Example of a modulo 8 counter ........................................................................92
Figure 53: Incomplete-cycle counter ..................................................................................93
Figure 54: Counting cycle ..................................................................................................93
Figure 55: Counting cycle logic diagram ............................................................................94
Figure 56: Transient states ................................................................................................95
Figure 57: Synchronous counter........................................................................................96
Figure 58: Karnaugh maps for full-cycle synchronous counters .......................................99
Figure 59: Series carry counter..........................................................................................99
Figure 60: Parallel carry counter........................................................................................99
Figure 61: Logic diagram for an incomplete-cycle synchronous counter .........................101
Figure 62: Karnaugh maps for a simplified incomplete-cycle synchronous counter.........101
Figure 63: Logic diagram for a simplified incomplete-cycle synchronous counter ...........102
Figure 64: Logic symbols for 74192 and 74193 counters ................................................104
Figure 65: Putting counters in series ...............................................................................105
Figure 66: Operating timing diagram for a 74192 counter ...............................................106
Figure 67: Operating timing diagram for a 74193 counter ...............................................107
Figure 68: logic symbols for 74190 and 74191 counters .................................................109
Figure 69: Putting in asynchronous series .......................................................................110
Figure 70: Putting in synchronous series .........................................................................111
Figure 71: 74190 counter operating timing diagram ........................................................112
Figure 72: 74191 counter operating timing diagram ........................................................113
Figure 73: Logic symbols for synchronous loading counters ...........................................115
Figure 74: Putting counters in series ...............................................................................116
Figure 75: Frequency divider ...........................................................................................117
Figure 76: 0 to N counter ................................................................................................118
Figure 77: Counters going from N1 to N2 ........................................................................119
Figure 78: Operating timing diagrams for 74LS160A and 74LS162A counters................120
Figure 79: Operating timing diagrams for 74LS161A and 74LS163A counters................121
Figure 80: Memories ........................................................................................................122
Figure 81: Memory speed ................................................................................................124
Figure 82: Architecture of a 16 x 8 ROM..........................................................................125
Figure 83: ROM circuit .....................................................................................................126
Figure 84: RAM architecture ............................................................................................129
Figure 85: RAM circuit .....................................................................................................130
Figure 86: Address selection circuit .................................................................................131
Figure 87: Decoder / demultiplexer inputs and outputs....................................................132
Figure 88: Decoder / demultiplexer symbol......................................................................132

Instrumentation
Automation Logic
12. SOMMAIRE DES TABLES

Table 1 : The octal symbols expressed in binary ...............................................................13
Table 2 : Relationship between hexadecimal, decimal and binary.....................................14
Table 3 : Gray code table...................................................................................................20
Table 4 : Table summarising the different codes ...............................................................22
Table 5 : Partial list of ASCII code .....................................................................................24
Table 6: ASCII code key ....................................................................................................25
Table 7 : The different names of logic states .....................................................................32
Table 8 : Positive logic (1)..................................................................................................33
Table 9 : Negative logic (2) ................................................................................................33
Table 10 : Functions with one variable ..............................................................................34
Table 11 : Functions with two variables .............................................................................34
Table 12 : Two-input truth table .........................................................................................35
Table 13 : Three-input truth table.......................................................................................35
Table 14 : Four-input truth table.........................................................................................36
Table 15 : OR operator truth table .....................................................................................37
Table 16 : AND operator truth table ...................................................................................38
Table 17 : NOT operator truth table ...................................................................................39
Table 18 : NOR operator truth table...................................................................................40
Table 19: NAND gate truth table........................................................................................41
Table 20 : Exclusive OR operator truth table .....................................................................43
Table 21 : Exclusive NOR operator truth table...................................................................44
Table 22 : Table summarising the logic gate symbols .......................................................46
Table 23: A memory's truth table .......................................................................................78
Table 24: Synchronous memory truth table .......................................................................80
Table 25: D Latch Memory truth table................................................................................82
Table 26: RST flip-flop .......................................................................................................86
Table 27: D flip-flop............................................................................................................88
Table 28: JK flip-flop ..........................................................................................................89
Table 29: JC flip-flop implication table ...............................................................................96
Table 30: Truth table for flip-flop JK...................................................................................97
Table 31: Implication table for full-cycle synchronous counters .........................................98
Table 32: Incomplete-cycle synchronous counter implication table .................................100
Table 33: Verification of the abnormal states...................................................................102
Table 34: Integrated counters ..........................................................................................103

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5. THE BASIC LOGIC OPERATIONS ...............................................................................37

Training Manual EXP-MN-SI080-EN

7.4.2. Secondary variable equation and output equation ..........................................75

Training Manual EXP-MN-SI080-EN

9.2.2.1. Putting in asynchronous series ................................................................110

Training Manual EXP-MN-SI080-EN

Know the binary, octal, decimal and hexadecimal numbering systems,

Know how to convert the various numbering systems,

Have an understanding of combinational logic, which is essential for programming

Know the basics of sequential logic.

Training Manual EXP-MN-SI080-EN

2. THE NUMBERING SYSTEMS AND CODES

Training Manual EXP-MN-SI080-EN

2.1. REPRESENTATION OF NUMBERS

The number of symbols used characterises the number of the base.

In base 10, we have the 10 symbols (0,1,…,9)

In base 2, we have the 2 symbols (0,1)

In base 3, we have the 3 symbols (0, 1, 2)

A number in a positive base ‘b’ is written:

Nb = an . an-1 … a1 . a0 , a-1 … a-m

NB = an . bn + an-1 . bn-1 + a1 . b1 + a0 . b0 + a-1 . b-1 … a-m . b-m

Training Manual EXP-MN-SI080-EN

2.2. BINARY-TO-DECIMAL CONVERSION

Let's look at another example with a larger number of conversions:

2.3. DECIMAL-TO-BINARY CONVERSION

2.3.1. Conversion of the integer part

The integer part of a number can be expressed as follows:

Training Manual EXP-MN-SI080-EN

NB = an . bn + an-1 . bn-1 + … +a1 . b1 + a0 . b0

NB / b = (an . bn-1 + an-1 . bn-2 + … + a1 . b0) … et … (a0)

We must continue dividing until we obtain a null quotient.

2.3.2. Conversion of the fractional part

The fractional part of a number can be expressed as follows:

NB = a-1 . b-1 + a-2 . b-2 + … + a-m-1 . b-m-1 + a-m . b-m

NB . b = a-1…(a-2 . b-1 + … +a-m-1 . b-m-2 + a-m . b-m-1)

We therefore proceed by successive multiplications by b.

0.375 x 2 = 0.75 Integer part = 0 Remainder = 0.75 MSB

N10 = 0.372 corresponds to N2 = 0.011

2.4. OCTAL NUMBERING SYSTEM

Here is the weight of each of the positions in an octal number:

2.4.1. Octal-to-Decimal Conversion

Training Manual EXP-MN-SI080-EN

2.4.2. Decimal-to-Octal Conversion

However, the remainder is calculated by multiplying the decimal fraction by 8. For

By multiplying the decimal part by 8, you will get a remainder of 0.25 x 8 = 2.

Likewise, 33 / 8 gives 4.125, hence a remainder of 0.125 x 8 = 1.

2.4.3. Octal-to-Binary Conversion

Training Manual EXP-MN-SI080-EN

Table 1 : The octal symbols expressed in binary

2.4.4. Binary-to-Octal Conversion

To illustrate this, let's convert 10001110102 into octal:

100 111 010

Example: The binary number 11010110:

011 010 110

2.5. HEXADECIMAL NUMBERING SYSTEM

Table 2 : Relationship between hexadecimal, decimal and binary

Hexadecimal representation is mainly used to represent a binary number in a more

Training Manual EXP-MN-SI080-EN

2.5.1. Hexadecimal-to-Decimal Conversion

35616 = 3.162 + 5.161 + 6.160

2AF16 = 2.162 + 10.161 + 15.160