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Assessment Cover Sheet

Faculty of Engineering

Module Details
Module Code EC2092 Module Title Foundation of Digital Design
Program: SLIIT Course:Introduction to Controls
B.Sc. Engineering & Robotics
(Hons)
Stream: Electrical & Electronic

Assessment details
Title Assignment Group assignment No
If yes, Group No.
Lecturer/ Instructor Date of Performance 16/05/2021
Due date 16/05/2021 Date submitted 16/05/2021

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ID Number Name (As per the institute records)

EN17409056 H. B. C. Jayasinghe

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(seal, signature, date) for improvement)

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Marks: [ All marks are subject to external moderation and approval of board of
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GT/February 2017 V3.0


Introduction
This shopping complex plans to build cashier counters in separate rooms on the ground floor to make it
easy for their customers to do the billing without any delay. There are 5 cashier counters in 5 different
rooms, where each queue for the counter can have maximum of four customers. The queue line consist 4
sensors placed one after the other with a considerable distance to indicate whether there is a customer or
not.

All five display boards are clearly visible when a customer arrives to the ground floor. Thus, he/she can join
to the queue which consist the least number of people. If a queue does not have any customer, it displays 0.
For example, if a queue consists only two customers, at the entrance display board it displays number 2. Out
of the four sensor spots these two customers can be at any two spots. Considering this requirement, the
digital system is designed to show the correct number of customers at the entrance display board if
customers stand on any sensor spot.

The number of customers in the queue is displayed on the entrance display board using two decimal digits,
as it is required to expand this project where the system can take maximum of 15 sensor inputs and show
the number on the display board.
Design Methodology and Results

Task 01

• Maximum of 15 sensor inputs are represented by 15 inputs to the encoder (At first 4 inputs are
used.)
• When the queue does not have any customer logic 1 & otherwise logic 0.
• The binary encoder’s 4 outputs are connected to a combinational circuit.
• Then, the combinational circuit returns its outputs to two 4 to 7 segment Decoders.
• These segment Decoders send their outputs to two 7 segments to the two decimal digits.

Figure 1: Functional block diagram


Task 02

1 x x x x x x x x x x x x x x 1 0 0 0 1

2 x x x x x x x x x x x x x 1 x 0 0 1 0

3 x x x x x x x x x x x x 1 x x 0 0 1 1

4 x x x x x x x x x x x 1 x x x 0 1 0 0

5 x x x x x x x x x x 1 x x x x 0 1 0 1

6 x x x x x x x x x 1 x x x x x 0 1 1 0

7 x x x x x x x x 1 x x x x x x 0 1 1 1

8 x x x x x x x 1 x x x x x x x 1 0 0 0

9 x x x x x x 1 x x x x x x x x 1 0 0 1

10 x x x x x 1 x x x x x x x x x 1 0 1 0

11 x x x x 1 x x x x x x x x x x 1 0 1 1

12 x x x 1 x x x x x x x x x x x 1 1 0 0

13 x x 1 x x x x x x x x x x x x 1 1 0 1

14 x 1 x x x x x x x x x x x x x 1 1 1 0

15 1 x x x x x x x x x x x x x x 1 1 1 1

Table 1: Encoder Truth Table


Decimal

0 0 0 1 0 0 0 1 0 1
0 0 1 0 0 0 1 0 0 2
0 0 1 1 0 0 1 1 0 3
0 1 0 0 0 1 0 0 0 4
0 1 0 1 0 1 0 1 0 5
0 1 1 0 0 1 1 0 0 6
0 1 1 1 0 1 1 1 0 7
1 0 0 0 1 0 0 0 0 8
1 0 0 1 1 0 0 1 0 9
1 0 1 0 0 0 0 0 1 10
1 0 1 1 0 0 0 1 1 11
1 1 0 0 0 0 1 0 1 12
1 1 0 1 0 0 1 1 1 13
1 1 1 0 0 1 0 0 1 14
1 1 1 1 0 1 0 1 1 15
Table 2: Combinational Circuit Truth Table
Decimal a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 1 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
Table 3: Decoder 1 - 1's Truth Table
Decimal a b c d e f g
0 0 1 1 1 1 1 1 0
1 1 0 1 1 0 0 0 0
Table 4: Decoder 2 - 10's Truth Table

Circuit was built using NOT, AND, OR gates & 2 seven segments.
Discussion
Full circuit for one display board is shown in the above figure. Similar type five circuits are needed as the
project has 5 display boards.

But as an alternative method, this circuit can be implemented as the below figure. Then, former encoder is
replaced by two 8*3 encoders & two 4-bit seven segment decoders feed to receive the displays.

When comparing both designs ,the circuit given below is most suitable as it uses NAND gates. NAND gates
are the primary gates of other logic gates as well as they are low cost ICs which will resulted to decrease the
overheads of the project

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