115

114 S.Q.8, in Nicchancal Enginecering (3Sce S.Q.8, in Mcchanical Engineering (Semester)

s.QB.in MechanicalEnginoering3"Semostcr) S.Q.B. in Mechanical Engincering (3 Semesicr)
Complement ot tuncon tA + B+U15
4. (@) Explain the working of RC phase shift oscillator using proper circuit
AB+C
X
i) A++B+C dhagram.
C Ww AC lnpu
) The logic gate that will have thigh' or T' at its inputs is HIGH is a/an (6) Explain the operation of IC S55 timer an astable multivibrator using
OR gae i) NOTEgate
NAND gate
proper cuagram 7
DA
gae
An oscilator employ's feedback
5. (a) Explain square law diode modulation method for AM generation. 7
nalr oyuie

) Explain the diference between narrowband FM and wideband FM.

3either positive nor negative (iv) negatrve
data insuniCne 6. (0) What are the factors that affect the input offset voltage. input bias and
) The AM spectrum consists of C oupur
nput oniset Current? DC output
V
camer Tequen (ü) upper sideband irequency
(6) What are the factors that affect the input ofset voltage, input bias and B n d g e Rechfier
1ower staeband tregueney ) all of the above
input offset CuTent? Fig. (B) Bridge rectifier during negative half cycle
( a ) With a neat skech, explain the working of 8
e of full wae rectifier

)
oentre-ap ful-wave rectiier,
full-wae bridge rectifier.
7. (a) Simplify the following expression using K-map and implement the result
Bridge retiferdefnifionA i t coniguration to ef+iciently From the above two figures (A and B), we can observe that the direction of
AIso, ciseuss the importance ot peak inverse voltage in rectiñer service.
uSing univesal gates: w ne Oarent (AC) into Direct Cuem (DC. curent rlow acrogs load resistorK;15 Same during the positive halt cyele and
Worcing o f Bridge Rectifier: When input AC signal 15 apphod across n e n e g a t i v e half cycle. Therefore, the polanty of the output DC signal is same ror boln
F(A, B, C, D) = ABC + AB +ABD + ABC
opian ne esistance ot cysal diode. Draw its equivalent circuit bridge recañier, durng the posiave malt cycie iodes D andD ae row ose posive and negaive halt cycles. Lhe output Dc s1gnal polanty mas
6) Design a 32:1 MUX using two16:1MUX 6
slicon and forward resistanre of SSuime the diodes to be of curent while the
8. (a) Explain the working of D& T flip-flops with the help of state table, diodes D, and Da: e dieeion of diodes is reversed then we get a complete negative DC
voltage.
blocks clectric eurent Om while diodesD, and R, are Thus, a bridge rectifier allows electric current dung Dou Po
excitation table and block diagram.
and D
b) Differentiate between synchronous and asynchronous counters. blds clecaric curent negave nair cycies orne input AC S1gnal.
The output wavefoms or the bidge rectiier is shown in the below ffgure.
AAAA 9. (a) Over what range; of input voltage will the Zener Circuit shown n tne
Dring dhe posinive haf cycle, the teminal A becomes positive w e ne
Tminal B becones negatve. I n s causes the diodesD, andu3 1orward based and

figure below, maintain 30 V across 2000 2 load, assuming, that series

K au t casES e dioesD andD, reverse biased.

AAA
resistant R = 200S2 and Zener current rating is = 2mA.
2 The curret flow direction during the positive halif cycle is shown in the figure AC input
T24 T A(Le. A o D to C to B).
R 200
w Cuent flow direchon
3. (a) Draw the D.D2 CuTent
input and outpt characteristics of CB connecãon. What do yo
understand rom tnese characiensucS:
Posile

(b) in a common base connection,

a=0.95. he
resistance which is onnected in the collector isvoltage
2V drop across 2
w7:
D
DgD4current
(b) Explain the various characteristics of regulated power
supply. 6 Total alp curent

L EE VCH
2 2V
there
1. (a) (i)
ANSWERSs
Explanation: Since no free charge carriens
is a poental barner, ne regions on ener sides ofcantherest
0mpieeiy epietcd o any ore ree cariers in comparison to
naterials further away from the junction. This area
called uhe Depletion Layer
a position
junction now become
in

around the PN Junction

Anctie
where

isis now
now
DC output

Pig (A) Bridge recifier during positive half cycle

b) Static or DC Forward Resistance: The opposition offered by a diode to
the direct current flowing forward bias conditluon is known as ils DC torwara

resistance or Stauc Kesistance. it8 measureu Dy taking

across the diode to the DC current flowing through it.
the ratio or DC voltuge

110

DiUBlon ii) Explanation: The function of an OR gate is to find the maximum

between the inputs which are binary in nature. Itis one or the basic galcs usco
1.0ka (0-200mA
(0-200 mA
B
(0-200 mA)

" boolean algebra ana cicctronic circuits lke transistor-iransistor logic, and

egion metal-oxIde semiconductors make use

of t.
complementary
1) i) Explanation: Positive feedback increases gain of the amplifier also
(0-20V (o-20V
reacedistortion, noise and instability. Because of Uese
tecdback is seldom employed in amplifiers. But the positive feedback is ed
usedin
in
EAC volar
) (iv) Explanation: In radio communications, a sideband is a band of
requencies higher than or lower than the carrler frequency, that are the result of tis clear irom the graph that for the operating point P, the forward voltage is
electrons
free the modulation process. A and the corTespondng torward cuTent is OB. Therefonre, the static torward
Positve Donor ion
Sistance of the diode is given as nput characteristics
Negatve Acoeptor ion
2.(a) 0) Center tapped full wave rectifer
PORonial dlrierenceL rull wave rectiier is a type of rectifier which uses a center
A center tappedand
RFOB
HOls
d S e urcuon two diodes to convert the complete AC signal into DC
apped ranstormer g (Const)
signal.
The center tapped full wave rectifier is made up of an AC source, a center Dynamic orAC Forward Resistance: The opposition ofered by a diode to AVE

. ) Eplnaio: Whenhe junconisrvese biasedtha5wbenthePLapped tramsormer, wodiodes,and aload resistO tesisance tis measredbyaratio ofchaneein voltapeacross thediode to the --C Vcs= OV
positive terminal of the batery, the electrons in the n side will be attracted sulting change in current through it. From the figure A above it is clear that for an
towards the pasitive terminal, and the holes in the p side will be aracted towards perating point P the AC forward resistance is determined by varying the forward
Centre tap oltage (CE) on both the sides of the operating point equally and measuring the
Vcs const
he negate. o
iEplanion: i must be noticed that the eiiciency is maximum when oTesponding torward curent (D).
the forward resistance of the diode is less than the load resistance across which the
butput is obained. We cam also say the maximum efñiciency of the full wave
inout ww. As shown in the circuit diagram, the curent flowing through D, is:
AVEB4
ecttier is 812%. DC output Since D, is forward biased and D, remain in reverse biased so

d ) v) Exlamation: One of the most common uses for transistors in an O u p u t characteristics

I= 2 =10 mA.
electronic cireut1s as simple swtches. In short, a transistorconducds current 2
2000
when po haeevolage
woteoe ics preoen, the switch 15 ott. U
When base volfage I5 preser
Ppeo conoary 3. (a) Bipolar Junction Transistor (BJT) is a three terminal (emitter, base,
winding transformer windin
he switch is on ollector) semiconductor device. Tbere are two types of BJTS, namely NPN and
A transistor svithin an clecronic circuit works like a combination of a diode The AC source is coanected to the primary winding of the center tapped NP It eonsists of two PN junctions, namely emiter junction and colletor Alcg const)..---- |ae(cE const)
nd a vanabie essay, also caled a potentiometer or poL When bias voltagetransformer. A center tap (additional wire) connected at the exact middle of the the unction. -5 mA
iecreases, sesIstancc ncEANES. secondary winding divides the input voltage into two parts. The basic circuit diagram for studying input characteristics is shown in the
VEE V)
eEplanation: CuTe gainß is defined as the ratio of change in collector The upper part of the secondary winding is connected to the diode D, and the ircuit diagram. The input is applied between emitier and base, the output is taken
uTent to change in base cume for a constant collector voltage in a commonlower part of the secondary winding 15 connected to the diode Da 5oth diode D e t w e e n collector and base. Here base of the transistor is common to boh input AVcB g const)
mitter circuil B=or we can rewric it asß= and diode D are connected to a comnon load
Wt the help ot a center tap dnd ouput
output and hence
and h ene Lthe name is Common
e namei5 Common Base
Base Conmsguration.
Connguration.
is considered as the ground point or the zero
1 D e cenier tap generally Input characteristics are obtained between the input curent and input voltage 1. Plot the input characteristics for different values of Vcaby taking VE
voltage reference point.
0)) Eplanation: The base current controls the collector current when the c utput voltage. It is plotted between VEE andg at constant Vc in CB X-axis and Ig on Y-axis taking Vcp as constant parameler.
ansistor 15 n tne acuve reCgon. A trans1slor is made up ol two PN Juncuons, an
In the working of full wave rectifier both the half cycles will come in the
oniguration. 2. Plot the output characteristics by taking VcB on X-axis and takingIc
osiUuve of negaüve side. The center tapped full wave rectilier uses a cenler tapped
nitter Juncion and a collector junction. The active region is when the emitier eristics are obtained between the output voltage and output
nction is forward biased and the colector junctuon is reverse biase. ranstormer to convert the nput AC oItage inlo oulput DC voltage. Y-axis taking lg as a constarnt parameter
stant input curent. It is plotted between Vcs andlc al constantlg

B COnE
ration.ration.
SQ5. 1n MCchanical Engineernng (5 >emesiet
112 S.QB, in Mechanical Engincering (3 Semester)_ the total phase shift necessary for regenerative
flowing through and output of the amplifier,
the given circuit diagram, the
curent
(0) AS 1s clear from IeedbackK will become 3 * 60 +180 36U as shown
uring the negative half cycle of the input AC signal, teminal A become
plicd, the ndary winding of the center tapped

trans dee this input AC voltage into two parts: positive and negu egative, terminal ABbecome
egative teminal positive
15 connected andp-side
to the centertap 15 g
of the n
diode D, and the positive
2000 mA
Durnng the positive halt cycle of the input AC signal, terninal A

PoSue, e n a l become negave and center tapIs grounded (zeto voLs). IDe
Decome

terminal B is connected to the n-side of the diode

HencelmA
positive terminal A is connected to the p-side of the diode D, andtne negauve 1 Ouput
n the other hand, the positive terminal B is connected to he p-side ot the
the ocitie half cvcle and allows electric current through it. diode D, and the negative terminal A is connected to the -side onea e 0 wbere .019 4180
ue aloueD2 5 Toward Dlased during the Degative halt cyele and aliows ciecinc
During posive Current througn Hence l 5 2 x10 A=52 uA.
dat
The diodeD, Supplies u Cuent to ne 0a0
(a) RC phase-shift oscillators use resistor-capacitor (RC) network (gure
to provide the phase-shift required by the feedback signal. They have excellent
Durine the negative half cycle, current flows only in the lower part of the
wide of loads. Stage 1
circuit while the upper part of the circuit carry no cument to the load because the and can yield a pure sine wave for a range
R yueney saDiuly
the half cycle of the input AC
D1S TeverseDiased. 1nus, during negative
oue
signal, only diode D allows electric current while diode D. does not allow The three ogether to get the required slope tor
RC Sages
C output electric cu
a lon
stabic oscillation trequency. The feedback loop phase shift
phase shift is-180°
is -180° when
when the
the phase
phase
iode D lows ele rent during the positive balf cycle and (tan60° =1.732).
diode D, allows electric current during the negative half cycle of the input A input Oupu
shiftof each stage is-60". This occurs
when o =
21f=D as

Then to achieve the required phase shift in an RC oscllator circut 1s to use

erntre tap 2 signal. As a result, both hair cycies poSinVE and negauveoE g
are allowed. So the output DC voltage is almost cqual to the input AC voI14ge. mulhple RC phase-shifting networks such as the circuit below.

On the other hand, the negalive terminal B is connected to the p-side of the Fig: RC PBase-Shift Network Basic RC Oscillator Cinrcuit
iiode D and the positive terminal A is connected to the n-sideot the diodeD250
During postve
han eycke
ag e postuve nair cycle and does not allow
RC network is expected to have an output which leads the
2 e Ideally a simple
Input AC signal sgral put by 90".
Thediode D, supplies DCcurent to the load R. The DC curent produced at than this as the capacitor CP hase shift
owever,
in
reality, the phase-ditference will be less angle of the RCC
the load Rz wll retun to the secondary winding tnrough a centet ta +ve n h e crcuit cannot be ideal. Mathematically the phase Network
.During the posif+ve halr cycle, curent flows only in the upper part or tine ---------*-FBeddaCK ****
c t w o r k is e p r e s s e a
circuit while the lower part of the circuit carry no current to the load because the
DC Output
fiode D, is reverse biased. Thus, during the positive half cycle of the input AC
ignal, only diode D,. allows clectric curent while diode D, does not allow R
the resistor. In
ectnc Cenue eap D2 unngneguve wbere, Ac 2 the reactance of the capacitor Cand Ris Outpur
ner y

scillators, these kind of RC phase-

shift networks, offering definite
eachcondition a

the phase-shit led by the Ca

(i) Bridge Rectifier: Scientists developed a new type of rectifier known as a an be cascaded s o as to satisfy

bridge rectifier. In bridge rectifier, center tap is not required. If stepping down or 3arkhausen Criter+on.
stepping up of volfage is not required, then even the transiormer can be ehmnated and R is the resistor. In
put the bridge a to Where, c is the reactance of the capacilor C
rectifier.
inthe center tapped the rectierethcaency ot bridge rectieris almostegual
fll wave Tectifie. The only advantage of bridge rectifier over definite
phase- shift networks, each offering a
scillators, these kind of RC The basic RC lator,
center tapped ull wave rectifier is the reduction in cost.
can be cascaded s o as to satisfy the phase-shit conauon led by ne
Oscillator wnicn 1s ak ohtained
from the
In bridge rectifier, instead of using the
center-tappea uransioer,
10r
u
used. Now we get an idea about the three ypes of rectifiers.The halfwave rectifier and
2arkhausen Criterion. Transistor o r an
etcanacitor combination. This regenerative feedback from the RC newos
D During negatve in th We know that in an amplifier circuit either using a Bipolar Or Lae capactor to store an electric charge, (similar to the LC
the
centertutorials. This tutorial is mainly already discussed phase-sin
or
lsu befween this input Detween S input
and
Dy
ious tutonials,
previous tocused o
mainly foaced on the bridge recaner.
produce a network
Amplifier, 1RC phase-shift
perational three-stage
wil
15 connected tank cireuit).
utput. I
 S.Q.B. in Mechanical Engineering (3 Semester) 121
120 S.Q8. in Mechanical Enguneering (nesie S.Q.5, in Mcchanical Engineering (3 SemeEster)
S.Q.B. in Mechanical Engineering (3 Semester)
to

c can e connected
e hiR (chase advance network) as shownto aboe
or interchangca
n c capactor charges up to o c (he upper comparaior imit) which is
roduce e Min tem foOr loop
a lagging phase shift (phase retard networik) the outcome 15 5 determined by the 0.693(R, +R2)C combination and discharges itselt down to

OSCiladons only occur at the frequency at which the overall phase-shit 1 16X1
Sine wave Vcc (the lower comparator imi) determined by the 0.693(R, x Ocombination. Hence
Now we can; implement this+B.
JA, expression using universal gates as follow:
s s60
n6 ar nected togeth This results
i n an output waeform whose voltage level is approximately equal to
(b) In the SS5 Oscuao c
los
nd euery evcle allowing it to V
operate as a free running oscilator. During each cycle capacitor, C charges up the capacitor
and resistors combinations The individual times required to Mux
through both timing resistors,R, and but discharges ser Ouy complete one charge and discharge cycle of the output is therefore given as:
7.
as UDe ouner side ol K 15 connectd to the discharge terminal, pin Astable 555 Oscillator Charge and Discharge Times
K Select ine M
cc *15)
095K *K2R
20.095x R *C
where, R is inN and C in Farads. 8. (a) T Fip-tlop: The name T ilip-tiop 1stermed trom the eontrol circuits.

When comnected as an astable multivibrator, the output from the 555 A, B, C, D) operation. The major applicanons Hind m making it to operate in toggling
T i p tiop Is modified form of JK ip-tlop
Oscillator will continue indefinitely charging and discharging betwecn cc and

TTUUL o c until the power supply is removed. As with the monostable multivibrator

unese charge and discharge hmes and therefore the frcquency are independent on
****** D Cate

OR Gate
Whenever the clock signal is LOW, the input is never going to ailect the
utput state. The clock has to be hgh for the nputs to get acive. 1 nus, I Tp-1loOP
1s a controled Bi-stable latch where the clock Signal is the control signal. 1 hus, uhe
Astable Astable
the supply volage. Hg.(a which have been discussed below.
Oupur output has two stable states
based on the inputs
individual times that the a cual to he sum ot the two
t Ue CapactTOr cnalrges and discnarges added together a n d i s
Which can be simplificd to more realistic implementation having minimum
Threshold given as: 2Der of gales as given below
Io99le-
555 Oscillator Cycle 'Time Pin

* .095K+ 2R,)C Input

n e o p u t irequency of oscillations can be found by inverting the equation
above for the total cycle ume giving a tinal equation tor the output requency ot an
Astable 555 Oscillator as:
555 Oscillator Frequency Equanon: J 1.44
T (R, +2R,)C HA.B,c. D) Truth Table of 'T Flip Flop
Capacitor oram
5. (a) Square Law Modulator: Following is the block diagram of the square
=AD+B
Voltage law modulator.
Clock
INPUT OUTPUT
Fig. (6) RESET T 9
Band S(
Hence the solution is given by the circut grven by Dg. )
X |LOW| x 0
Fiter

f Output
Voltage

Let the modulating

(D) Now here total 32 1nput lines and
Smit one oI the two input to output depending
er MUX 0 - s ) will be selected and for M
T be selecied.
one
output iune. There
on its select
is
2X1 MUX will
line M. So for M

=1 lower MUX 16-1s1) here

0 =
HIGH
HIGH HIGH | 0 No change_
HIGH
LLOw THIGH T_A| No change
Toggle
The T flip tlop is the modified form of JK fip flop. The Q and Q represenis

and carmier signals be denoted

as m() and
respecuvely. These two 51gnals are applied as inputs to the summer (adder) block. Acos(2ct) According to the table, based on the input the output changes its stute. But. the
clock
important thing to consider is all these can occur only in the presence of the
signal. This, Works unlike SR fip Flop and JK füp-tlop for the complimentury
inputs. This only has the toggling tunction.

122 S.Q8. in Mechanicnl Engincening( Seme s.Q3. inMechanicalEngincering(3°Semeser) 28

S.Q.B. in Mechanical Engincering (Semeslen) SQ5, 1n Mechanical Engineering(5 Semester)

Thus summer block produces an output, which is the addition of the modulating The modulation index m, of narrow band FM is small as compared to one
and the camer signal. Mathemaocany. we can
radian. Hence, the spectrum of narrow band FM consists of the camer and uPPe
he D Plp Flop is by far the most important of the clocked flip-flops as it
cnsures that ensures that inputSS and K are never cqual to one at tne sume u e .
Excitation Table
sideband and a lower sideband. For small values of m, the values of the j ume.
ne Q0 Q0+1) T
oeicients are as under:
re
constructed from a gated SR in.
The modulating signal and camier are connected in series with each other and added ber wu an nverier

Sngie D (Data) inpuL

heir sum , ) is applied at the input of the non-linear device, such as diode, m) Then this single Dut lohe
transistor ec. 1nu m2 Sgnal, and the inverter is used to generate the compler e
J m ) =0forn> I.
hercby making a level-sensitive D-type flip-lop froma level-sensitive SR-latch
*EcOs(2I) s now S D and R = not Das shown.
De tnput Ouput relauon tor non-lunear devce 1s as under: Hence, a narrow band FM wave can be expressed mathematically as under,
0)av,)+ bv50) (6) Diferences between Synchronous and Asynchronous Counter

NNow, substituting
cousAns.
the expression () in (i), we get
au)-st)E, sinag+sino, +,- Data (D) o

ouniers
are
ot
two
ypes depending upon
counters areE: ASynchronous counier, and Synchronous counter
clock pulse applied. These

Carrier USB LSB

v 0 - a a0)+E,cos(27f) + br{zt) + E, cog(2xIDP In Asynchronous COunter is also known as Ruppie CoUnter, derent uP
o )=a),cos2* The sign associatedwith the Ls5 represents aphase shit ot 180
Practically, the narow band FM systems have ms less than 1. The maximum
ymbol GoCK (CI O
opare uriggered with diiferent clock h eemeciock simultaneously

1) ) ermissible firequency deviation is restricted to about 5 kHz. This system is used in

SynchronoUS erifaster than asynchronous counter in operaton.
2br( cos (2/+bE;
coa2nf) PM mobile communicaions such as poice wireless, amoulances, taxicabs etC.
GtedCircuitSA FP:10e
and yncnrno
Let's see the diference berween these two counters:
..Wideband FM: For large values of modulation index m the FM wave nvonor

cnronos
0 ) are as unde trically around the carrier. Such a PM wave has infnite
handwidthand D Fiptop ncnronous
Modnlating Signal hence called as wideband FM. Truth table
No
1.nsynchronous counter, all tupin asynchronous counter, aeren
atam

Term 2.:aE, cos(2f) Camrier Signal The modulation index of wideband FM is higher thanl.
flops are triggered wth same cioca
n e naxunun pemiss1e deviauO0 IS k i 2 and t 1s used in the
Tem3. brt Squared modnlating Signal diffTent clock, not simultaneousiy
Tem 4.2bxtcost2): AM wave with only sidebands entertainment broadcastung applicauons such as FM raal0, IV ec.
er is faster than Asynchronous Counter s Siow
Frequency Spectrum of a Wideband FM wave: 2.
Term S.bEcos-(25/) Squared Carier ync nter in operation. than synchronous counter
The cxpression for the wideband FM is complex since it is sine of sine asycrO
Out of chese five tems, terms 2 and 4 are useful whereas the remaining terms anct
usine the Bessel funcions the e Dessel runcuons. By
Characteristic equation: Q0 +)=DO) opcrauD
3. Counter does not produce any Asynchronous counter produces
are notusef tions the equation for wideband FM wave Can de expanded as Excitation Table
Let us elub tems 2, 4 and 1, 3, 5 as follows to get, follows: decoding errors ais
Counter 1s
M 50) bolm,) sin o + ,m,)Nsin(o + o -sin(@ - ] also called Asynchronous
v0)= at) + br-0) + bE^coa*(2f) Synchronous Counter is
Unuseful Terms
*Jaom,)sin(o, +20,-sino, +2+Jtm,)l sinto, +30] |Parallel Counter: designing as
Counter
sin @-3o,+J,ms}sin(o,+4o,)-sin(o 40 1 Synchronous as
Counter designing Asynchronous
as implementation is very casy.
COS)*2bx()E,cos(2n) () well implementation
are
complex well
u e to ncreasing tne mumber of
Comparison between Narrowband FM (NBFM)
Useful Terms and Wideband FM (WBFM)
TFip nop 6. Synchronous Counter wil operure Synearonousb P
The LC unced circuit acts as a bandpass filler. lts froquency responee 15sn SrNo. Parameter
NBEM WBFM Truth Table ence
in fig. 2 which shows that the circuit is tuned to frequency band its bandwidth i in any desired count sequence.
(UP/DO
DOWN). _
equal to 2 , This bandpass filter eliminates the unuseful terms from the equatior 1. Modulation indexLess than or slightlyGreater O+1)
than Asynchronous Counter examples
greater than 1 Q0- Synchronousou
ung countct, 9OnndOu
e are: Ripple UP counter, Kipp
(b) Narrow Band FM: A namow band FM is the FM wave with a small 2 Maximum deviation 5 kHz DOWN counter:
bandwidth. 3. Range of modulating |20 Hz to 3 kHz 20 Hz to I5 kHz Characteristic Equation: Qt + )=TOQ0 + TOQO)= TO E QU
requency

S.Q.B. n Mcchanical Engincering ( Semester 131

124
s.Q.B.inMechanicalEnginceringC8 Semester) S.QB. in Meclhanical Engineerng(3 Semeste)
S.Q.8. in Mechanical Engincering (S Scmesic
Typical values for Vo are around I to 10 mV for cheap commercial-grad determine the
4. Stightly grater than 1 5 t o 2500 There are various factors that
Maximum o p n p negraea c i r u r s ( i s can oe reuucea to Sever i r o vois
. () As per the data given, the values of circuit parameicers are as follow: rower SupPPly Characteristics: voltage regulation,
uhe
Oset n0 using nignerqually
pins or o r laser u m n e d
R s200 2; R; =2 k n ; l2= 25 mA of the power suppiy nolerciection, and so on. Some of the
Large about 15 times c d using
5.
Bandwidth Sna f AM greater than that ot NprM devices. However, the input osetvollage valuie y Output voltage = 30 Volt. source regulauon lained below:
Characteristucs are brietly explained below:
BW - 2(0* Jma Chopper ery low ofset voltages are required. g in
W: 2f is
load etfectfromthe change
Sol -15mA The or

Input bias current and input offset current also affect the net otsset voltage oadKegulation:when load regulaton
the load current changes minnua
Entertainment
ApplicationsS i o n like broadcasting (Can oeu seen for a given amplifier. The voltiage offset due to these cuTeS I5 Case 1. When I =0(minimum)
music pur O g p a a c r and 5 Teated t ue npeunce or ue signa
police wireless, tor high quality L
15 mA Loadregulation = VaoloadVrullond
nuance, Snort ranstmission). source and of the feedback and input impediance neEworx SUD
n g e snup to shore
resistors used n o ave lower input bias currents than bipolar-input
Then IslztL =15 mA.
200x 15x10=3000x Volt =3 Volt no lond Tefers to the Load Voltage at no load

>o volagel t across R's 10 at ful load.

>0 Ys a g e at input side Telers to tne
Load voltage
p-amps, and hence incur less offset of this type all lowd
load
+30)=33V can
understand
that
when OCCurs the
Vno load Val load
6. (a) Block diagram of OP-AMP: p u t Oset volage Is 5ynbolcaly represenied by a votage source that is in
Which 15 minimum volage at input = 33 Volt O equation we
ne Dve equauon we c ls are open circuited.
Block diagram of OP-AMP indicate the following sages: pvo g a v e p u r teminal (it is mathematically
e terms of
resistance
when ine ioad resisa
e f the minimum value where voltage reguauo
equivalent either way). Normaiy input otset voifage IS n nin
otermidiate Lev shifting Outp input voltage applied at the non-inverting terunal to make output zero. eotut Case 2. When l = 25 mA (maximum
Stage JStage Stage Output %Load Regulation = x100
V. (@) 1be grven functon is fA, B, C, D) tall lasd
Non Inverting 15 mA = 40 mA.
inpur

OPAMP is basically a differential amp1.e., it will amplity the voltage which is

ABC +AB + ABD + ABC
ABC=ABCo+D) = +ABCD (1)
o +L=Do00 is
voage 0 0 x 40x10
(2) Minimum Load Resistance: 1The load resistance at wncn a powersuppuy

delivers its ull-joad

rated eurrent at rated voltage 1s releTed to as m

i c r e a l l y prescnt Detween l s p u r terminals.

Input stage: The input stage 15 a dual input, Da1anced ouput e r c u a

AB ABCD+CD) = AB(CD) + ABCD 800x10 Volt = 8 Volt. resistance
Minimum Load Resistance =
So input voltage =8 +30 = 38 Volt.
The input are inveruE AMP and decides the value of input resistance ABC+D)+ ABCD
m the
most of the voltage galn or uie
=ABC(D+D) + ABD(C+)+ ABCD Which is the maximum value of input voltage. should never
i n c r e a s e than that mentoned
Hence range of the input voltage IS= Vmin to m a x 3 3 Volt to 38 Volt. De vaue oall load Curent
datasheet oE Ue power
Intermediate stage: This is usually another difterential amp. 1ne inpur stage ABCD+ABCD + ABDC+ ABDC + ABCD has
(6) REGULATED POWER SUPPLY
Regulation:
In
the block the input line voltage
diagram,
g s a uaL 1nput unoncea ouuput aurerenated amp.
Level-shifting s t a g e : Due to direct coupling USed D e w e n n e Sg
ABD ABD(C+)=(ABCD + ABCD) -- ( )
supply is an electronic circuit that is designed to providc a 3) Source/Line IEs Dut in practice, here are considerable vanatons in ac

constant DC voltage of predetermined value across load terminals irespectve or

olv mains voltage.Snce his aC Suppuythe bridge
vogrectiier is
the input of
level snu
o hrino dc level to zero volts with respect to gnd
dc
ABC= ABCD +D)=ABCD +ABCD
Using the k-Map the grven expressions can be solved as rouow
-

ac mains tiuctuations Or koad v u n a u o ordinary Ppower supply, ne tered oupur

directly

level Level siu A regulated power supply essentialuy co t from an

oge
is normally
complenenty capaDilya regulated output voltage
for
bity of or nd a voltage reg 5 e oltaee reeulating device that provides the final
1he source regulanon
is dehned as the change n

ases the magnitude of voltage and raises the current suppiying

AB a speciied rage or ne v O g
OP-AMP. t also ensures that the output resIstance of OPAMP 1S Iow. ordinary Pow voltage remains constant irespective of variations in the ac (4) utput impedance:ATEgulaled power suppiy 15 a very stt De votag
(6) The input ofset voltage (Vos) is a paramcter dehning the ditferental Dc th-
input voltage or variations in output (or loaa) cu small. Even though
voltage required between the inputs of an ampliner, especialy an operational
output resistance is very A
Figure given below sDowS De compec curcut or a g a c u power supply the load voltage.
the circuit is
So ad resistance is varied, almost no change is seen in

Tor voiltage ampiiners,

Ovolts with
regulalor as a regulating device. Each part of Or Zeto.
ampuner (oP-amp), to
mare
ne ouput zero
outpuis, aependang oupur type)-
on n e
with a transistor s e i e s
ideal voltage source has an output impedance
between differential Cxplained n detail. (5) Ripple Rejection: Voltage regulators stabilize the output voltage again-
respect to ground or

1S
ditterentual inpu, tnis input cirerence
ir

An 1deal op-amp amplfies

the
v 1s
o
volts (1.e. both inputs are at tne same v o g vanations in input voitage. ppie uventoe
voltage. Thus, a vollage regutator aenuates e ppic negative feedback, u
f real op-amns Voitage
due to manufacturing process he utout to be zero at a non-zeto value LoOp unregulated input voltage. SlnCc v o g

may not be exay inpu egug

distortion is reduced by the same factor as the gain.
of differential input, called the input offset voltage