13.

3
A Constant Slew-Rate Ethernet Line Driver
David S. Nack
Level One Communications, Inc., an Intel Company,
9750 Goethe Rd, Sacramento, CA 95827-3500

Abstract The slew rate in the middle of the M12/13’s transition

region (assuming all devices stay saturated) is:
A biasing technique is described that facilitates the
design of a fast ethernet line driver. The slew rate is I ulrl oc I bias I tuil

insensitive to temperature and process variations. The T c v 011 12 ,I3

(1)
core-biasing block consists of three current sources, a
resistor, and two transistors. 230ppm/deg C Where Von = VGS - VT (2)
temperature drift is achieved without trimming.
Since Itail sets the output swing across an external
Introduction resistor, it must be held constant to maintain accurate
amplitude control. If (3 is implemented with a MOS
Many applications, including communications, require device, it will be insensitive to temperature and supply
that a line driver produce a pulse shape that conforms variations, and only weakly sensitive to process
to a fixed template. To be manufacturable, these variations. Therefore, if lbias can be made to track Van,
devices must have output slew rates that are an accurate slew rate can be attained. The starting
insensitive to variations in process, temperature, and point for creating lbias is shown in Fig. 2.
power supply voltage. Trimming can be employed to
remove the process variation, but this adds I1 lbias
manufacturing cost, and is impractical if the untrimmed
vc c <-- <--
t I T

circuit is sensitive to temperature. Phase locked loops

can be used to create a replica biasing circuit, which
slaves to an off chip timing reference [l], but this
v
technique is more complex and consumes more power
than what is described in this work. Also, a tradeoff FIG. 2
exists between matching (best with pll in proximity) and
noise injection from the clocks and oscillator (best with If a fixed voltage (V) is applied to M2’s gate, then the
pll physically separated). A pll can also be used to drain current in M I is given by:
create an over-sampled waveform synthesizer [2],
which has the additional limitation that post-filtering
must be performed to minimize electro-magnetic
interference.
pnCoxW
Circuit Description
Where p = 2L for 192 (4)
If another constant current (Ix) is added to 11, and the
result is divided by Van, one can test whether the
desired tracking has been achieved:

I I1

I,

I,

1)

>k1°
Dataln M l q F Let It=l amp, V=OS volt, and let V,. vary from 0.5 to 1.0
- volt. This implies that p varies from 4 to 1 amp/square volt
1 to allow for both process and temperature variations. (The
,I II I1

temperature raised to the -1.5 power dependence on

mobility gives p a 1.75X variation for a 0 to 125 degree
C temperature range. This leaves a 2.3X variation for
slow to fast process corners.) Ix can then be chosen to
satisfy the desired relationship at the two extremes.

176 0 2000 IEEE

0-7803-6309-4/00/$10.00 2000 Symposium on VLSl Circuits Digest of Technical Papers

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 lt=400ua, Ix=60ua, and llail=l 000ua. M I draws only
For p = 1 J&@ = IX + 0.169 (7) about 5ua out of the 400ua in the fastest
Von
procesdtemperature corner. If M I , 2 were made any
For p =4 Ibicls - 21x
-- stronger, MI would shut off, and tracking would be
Von (8) compromised in the fast corner. MI, 2 can be made
Therefore, if Ix=O.I 69 amp, then- lbias/Von=O.338 weaker and tracking can still be achieved with a lower
amplvolt at the two end points. The ratio is now: value of Ix. However, the sensitivity to mismatches in
the R, MI, M2 circuitry is minimized if the I1 component
of lbias is minimized, which requires maximizing Ix. The
output stage is a 1:20 current mirror with active
While this ratio is not an independent function of p, it is termination. The actual implementation biases M2’s
quite accurate over the range of interest. As the plot in drain to the same voltage as that of MI, and a separate
Fig. 3 shows, the total variation in lbias/Von is 1.066, or reference creates the appropriate potentials for the
plus and minus 3.3%. clamp circuitry.

0.35 t Measured Results

This circuit was fabricated in a 0.35um 3.3volt CMOS

process for a 100BaseTx application where the
specified rise time limit was from 3.0 to 5.0 nsec.
Simulations without offsets predict a total variation
(process, temperature and voltage) of plus and minus
220psec from a 4.0nsec nominal. Fig. 5 shows the
measured output waveform on infinite persistence with
Fig. 3 a temperature sweep from -5 to 135 degrees C with
1.0 2.0 30 4.0
less than 130psec of drift (230ppm per degree C).
This tracking can be understood intuitively by Tek 2 OOtSlr 9003 ACqs
considering the V ,, of M1 ,2with process variation. A . . , .. . . , . . . . * ’ . . , . . ..
. * , . . . . , . .t------c-H----j I . .-r-r-,

slow process corner will yield a weaker device and . . . .

.. .. .. ..
therefore a larger Vow As V O n increases, the fixed
differential voltage applied to the gates will become a .. .. .. .. .
smaller percentage of VOn, such that the current
steering will be more balanced between M I and M2,
and I1 will increase. So a larger VOn will result in a
larger Ibias. Since the lbiascurrent created by MI, 2 ,. .. .. .. -
needs to track the V ,, of M12, 13, these two differential
pairs need to match each other. A more complete
Fig. 5
implementation is shown in Fig. 4. The clamp circuits
keep all devices in saturation and limit the differential
References
voltage swing on A, while maintaining a minimum 100/1
on/off ratio in M12/13. Ir is derived from a bandgap [I] J.E. Kardontchik, “Introduction to the Design of the
voltage across an internal resistor of the same type as Transconductor- Capacitor Filters” Kluwer Academic
R such that VbiaS-Vx=450mV. For W and L sizing, Publishers, 1992, pp219-233
MI=M2, M10=M11, and M12=M13. M12,13 are made [2] C. Shih et al., “System and Method Employing
from the same unit cells as MI, 2. Predetermined Waveforms for Transmit Equalization”.
US Patent 5267269, Nov. 30, 1993.

7
I I
FIG. 4

vc c I1 lbias
<--
T
I
lbias I
V
T

vx ”
I I
IR I It I Ix
V V V

2000 Symposium on VLSl Circuits Digest of Technical Papers 177

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