Assignment 4

First Semester
Session 1441/1442 AH

Student Name :

Student ID :

Student Signature :

Department : Department of Computer Science Marks

Course Code : COCS 311
Course Name : Computer Architecture
Deadline : Saturday, November 21, 2020
Number of Exam Pages : 2
6
Marks
Outcome 1 /5
5 Marks
NB! Only Hand Written assignment will be evaluated.
Outcome 2 /1
1 Marks

Total Marks
(In Figure) / 6 Marks

Total Marks
(In Words)

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 Outcome 1 &2 [6]
Q1.
a. Write at least six difference between RISC and CISC. [1.1] [1]
b. Illustrate the Memory Mapped IO. [1.2] [1]
c. Illustrate what do you mean by Interrupt. Write its main purpose. Discuss hardware interrupt,
Software interrupt and priority interrupt. Explain how interrupts are prioritized. [1.2] [3]

Q2. Justify the purpose of Program Counter and Instruction Register. [2.3] [1]

Best of Luck

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Q1
a)

RISC CISC
Columns are difficult columns are easy
emphasis on hardware emphasis on software
the register is less complexity in compiler
use allot of microprogramming instruction set with formats less
addressing modes more than CISC Less addressing modes
multiple instruction formats and size. register more

b)

Memory Mapped I/O:

There is a single address space for memory locations and I/O devices.
A single read line and a single write line are needed on the bus.

• Devices and memory share an address space

• I/O looks just like memory read/write
• No special commands for I/O
• Large selection of memory access commands available

c)

Interrupt • Interrupt is processor's response to an event which software, attention is required.

• It alerts the processor of interrupt and act as request to processor.
• Interrupt has highest priority for software and hardware events.
Purpose of Interrupt • Main purpose of interrupt is to increase efficiency of processor.
• Processor is faster as compared to external devices therefore a lot of time is wasted
matching their speeds. Interrupt is useful to overcome these limitations.
hardware interrupt • when any external device or hardware send signal for processor it's hardware
Interrupt.
• These are of two types:
1. Maskable: These can be delayed when higher priority interrupt arrives.
2. Non-Maskable; these can't be delayed and require immediate processing
Software interrupt • Caused by internal system
• These are of two types:
1. Normal interrupt: when any software instruction case interrupt
2. Exception: these are not planned; they generate by own during program exception
priority interrupt It's used to decide the priority of interrupt causing devices. This priority is then used by
processor to respond to interrupts.
how are interrupts • Interrupt are prioritized using Daisy currently being excepted.
prioritized? • All interrupt generating devises are serially connected.
• The devises are then arranged in decreeing order of priority highest at first and
lowest at last

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 Q2

program counter:

• It stores the address of the instruction currently being excepted.

• It's registers in processor.
• After fetching instruction is increase the program counter by 1.

Instruction Register:

• It stores current instruction being either excepted or decoded

• Also known as current instruction register.

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