Data Transfer Instructions

Instruction Byte Addressing Machine Cycle T-states Flag

mode
MVI R, data 2 Immediate OF + MEMR 4+3=7 NO
MVI M, data 2 Immediate, OF + MEMR + MEMW 4 + 6 = 10 NO
Indirect
MOV R1, R2 1 Register OF 4 NO
MOV R, M 1 Indirect OF + MEMR 4+3=7 NO
MOV M, R 1 Indirect OF + MEMW 4+3=7 NO
LXI RP, 16-bit 3 Immediate OF + 2 MEMR 4 + 6 = 10 NO
LDA addr 3 Direct OF + 3 MEMR 4 + 9 = 13 NO
STA addr 3 Direct OF + 2 MEMR + 1 MEMW 4 + 9 = 13 NO
LDAX RP 1 Indirect OF + MEMR 4+3=7 NO
STAX RP 1 Indirect OF + MEMW 4+3=7 NO
LHLD addr 3 Direct OF + 4 MEMR 4 + 12 = 16 NO
SHLD addr 3 Direct OF + 2 MEMR + 2 MEMW 4 + 12 = 16 NO
XCHG 1 Register OF 4 NO
 Arithmetic Group Instructions

Instruction Byte Addressing Machine Cycle T-states Flag

mode
ADD R 1 Register OF 4 ALL
ADC R 1 Register OF 4 ALL
ADD M 1 Indirect OF + MEMR 4+3=7 ALL
ADC M 1 Indirect OF + MEMR 4+3=7 ALL
ADI data 2 Immediate OF + MEMR 4+3=7 ALL
ACI data 2 Immediate OF + MEMR 4+3=7 ALL
SUB R 1 Register OF 4 ALL
SBB R 1 Register OF 4 ALL
SUB M 1 Indirect OF + MEMR 4+3=7 ALL
SBB M 1 Indirect OF + MEMR 4+3=7 ALL
SUI data 2 Immediate OF + MEMR 4+3=7 ALL
SBI data 2 Immediate OF + MEMR 4+3=7 ALL
INR R 1 Register OF 4 ALL - CY
INR M 1 Indirect OF + MEMR + MEMW 4 + 6 = 10 ALL - CY
INX RP 1 Register OF 6 NO
DCR R 1 Register OF 4 ALL - CY
DCR M 1 Indirect OF + MEMR + MEMW 4 + 6 = 10 ALL - CY
DCX RP 1 Register OF 6 NO
DAA 1 Implicit OF 4 ALL
DAD RP 1 Register OF + 2BI (BUS IDEAL) 4 + 6 = 10 CY
 Logical Group Instructions

Instruction Byte Addressing Machine T-states Flag

mode Cycle
ANA R 1 Register OF 4 ALL, AC = 1, CY = 0
ANA M 1 Indirect OF + MEMR 4+3=7 ALL, AC = 1, CY = 0
ANI data 2 Immediate OF + MEMR 4+3=7 ALL, AC = 1, CY = 0
ORA R 1 Register OF 4 ALL, AC = 0, CY = 0
ORA M 1 Indirect OF + MEMR 4+3=7 ALL, AC = 0, CY = 0
ORI data 2 Immediate OF + MEMR 4+3=7 ALL, AC = 0, CY = 0
XRA R 1 Register OF 4 ALL, AC = 0, CY = 0
XRA M 1 Indirect OF + MEMR 4+3=7 ALL, AC = 0, CY = 0
XRI data 2 Immediate OF + MEMR 4+3=7 ALL, AC = 0, CY = 0
CMA 1 Implicit OF 4 NO
CMP R 1 Register OF 4 CY Z Result
CMP M 1 Indirect OF + MEMR 4+3=7 0 0 A>M
0 1 A=M
CPI data 2 Immediate OF + MEMR 4+3=7
1 0 A<M
CMC 1 Implicit OF 4 CY
STC 1 Implicit OF 4 CY
RLC 1 Implicit OF 4 CY
RRC 1 Implicit OF 4 CY
RAL 1 Implicit OF 4 CY
RAR 1 Implicit OF 4 CY

RLC RAL

RRC RAR
 Branch Group Instruction
Instruction Byte Addressing Machine Cycle T-states Flag
mode
JMP addr 3 Immediate OF + 2 MEMR 4 + 6 = 10 No
Jcond addr 3 Immediate TRUE : OF + 2 MEMR 4 + 6 = 10 No
FALSE : OF + MEMR 4+3=7
CALL addr 3 Immediate, OF + 2 MEMR + 2 MEMW 6 + 12 = 18 No
Indirect
Ccond addr 3 Immediate, TRUE : OF + 2MR + 2 MW 6 + 12 = 18 No
Indirect FALSE : OF + MEMR 6+3=9
RET 1 Implicit OF + 2 MEMR 4 + 6 = 10 No
Rcond 1 Implicit TRUE : OF + 2 MEMR 6 + 6 = 10 No
FALSE : OF 6
RST n 1 Indirect OF + 2 MEMW 6 + 6 = 12 No
PCHL Rp 1 Direct OF 6 No

Stack, I/O, Machine Control

Instruction Byte Addressing Machine Cycle T-states
mode
PUSH Rp 1 Register (source) OF + 2 MEMW 4 + 6 = 10 N
Indirect (dest)
POP Rp 1 Register (dest) OF + 2 MEMW 4 + 6 = 10 N
Indirect (source)
SPHL 1 Register OF 6 N
XTHL 1 Register OF + 2 MEMR + 2 MEMW 4 + 12 = 16 N
IN Port addr 2 Direct OF + MEMR + I/O READ 4 + 6 = 10 N
OUT Port addr 2 Direct OF + MEMR + I/O WRITE 4 + 6 = 10 N
HLT 1 Implicit OF ( bus idle ) 5 N
NOP 1 Implicit OF 4 N
DI 1 Implicit OF 4 N
SIM 1 Implicit OF 4 N
RIM 1 Implicit OF 4 N