EC8691 - Microprocessors and Microcontrollers (Ripped From Amazon Kindle Ebooks by Sai Seena)

SUBJECT CODE : EC8691
Strictly as per Revised Syllabus of

Anna University
Choice Based Credit System (CBCS)
Semester - V (CSE / IT)
Semester - VI (ECE)
Microprocessors
& Microcontrollers
Atul P. Godse
M.S. Software Systems (BITS Pilani)
B.E. Industrial Electronics
Formerly Lecturer in Department of Electronics Engg.
Vishwakarma Institute of Technology,
Pune.
Dr. Deepali A. Godse

M.E., Ph.D. (Computer Engg.)
Head of Information Technology Department,
Bharati Vidyapeeth's College of Engineering for Women,
Pune.
® ®
TECHNICAL
PUBLICATIONS
SINCE 1993 An Up-Thrust for Knowledge
(i)
Microprocessors & Microcontrollers
Subject Code : EC8691
Semester - V (Computer Science & Engineering / Information Technology)

Semester - VI (Electronics & Communication Engineering)
First Edition : June 2019

Reprint : January 2020
Second Revised Edition : June 2020
ã Copyright with Authors

All publishing rights (printed and ebook version) reserved with Technical Publications. No part of this book
should be reproduced in any form, Electronic, Mechanical, Photocopy or any information storage and
retrieval system without prior permission in writing, from Technical Publications, Pune.
Published by :
® ®
Amit Residency, Office No.1, 412, Shaniwar Peth,
TECHNICAL Pune - 411030, M.S. INDIA, Ph.: +91-020-24495496/97
PUBLICATIONS
SINCE 1993 An Up-Thrust for Knowledge Email : sales@technicalpublications.org Website : www.technicalpublications.org
Printer :
Yogiraj Printers & Binders
Sr.No. 10/1A,
Ghule Industrial Estate, Nanded Village Road,
Tal. - Haveli, Dist. - Pune - 411041.
ISBN 978-93-332-0231-2
9 789333 202312 AU 17
9789333202312 [2] (ii)

 
T/3 2T/3
TON TOFF
T
modes :
SP
15 8 7 0
AX AH AL CS BP
BX BH BL DS SI
CX CH CL ES DI
DX DH DL SS F IP
(a) General purpose registers (b) Segment registers (c) Flag register (d) Pointer and
index registers
Address
FFFFFH
Extra segment 64 K
ES
Stack segment 64 K
SS 1 Mbyte
physical
memory
Data segment 64 K
DS
Code segment 64 K
CS
00000H
Memory
interface
BIU C-bus
C-Bus

6
5 Instruction
B-bus 4 stream
3 byte
ES
2 queue
CS
SS 1
DS
IP
Control
system
EU A-bus
AX AH AL
BX BH BL
Arithmetic
CX CH CL logic unit
DX DH DL
SP
BP
SI Operands
DI Flags
Time required for execution of two instructions without pipelining
Time
saved
Sequential F1 D1 E1 F2 D2 E2
phases
BIU F1 F2 F3
Overlapping
phases
EU D1 E1 D2 E2 D3 E3
Time required for execution of two

instructions because of pipelining
8085 Compatible flags
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U U U U OF DF IF TF SF ZF U AF U PF U CF
U = Undefined Carry flag : Set by carry out of MSB

Parity flag : Set if result has even parity
Auxiliary carry flag for BCD
Zero flag : Set if result = 0
Sign flag = MSB of result
Single step trap
Interrupt enable
String direction
Overflow
0110 0101 1101 0001
 0010 0011 0101 1001
1000 1001 0010 1010
Physical address
FFFFFH Highest address
7FFFFH Top of extra segment
64 K
70000H Extra segment base ES = 7000H
5FFFFH Top of stack segment
64 K
50000H Stack segment base SS = 5000H
4489FH Top of code segment
64 K
348A0H Code segment base CS = 348AH
2FFFFH Top of data segment
64 K
20000H Bottom of data segment
00000H
Physical memory
Physical addresses
Top of code segment 4489FH CS 3 4 8 A 0 Implied zero

(nibble)
IP + 4 2 1 4
4 zero bits
Physical address 3 8 A B 4
Code byte 38AB4H

IP = 4214H
CS = 348AH Start of Code segment
348A0H
(a) (b)
End of stack segment 3FFFFH
Top of stack 38434H
SP = 8434H
SS = 3000H Start of stack segment 30000H

3000 0 H SS
+
001 0 H BP
Physical Address 3 0 0 1 0 H
2000 0 H DS
+
002 0 H BX
001 0 H BP
+
004 0 H SI
Effective Address 005 0 H
3000 0 H SS
+
005 0 H EA
1000 0 H CS
+
002 0 H BX
 
 
 
 

 BX  1, BX

ES 7 0 0 0 0 H
SI + 1 0 0 0 H
7 1 0 0 0 H
SS 9 0 0 0 0 H
SP + 0 0 0 0 H
9 0 0 0 0 H
DS 8 0 0 0 0 H
DI + 2 0 0 0 H
8 2 0 0 0 H
DS 8 0 0 0 0 H ES 7 0 0 0 0 H
SI + 1 0 0 0 H DI + 2 0 0 0 H
8 1 0 0 0 H 7 2 0 0 0 H
DS 8 0 0 0 0 H
DI + 2 0 0 0 H
8 2 0 0 0 H
DS 8 0 0 0 0 H
EA + 2 0 8 D H
8 2 0 8 D H

DS 8 0 0 0 0 H
EA + 1 0 2 D H
8 1 0 2 D H
ES B 0 0 0 0 H
+ EA 2 0 5 D H
B 2 0 5 D H
SS A 0 0 0 0 H
+ SP 0 0 0 0 H
A 0 0 0 0 H
DS 6 0 0 0 0 H
+ EA 2 4 2 D H
6 2 4 2 D H
DS 6 0 0 0 0 H ES B 0 0 0 0 H
+ SI 2 0 0 0 H + DI 3 0 0 0 H
6 2 0 0 0 H B 3 0 0 0 H
Source address Destination address
DS 6 0 0 0 0 H
+ SI 2 0 0 0 H
6 2 0 0 0 H
DS 6 0 0 0 0 H
+ EA 3 0 8 D H
6 3 0 8 D H

DS 6 0 0 0 0 H
+ EA 2 0 0 2 H
6 2 0 0 2 H

 [10H]

124B 0 H
+ 341 C H
158C C H
1085 0 H
+ 453 7 H
14D8 7 H
( 341B )H
(123A )H
OS 123A0  implied zero
Offset  341B
157BB physical address
Memory stack segment
30036H
30035H
CX
CH CL 30034H
20 30 30 30033H
20 30032H
30031H
30030H
SP 0034
30000H
30000
SS 3000 +
SS  10H
30045H
30044H
40 30043H
40 50 50 30042H
CH CL
30041H
CX
30040H
SP 0042
30000H
30000
SS 3000 +
SS  10H
CX  0









A B
X X X X X X X X Unknown 8-bit binary number
1 1 1 1 0 0 0 0 Masking pattern
X X X X 0 0 0 0 Result
Masked bits
+ 1 1 1 1 0 0 0 0 Setting pattern
1 1 1 1 X X X X Result
Set bits
Y  A BA B
+ 0 0 0 0 1 1 1 1 Pattern for inverting lower 4-bits
X X X X X X X X Result
Inverted bits
0 0 0 0 0 0 0 1 Bit pattern to test bit 0
0 0 0 0 0 0 0 X Result
Tested bit
2n
CY Target register or memory
SHL 0
CY
SAL 0
CY
SHR 0
CY
SAR
Sign bit (MSB)

CY B7 B6 B5 B4 B3 B2 B1 B0
0 1 0 1 1 0 1 1 1 0
After execution 1 0 1 1 0 1 1 1 0
B7 B6 B5 B4 B3 B2 B1 B0 CY
0 1 0 1 0 1 0 0 1 0
After execution 0 1 0 1 0 1 0 0 1
B7 B6 B5 B4 B3 B2 B1 B0 CY
1 0 1 0 1 0 0 1 0
1 1 0 1 0 1 0 0 1
CY Target register or memory
RCL
( Rotate left through carry )
CY
ROL
( Rotate left )
CY
RCR
( Rotate right through carry )
CY
ROR
( Rotate right )
CY B7 B6 B5 B4 B3 B2 B1 B0
1 0 1 0 1 0 1 1 1
0 1 0 1 0 1 1 1 0
B7 B6 B5 B4 B3 B2 B1 B0 CY
1 0 1 0 0 0 1 1 0
1 1 0 1 0 0 0 1 1
CY B7 B6 B5 B4 B3 B2 B1 B0
0 1 0 1 0 1 1 0 1
1 0 1 0 1 1 0 1 0
B7 B6 B5 B4 B3 B2 B1 B0 CY
1 0 0 1 1 0 1 0 1
1 1 0 0 1 1 0 1 0
 



opcode
short EB Disp
opcode
near Disp Disp

E9
Low High
opcode
IP IP CS CS
far EA High High
Low Low







Mnemonic Source operand
AGAIN : ADD AX, price [BX] ; Add price of item to AX
Label Destination operand Comment

Time period Start
Define problem
Program
Develop algorithm File extensions
development
time
Create assembly language
program using any text editor ASM
Assemble
if
Assemble time YES
assembly
error
NO
Object code module in binary OBJ
LST
Link
Link time
Linked modules EXE
MAP
Locate time Locate BIN
NO External YES
system?
Load debugger Load emulator
Load
time
Load program Load program
Execution Run and test program Run and test program

time
Errors NO NO Errors
? ?
YES YES
Use debugger to Use debugger to
find errors Stop find errors
[
Assembly language
Source program text written
module in any text editor [
Make
Error corrections
messages
Assemble time Assembler

Listing
Object
Other object module
modules
Modules from Memory

Link time library Linker map
Linked
modules
(Load module)
Load time Loader

1010 ......... 0010
1011 ......... 0110
0010 ......... 1010
0101 ......... 0111 Processor
1101 ......... 1010
main
Program
Execution time
1100 ......... 0011
memory
execution 0011 ......... 1100
1010 ......... 0111
0001 ......... 1011
CPU
Both data
segments have
same starting
address
DATA for DATA for

source source Data
module 1 module 2 segment
Code for
source
module 1
Code
segment
Code for
source
module 2
(a)
My_stack
segment
150
words
combined
stack
Top_of_stack
(b)
End of stack segment 4FFFFH
Top of stack 49F20H
SP = 9F20H
SS = 4000H Start of stack segment 40000H

AX 4455H
CX 1234H AX 4455H
End of stack segment End of stack segment
4FFFFH CX 1234H 4FFFFH
SP FFFFH
4FFFEH 44 H 4FFFEH
4FFFDH 55 H 4FFFDH
4FFFCH 12 H 4FFFCH
4FFFBH SP FFFBH 34 H 4FFFBH Top of stack
4FFFAH 4FFFAH
40003H 40003H
40002H 40002H
40001H 40001H
SS 4000H Start of stack segment SS 4000H Start of stack segment
40000H 40000H
(a) Before execution (b) After execution of PUSH AX and PUSH CX
BX DX BX 4455H DX 1234H
End of stack segment End of stack segment 4FFFFH

4FFFFH SP FFFBH Top of stack
44 H 4FFFEH 44 H 4FFFEH
55 H 4FFFDH 55 H 4FFFDH
12 H 4FFFCH 12 H 4FFFCH
SP FFFBH 34 H 4FFFBH Top of stack 34 H 4FFFBH
4FFFAH 4FFFAH
40003H 40003H
40002H 40002H
40001H 40001H
SS 4000H Start of stack segment SS 4000H Start of stack segment
40000H 40000H
(a) Before execution (b) After execution of POP DX and POP BX

PROCEDURE 2
MAINLINE PROCEDURE 1
CALL CALL CALL

PROCEDURE 1 PROCEDURE 2 PROCEDURE 1
NEXT MAINLINE RETURN

INSTRUCTION
AFTER CALL
RETURN TO
MAIN PROGRAM
PROCEDURE PROCEDURE PROCEDURE

MAINLINE RECURSIVE RECURSIVE RECURSIVE
CALL
RECURSIVE CALL CALL CALL
NEXT MAINLINE
INSTRUCTION
PROCEDURE RECURSIVE RET RET RET
IF N
DECREMENT N
CALL RECURSIVE
ELSE
RETURN





 IF XX (condition) 


ELSE (optional)  Conditional Block


 ENDIF (end of IF) 



4  (Count  1)  (2  16)  (2  4)
MOV CX, Count Loop Last loop
 
1

10 MHz

 
Required delay time

Time for 1 - clock cycle
50 ms
0.1 s
Number of required clock cycles  4  (2  4)
Execution time for one loop
500 000  4  6
(16  2)


4  (count  1)  ( 2  16)  (2  4) ] 
MOV CX, Count Loop Last loop
 
 
INTERRUPT
SERVICE
PROCEDURE
MAINLINE PUSH FLAGS
PROGRAM CLEAR IF PUSH REGISTERS
CLEAR TF
PUSH CS
PUSH IP
FETCH ISR ADDRESS
POP IP
POP CS POP REGISTERS
POP FLAGS IRET
ADDRESS
3FFH
TYPE 255 POINTER :
(AVAILABLE)
3FCH
AVAILABLE INTERRUPT
POINTERS (224)
TYPE 33 POINTER :
(AVAILABLE)
084H
TYPE 32 POINTER :
080H (AVAILABLE)
07FH
TYPE 31 POINTER :
(RESERVED)
RESERVED INTERRUPT
POINTERS (27)
TYPE 5 POINTER :
(RESERVED)
014H
TYPE 4 POINTER :
OVERFLOW
010H
TYPE 3 POINTER :
1-BYTE INT INSTRUCTION
00CH
DEDICATED INTERRUPT TYPE 2 POINTER :
POINTERS (5) NON-MASKABLE
008H
TYPE 1 POINTER :
SINGLE-STEP
004H
TYPE 0 POINTER : CS BASE ADDRESS
DIVIDE ERROR IP OFFSET
000H
16 BITS
11  4  44 10

T1 T2 T3 T4 T1 T1 T1 T2 T3 T4
ALE
LOCK
INTA
FLOAT
AD0-AD15 Interrupt type
 



MAIN PROGRAM
NMI
DIV
DIVIDE ERROR
PUSH FLAGS, CS, IP

CLEAR TF & IF
TRANSFER CONTROL
IF = 0 TF = 0
PUSH FLAGS, CS, IP

CLEAR TF & IF
TRANSFER CONTROL
EXECUTE NMI
EXECUTE DIVIDE
ERROR ROUTINE
RETURN TO MAIN PROGRAM

INTA
 


(Max (Min
mode) mode)
GND 1 40 VCC GND 1 40 VCC
AD14 2 39 AD15 A14 2 39 A15
AD13 3 38 A16/S3 A13 3 38 A16/S3
AD12 4 37 A17/S4 A12 4 37 A17/S4
AD11 5 36 A18/S5 A11 5 36 A18/S5
AD10 6 35 A19/S6 A10 6 35 A19/S6
AD9 7 34 BHE/S7 A9 7 34 SS0 (HIGH)
AD8 8 33 MN/MX A8 8 33 MN/MX
(Min (Max
AD7 9 32 RD mode) AD7 9 32 RD mode)
AD6 10 8086 31 RQ/GT0 (HOLD) AD6 10 8088 31 HOLD (RQ/GT0)
CPU CPU
AD5 11 30 RQ/GT1 (HLDA) AD5 11 30 HLDA (RQ/GT1)
AD4 12 29 LOCK (WR) AD4 12 29 WR (LOCK)
AD3 13 28 S2 (M/IO) AD3 13 28 IO/M S2
AD2 14 27 S1 (DT/R) AD2 14 27 DT/R S1
AD1 15 26 S0 (DEN) AD1 15 26 DEN S0
AD0 16 25 QS0 (ALE) AD0 16 25 ALE (QS0)
NMI 17 24 QS1 (INTA) NMI 17 24 INTA (QS1)
INTR 18 23 TEST INTR 18 23 TEST

CLK 19 22 READY CLK 19 22 READY
GND 20 21 RESET GND 20 21 RESET
RQ GTO M IO
TEST
RQ GTO DEN
IO
Data bus D15 D8 D7 D0

(D0-D15)
BHE A0
CS CS
Bank 1 Bank 0
(512 bytes) (512 bytes)
Address
bus A1 A19 A1 A19
(Odd addressed memory bank) (Even addressed memory bank)

1 Mbytes
512 kbytes 512 kbytes

15 8 7 0
FFFFFH FFFFEH
Reserved
FFFFDH FFFFCH
FFFFBH FFFFAH
FFFF9H FFFF8H 16 bytes
FFFF7H FFFF6H
Dedicated
FFFF5H FFFF4H
FFFF3H FFFF2H
FFFF1H FFFF0H
003FFH 003FEH
003FDH 003FCH
0007FH 0007EH
0007DH 0007CH
Reserved Interrupt
vector
table
00015H 00014H
128 bytes 00013H 00012H
00011H 00010H
Dedicated
00003H 00002H
00001H 00000H
Odd Bank Even Bank
7 0
FFFFH
FFFEH
00FFH 64 K
00FEH I/O space
Reserved
00F8H
Page 0
00F7H
0001H
0000H
+VCC
+VCC
MN/MX
CLK
R 8284A ALE STB
Clock READY
BHE BHE
generator 8282
RESET
Address Address
RES A19-A16 latch bus
C RDY
(3)
AD15-AD0 OE
WAIT
STATE
8086 CPU
GENERATOR
8286 Data
Transceiver bus
(2)
DEN OE
DT/R T
(Optional for increased

data bus drive)
M/IO
WR
RD
HOLD Control
HLDA
bus
INTR
INTA
8282 8283
DI0 D Q DO0 DI0 D Q DO0

CLK CLK
DI1 DO1 DI1 DO1
DI2 DO2 DI2 DO2
DI3 DO3 DI3 DO3
DI4 DO4 DI4 DO4
DI5 DO5 DI5 DO5
DI6 DO6 DI6 DO6
DI7 DO7 DI7 DO7
STB OE STB OE
AD0 A0 B0
AD1 A1 B1
AD2 A2 B2
AD3 A3 8 B3 Data Bus
AD4 A4 2 B4
AD5 A5 B5
AD6 A6 8 B6
AD7 A7 6 B7
DEN OE
DT/R T
8086
AD8 A0 B0
AD9 A1 B1
AD10 A2 B2
AD11 A3 8 B3 Data Bus
AD12 A4 2 B4
AD13 A5 B5
AD14 A6 8 B6
AD15 A7 6 B7
OE
T
RES D
Q RESET
CLK
X1
XTAL
X2 Oscillator
OSC
F/C
+3 +2 PCLK
SYNC SYNC
EFI
CSYNC
RDY1
AEN1 CLK
RDY2 CLK CLK

D Q D Q READY
AEN2 FF1 FF2
ASYNC
X1 X2
EFI CLK CLK
RESET RESET
F/ C
AEN1
AEN2 READY READY
CSYNC
+5 V
8284 8086
Clock generator
10 K
RES
10 F
PCLK
RDY1 RDY2
VCC
Clock
generator
RES 8284
Rdy VCC
MN/MX
Wait
state M/IO M/IO
generator CLK
INTA INTA
Ready
Reset RD RD
WR WR
8086 ALE STB A0

GND OE A19
AD0-AD15
Addr/Data Latches
A16-A19 (2 or 3)
BHE BHE
DT/R T D0
DEN OE D15
Y7 A0 Y6 Y0 A0 Y1
Transceivers
(2) O0
Y0 O0
Addr Addr OE D8-D15 Addr CS OE D0-D7 Addr CS OE WRD8-D15 Addr CS OE WR D0-D7 Addr CS RD WRD0-D15 CS
Y1 O1
Data Data Data Data Data
Decoder VCC Decoder
EPROM (ODD) EPROM (EVEN) RAM (ODD) RAM (EVEN) I/O
Y6 O6
M/IO EN EN Y7 EN EN O7
Fig. 6.4.6 Minimum mode 8086 system

A1 A 16
A1 A 11 A 0 BHE
BHE A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0
VCC
MN/MX
74LS373(2)
L
AD15 A A0
AD0 T
A15
CLK C
ALE H
D0
8086 VCC D15
74LS138
D G1 MEMR
E
RD A C MEMW
O
WR B D IOR
E
M/IO C R
IOW
G1 G2
CLK Reset Ready A16
OE D8-D15 A1-A11 OE D0-D7 A1-A11 OE D8-D15 A1-A16 WR OE D0-D7 A1-A16 WR
CLOCK 2 K ROM 2 K ROM 128 K RAM 128 K RAM

VCC
8284A CS CS CS CS
ALE
VCC D G1
E
A19 L A C
A18 A B O
T D
A17 C E Y7
A16 C R
H G1 A0 A0
Y1
BHE G2 GND
74LS373 74LS138
Fig. 6.4.7 Interfacing 128 K RAM and 2K ROM with 8086 in minimum mode
VCC LOCAL BUSES
8284 MN/MX GND CLK MRDC MEMORY READ

CLOCK CLK S0 S0
GENERATOR MWTC MEMORY WRITE
READY S1 S1 AMWC ADVANCED MW
RES 8288
RESET S2 S2 BUS IORC I/O READ
RDY CTRLR
DEN IOWC I/O WRITE
8086
GND CPU AIOWC ADVANCED I/O W
DT/R
INTA INTERRUPT
LOCK N.C. ALE
WAIT ACKNOWLEDGE
STATE
GENERATOR
STB
GND OE 1 MEGABYTE
AD0-AD15 ADDRESS BUS
ADDR/DATA 8282
A16-A19 LATCH
(2 OR 3)
BHE
T
OE 16-BIT
8286 DATA BUS
TRANSCEIVER
(2)
Latches
STB 8282s (3)
If there is no
8259A, this is
Clock an inverter
8284A
OE Transceiver
8286 (2)
T
CLK ALE
CEN DEN
+5 V
Control Control
AEN logic signal DT/R
generator
8086/ IOB MCE/PDEN
8088
BUS MRDC
controller
8288 MWTC
Command Control
IQRC bus
S0 signal
S0 generator IOWC
S1 Status
S1 INTA
S2
decoder
S2
INTA
Priority interrupt
controller 8259A
VCC

CLOCK CLK S0 S0
RES 8288
RDY CTRLR
DEN IOWC I/O WRITE
8086
GND CPU DT/R AIOWC ADVANCED I/O W
INTA INTERRUPT
LOCK N.C. ALE
WAIT ACKNOWLEDGE
STATE
GENERATOR
STB
GND OE 1 MEGABYTE
ADDR/DATA 8282
A16-A19 LATCH
(2 OR 3)
BHE
T
OE 16-BIT
8286 DATA BUS
TRANSCEIVER Y7 A0 Y6 Y0 A0 Y1
(2)
Y0
Y1 Y2
Addr Decoder
Y6 OE D8-D15 Addr CS OE D0-D7 Addr CS OE WRD8-D15 Addr CS OE WR D0-D7 Addr CS RD WRD0-D15 CS
EN Y7
Data Data Data Data Data
EPROM (ODD) EPROM (EVEN) RAM (ODD) RAM (EVEN) I/O
RQ GT
One Bus Cycle
T1 T2 T3 T4
CLK
Address, BHE OUT
A19/S6-A16/S3
Status OUT
and BHE/S7
TAVDV
AD15-AD0 Data IN
Address OUT
ALE
M/IO LOW = I/O READ, HIGH = MEMORY READ
RD
TRLDV
DT/R
DEN
One Bus Cycle

T1 T2 T3 T4
CLK
Address, BHE OUT
A19/S6-A16/S3
Status OUT
and BHE/S7
AD15-AD0 Address OUT Data OUT
TDVWH
ALE
M/IO LOW = I/O WRITE, HIGH = MEMORY WRITE
TWLWH
WR
DT/R
DEN
CLK  
HOLD

HLDA
AD15-AD0 Requesting
8086 master 8086
A19/S6, A16/S3
BHE/S7, M/IO
RD, WR, DT/R, DEN
One Bus Cycle
T1 T2 T3 T4
CLK
S2-S0 S2-S0
S2-S0 Inactive
BHE, A19-A16
Address/status Float
S7-S3
AND BHE/S7
Data IN D15-D0
Address/data A15-A0
(AD15-AD0)
TAVDV
* ALE
TRLDV
* MRDC
or IORC
* DT/R
* DEN
One Bus Cycle

T1 T2 T3 T4
CLK
S2-S0
S2-S0
S2-S0 Inactive
BHE, A19-A16
Address/status Float
S7-S3
AND BHE/S7
Address/data A15-A0 Data out D15-D0

(AD15-AD0)
TDVWH
* ALE
TWLWHA
* AMWC
or AIOWC
* MWTC
or IOWC TWLWH
* DEN
* 8288 bus controller
outputs
CLK


RQ/GT
Master requests 8086 grants bus Master releases

bus access to requesting master bus
RQ GT
DEN
R
MX
MN / MX
MX MX
MX
BHE A0
BHE A0
QS1 QS 0
QS 1 QS 0
DEN
DEN
DT R
AMWC
AIOWC
D 0 - D7
Input
port
Data bus (Tri-state buffer) Data from input
device
(Keyboard)
Enable
D 0 - D7
Output
device
Data bus (Latch)
To output device
(Display)
CLK
Start I/O
routine
Get I/O port A

status register
Is
Yes Call the I/O port A
service request
bit set service routine
?
No
Get I/O port B

status register
Is
Yes Call the I/O port B
service request
?
No
Get I/O port C

status register
Is
Yes Call the I/O port C
service request
?
No
End
28
( 2 16 )
Buffer
or To
A0 Data I/O
Latch
A1 bus device
Decoder
A2
OE
A3
A4 G1
A5 G2 M/IO IORC/IOWC
A6
A7 G RD/WR
Y0
74LS138
+5 V
R R R R R R R R = 10 K
74LS244
S0 I0 O0
S1 I1 O1
S2 I2 O2
S3 I3 O3
Tri-state Lower byte
DIP S4 I4 buffer O4 Data bus(D0-D7)
switches of 8086
S5 I5 O5
S6 I6 O6
S7 I7 O7
OE
A0 A
A1 D
B
A2 e
C
A3 c
A4 G1 o
A5 G2 d M/IO
e IOR
A6
A7 G r RD
Y0
74LS138
VCC = +5 V
G VCC
A2 A (MSB) Y0 PORT (E8)
A1 B Y1 PORT (E9)
A0 C (LSB) Y2 PORT (EA)
Y3 PORT (EB)
A7 74138
A6 Y4 PORT (EC)
G2
A5 Y5 PORT (ED)
A3 Y6 PORT (EE)
A4 G1 Y7 PORT (EF)
GND
+5 V
74LS244
S0 I0 O0
S1 I1 O1
S2 I2 O2
S3 I3 O3
Tri-state Lower byte
switches of 8086
S5 I5 O5
S6 I6 O6
S7 I7 O7
OE
+5 V
74LS244
S8 I0 O0
S9 I1 O1
S10 I2 O2
S11 I3 O3
Tri-state Higher byte
switches of 8086
S13 I5 O5
S14 I6 O6
S15 I7 O7
OE
A0 A
A1 D
B
A2 e
C
A3 c
A4 G1 o
A5 G2 d M/IO
e IORC
A6
A7 G r RD
Y0
74LS138
+5 V
L0 L7
330 
A0 A O0
D Lower Byte L
A1 B A
E Data bus (D7-D0)
A2 Y2 T
C C of 8086
C
A3 O
A4 G1 H
D O7
A5 G2 E M/IO LE
A6 R 330 
A7 WR
G IOWC
Decoder select Decoder input
A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 1 0 = 82H
+5 V +5 V
L0 L7 L8 L15
330 
A0 A O0
Lower byte L
A1 D
B Data bus (D7-D0) A
E
A2 T
C C of 8086
Y1 C
A3 O
A4 G1 H
D
A5 E LE O7
G2
A6 R 330 
A7 G
330 
O0
Higher byte L
Data bus (D8-D15) A
T
of 8086 C
H
LE O7
M/IO
WR 330 
IOWC
Decoder select Decoder input

A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 1 0 = 82H
+5 V
74LS244 R R 10 K
D0
B
Lower byte U S0
Data bus of 8086 F
F
E
RD R D7
IORC
S7
OE
+5 V
M/IO
IOWC Y0
L0 L7
WR
A0 A 74LS373
A1 D
B E Y0
A2 330 
C C
L O0
A3 O Y2 A
A4 G1 D
T
A5 G2
E
C
A6 R
H
A7 G O7
330 
LE
Start
Read the switch

status
Is No
S1 = 0
?
Yes
Glow lower Glow higher

nibble LEDs nibble LEDs
CALL Delay CALL Delay
Switch off lower Switch off higher

nibble LEDs nibble LEDs
CALL Delay CALL Delay



+5 V
74LS244 R R 10 K
D0
B
U
Lower Byte F S0
Data bus of 8086 F
E
R
RD IORC D7
S7
OE
+5 V
M/IO
IOWC Y0
WR L0 L7
A0 A 74LS373
A1 D
B E Y0
A3 A2 330 
C C L O0
A4 O Y2 A
G1 T
A5 D C
A6 A7 G E H
R
G2 O7
330 
A8 74LS138 LE
A9
A10
A11
A12
A13
A14
A15
+5 V
R R 10 K
74LS244
D0
B
U
Lower byte F S0
Data bus of 8086 F
E
R
RD D7
MRDC
S7
OE
+5 V
M/IO
MWTC Y0
WR L0 L7
A0 A 74LS373
A1 D
B E Y0
A3 A2 330 
C C L O0
A4 O Y2 A
G1 T
A5 D C
A6 A7 G E H
R
G2 O7
A8 330 
A9 74LS138 LE
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
BHE A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
VCC
MN/MX
74LS373
L
AD15 A A0
AD0 T
A15
C
ALE H
D0
D15
VCC
G1 MEMR
D
RD A E MEMW
C
WR B O
D
IOR
M/IO C E
R IOW
G1 G2
CLK Reset Ready
74LS138
D0-D7 RD WR A1 D8-D15 RD WR A1 D0-D7 RD WR A1 D8-D15 RD WR A1 D0-D7 RD WR A1
CLOCK I/O I/O I/O I/O I/O

8284A Device 1 Device 2 Device 3 Device 4 Device 5
74LS138 CS CS CS CS CS
A2 A
A3 B Y0
C
3:8
A0 A0 A0
A4 Decoder
A5
A6 E1
A7 Y1
A12
A13
A14 E2 Y2
A15
A8
A9
A10 E
A11
BHE LATCH
ALE
A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0
Y0
A4 A0
Y1
A5 A1 0010H
Y2
A6 A2 3:8 0020H
Y3
Decoder 0030H
A0 Y4
74LS138 0040H
Y5
E3
A3 Y6
A7 E1 Y7
A15 E2
M IO M IO
IO M IO M
Interrupt request
I/O
CPU System
Interrupt acknowledgement
Start
Initialize counter
Initialize source pointer
Initialize port address
Get byte
Send byte
No
Last byte ?
Yes
Stop
CPU DMA
Start
Request I/O transfer Acknowledge
Send addresses of
source and destination Request bus
and number of bytes
to transfer
No
Bus free !
Yes
Perform other activities Activate address lines
Perform data transfer
Release bus
Total data
bytes No
transferred
Yes
Notify CPU of
Acknowledge
completion
Stop
Data transmission
Serial Parallel
Synchronous Asynchronous Interrupt driven DMA Programmed I/O

C1-1 C1-2 C1-3 C2-1 C2-2 C2-3
CPU operation 2-1 2-2
1-1 1-2
/O operation
t1 t2
Process 1 Process 1 Time
(a) Uniprogramming approach
C1-1 C1-2 C1-3

CPU operation C2-1 C2-2 C2-3
1-1 1-2
I/O operation 2-1 2-2
Process 2
Process 2
Time
(b) Multi-programming approach
Memory
8086/8088
Processor
Bus
Bus Bus
Clock control System bus
Request Grant
logic
Coprocessor
or
Independent I/O
processor Devices
8086/8088
Set up a task
message
Independent processor
Wake up
independent Command Wait for
processor request
(Start Channel) Channel
Attention
Fetch task
message
(Read task)
Execute
its own
program sequence
Execute
assigned task
Status
or
Wait for IRQ Inform CPU
ready or
of completion
interrupt request
Next task
System System
memory I/O devices
System bus
Module 1 Module 2 Module 3
System bus System bus System bus

control logic control logic control logic
Processor Closely coupled

Local bus Processor Local bus Local bus
(8086/ 8088 multiprocessor
control logic (8086/8088) control logic control logic
and 8087) module
Clock Clock
Local bus Local bus Local bus
Local Local Local Local Local Local

memory I/O devices memory I/O devices memory I/O devices
System bus
Master N Master 2 Master 1
Bus access Bus access Bus access

logic logic logic
Bus grant
Bus request Bus
Control
Bus busy Logic
System bus

logic logic logic Module
address
Bus
Control
Logic
Bus request
Bus busy
System bus

logic logic logic
Bus grant 1
Bus request 1
Bus grant 2
Bus request 2 Bus
Control
Logic
Bus grant N
Bus request N
Bus busy






 
VSS 1 40 VCC
A14/D14 2 39 A15/D15
A13/D13 3 38 A16/S3
A12/D12 4 37 A17/S4
A11/D11 5 36 A18/S5
A10/D10 6 35 A19/S6
A9/D9 7 34 BHE/S7
A8/D8 8 33 RQ/GT1
A7/D7 9 32 INT
A6/D6 10 8087 31 RQ/GT0
A5/D5 11 NDP 30 NC
A4/D4 12 29 NC
A3/D3 13 28 S2
A2/D2 14 27 S1
A1/D1 15 26 S0
A0/D0 16 25 QS0
NC 17 24 QS1
NC 18 23 BUSY
CLK 19 22 READY
VSS 20 21 RESET
NC = NO CONNECT
INT INTR MN/MX
8259A
(Programmable
8086
interrupt S2-S0 (Processor status)
controller) AD15-AD0
RQ/GT A19-A16
IRn
TEST QS1-QS0 BHE 8086/8088
Bus Interface
Components
Multi -Master
(Bus controller, System Bus
Busy Queue status latches and
transreceivers)
Interrupt Bus
Ready, Clock request request/grant
and Reset
8284A
Clock
generator
Coprocessor
(such as 8087)
Ready Reset
8086/8088 Coprocessor
Fetch and Coprocessor read instructions

Decode instruction
Decode instruction
Is Is
Yes MSBs of MSBs of No
Treat instruction Treat instruction
as NOP code byte code byte as NOP
= 11011 = 11011
?
No Yes (i.e. ESC instruction)
Deactivate the
Execute
host's TEST pin and
the 8086
execute the specified
instructions
operation
Activate the
Is TEST pin
No WAIT
instruction 8
08
? or8
86
80
he
upt
ke
Yes Wa
Check
Yes whether No
TEST pin is
activated
Control Unit Numeric Execution Unit
15 0
Control Register Exponent Programmable

module Shifter
Status Register
Exponent Fraction
Bus Bus
Interface
Numeric Execution Floating-point
Unit Instruction Microcode 16 Arithmetic
control Module
unit 68
Data
Data
Buffer 16
64
Temporary
16 Registers
Tag Bits Register

Stack
1 0 79 0
(0)
(1)
(2)
(3)
(4)
Status (5)
(6)
Address
(7)
80 bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Exception flag
B C3 ST C2 C1 C0 IR PE UE OE ZE DE IE (1=exception has occurred)
Invalid operation
Denormalized operand
Zerodivide
Overflow
Underflow
Precision
(reserved)
Interrupt request
Condition code ST values :
000 = register 0 is stack top
Stack top pointer 001 = register 1 is stack top
Conditional code
Busy 111 = register 7 is stack top
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC RC PC IEM PM UM OM ZM DM IM EXCEPTION MASKS
(1=EXCEPTION IS MASKED)
INVALID OPERATION
DENORMALIZED OPERAND
ZERODIVIDE
OVERFLOW
UNDERFLOW
PRECISION
(RESERVED)
(1)
INTERRUPT-ENABLE MASK
PRECISION CONTROL(2)
ROUNDING CONTROL(3)
INFINITY CONTROL(4)
(RESERVED)
(1) Interrupt - Enable mask (3) Rounding control
0 = Interrupts enable 00 = Round to nearest or Even
1 = Interrupts disabled (Masked) 01 = Round down (toward %)
(2) Precision control 10 = Round up (toward %)
00 = 24 bits 11 = Chop (Truncate toward Zero)
01 = (reserved) (4) Infinity control
10 = 53 bits 0 = Projective
11 = 64 bits 1 = Affine
DEFAULT AFTER FINITE
Approximate
Data type Bytes Range (decimal) Format
Word integer 2 –32,768 to 32,767 S Magnitude

15 0
9 9
Short integer 4  –2 x 10 to 2 x 10 S Magnitude
31 0
18 18
Long integer 8  –9 x 10 to 9 x 10 S Magnitude
63 0
18 18
Packed BCD 10 –10 + 1 to 10 –1 S 0 D17 D16 D2 D1
79 78 72 0
–38 38
Short real 4  1 x 10 to ± 3 x 10 S E F
31 30 23 22 0
–308 308
Long real 8   10 to ± 10 S E F
63 62 52 51 0
–4932 4932
Temporary real 10   10 to ± 10 S E F
79 78 64 63 0
sign 2 exp  mantissa







Table (a) Table (c)
Order C3 C0 (ST) C3 C2 C1 C0
(ST) > (SRC) 0 0 + Unnormal 0 0 0 0
(ST) < (SRC) 0 1 + NAN 0 0 0 1
(ST) = (SRC) 1 0 – Unnormal 0 0 1 0
Not comparable 1 1 – NAN 0 0 1 1
+ Normal 0 1 0 0
+ 0 1 0 1
– Normal 0 1 1 0
– 0 1 1 1
+0 1 0 0 0
Empty 1 0 0 1
Table (b) –0 1 0 1 0
Order C3 C0 Empty 1 0 1 1
(ST) > 0 . 0 0 0 + Denormal 1 1 0 0
(ST) < 0 . 0 0 1 Empty 1 1 0 1
(ST) = 0 . 0 1 0 – Denormal 1 1 1 0
Not comparable 1 1 Empty 1 1 1 1
4
4
2x 1
 
  

Programmable Memory
I/O Peripheral Data Data and
Devices Interface (8255) instructions
Command and Data
status
CRT
CPU Controller
Command and (8275)
status
Handshaking
Serial I/O USART
Data
Devices (8251)
DMA
Command and Command and controller
status status
Data
CRT
Data and Controller
Command and
instructions (8275)
Memory status
Data and 8089 Data Programmable

instructions Peripheral I/O
IOP
Command and Interface (8255) Devices
status
Channel attention
CPU
(8086/8088) Data
Interrupt USART Serial I/O
Command and (8251) Devices
status
CPU
/O Channel 1
Main
Channel Control
DMA REQ1 Control
DMA
CCP
Terminate 1
Register
File
ALU Bus Control Status
and Bus
Arbitration
/O Bus Address /
/O Channel 2 Data Bus
Channel
DMA REQ2 Control
DMA Assembly /
Terminate 2 Disassembly
Register
File
nstruction
Fetch Unit
User Programmable Registers
Tag 19 0
G.P. Address A (GA)
G.P. Address B (GB)
G.P. Address C (GC)
Task Pointer (TP)
1- Bit Pointer To Either /O or System Memory Space
15 0
ndex (IX)
Byte Count (BC)
Mask Compare (MC)
Channel Control (CC)
Non User Programmable
19 0
Parameter Pointer (PP)
Channel Control Pointer (CCP)

INT INTR MN/MX
8259A
(Programmable
8086
interrupt S2-S0 (Processor status)
A19-A16
IRn
RQ/GT0 BHE 8086/8088
Bus Interface
Components
Multi -Master
Bus request/grant latches and
transreceivers)
Interrupt
Ready, Clock request
and Reset
8284A
Clock
generator
Independent
Processor
(such as 8089)
Ready Reset
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Selects Data Transfer Mode

B7 Single transfer mode
B15 B14 Data transfer mode
0 No action
0 0 I/O port to I/O port 1 Terminates DMA
0 1 Memory to I/O port after a single cycle.
1 0 I/O port to Memory
1 1 Memory to Memory B8 Changing control
0 No action
B13 Translate Mode 1 Channel in operation
1 Translate Enable gets lower priority.
0 Translate Disable
B9 LOCK control
B12 B11 Synchronization control 0 No action
1 Activates LOCK output
0 0 Unsynchronize transfer begins
of an 8089 during DMA
when bus cycle is available.
transfer cycle.
0 1 Source synchronize transfer;
starts the read operation of the
next transfer cycle after B10 Source/Destination Indicator
receiving the DRQ signal.
1 0 Destination Synchronize 0 Source = GA
transfer : Starts the write Destination = GB
operation of the next transfer 1 Source = GB
cycle after receiving the DRQ Destination = GA
signal.
1 1 Not used.
TERMINATION CONTROL
B6 B5
0 0 No external termination
0 1 Terminates when EXT is high; offset is set to 0
B4 B3
0 0 No termination by byte counter
0 1 Terminates when BC = 0; offset is set to 0
NOTE : Upon B2 B1 B0
termination of a
DMA operation 0 0 0 No termination by mask comparison
the channel 0 0 1 Terminates when comparison matches; offset is set 0
executes 0 1 0 Terminates when comparison matches; offset is set 4
the instruction 0 1 1 Terminates when comparison matches; offset is set 8
whose address 1 0 0 No effect
is the contents 1 0 1 Terminates when there is no match; offset is set 0
of TP plus an 1 1 0 Terminates when there is no match; offset is set 4
offset. 1 1 1 Terminates when there is no match; offset is set 8
Independent
Processor
(such as 8089)
Interrupt
request
Bus request/grant
RQ/GT0
IR0 MN/MX
8259A INT INTR
(Programmable 8086
S2-S0 (Processor status)
interrupt
RQ/GT1 A19-A16
IR1
TEST QS1-QS0 BHE 8086/8088
Bus Interface
Components
Multi -Master
Busy Queue status latches and
transreceivers)
Interrupt Bus
Ready, Clock request request/grant
and Reset
8284A
Clock
generator
Coprocessor
(such as 8087)
Ready Reset
7 07 0
Address SYS Bus
FFFF6H
FFFF8H SCB Address
FFFFAH
SCB Relocation
SOC
System
CB Address Configuration
Block
CB Relocation
BUSY CCW
PB Address Control Block

for
PB Relocation Channel 1
BUSY CCW
PB Address Control Block
for
Parameter PB Relocation Channel 2
Block
TB Address
TB Relocation Task Block
  OP Task 
User Defined
Program
P O B ICF ICF CF CF CF
PARITY ZERO BUS INTERRUPT COMMAND

BIT LOAD CONTROL FIELD
LIMIT FIELD
TM
TECHNICAL PUBLICATIONS - An up thrust for knowledge

PC 3 - PC7
PA3 1 40 PA4
PA2 2 39 PA5
PA1 3 38 PA6
PA0 4 37 PA7
RD 5 36 WR
CS 6 35 RESET
GND 7 34 D0
A1 8 33 D1
9 32
PCU
A0 D2
PC7 10 31 D3
PC6 11 30 D4
8255A
PC5 12 29 D5
PC4 13 28 D6
PC0 14 27 D7
VCC
PC1 15 26
(+5 V)
PC2 16 25 PB7
PC3 17 24 PB6
PB0 18 23 PB5
PB1 19 22 PB4
PB2 20 21 PB3
PCL
GROUP GROUP A PA
A PORT A
POWER +5V CONTROL (8) PA7-PA0
SUPPLIES GND
GROUP A PCU
PORT C
BI-DIRECTIONAL Upper
DATA BUS (4) PC7-PC4
D7-D0 DATA
BUS
BUFFER 8 BIT
INTERNAL GROUP B PCL
DATA BUS PORT C
Lower
(4) PC3-PC0
RD
WR READ/ GROUP GROUP B PB
A0 WRITE
CONTROL B PORT B
A1 LOGIC CONTROL (8) PB7-PB0
RESET
CS
Data Bus
STB
Computer Printer
ACK
BUSY
PC 3 - PC7
D 3 - D1 ( B 2 B1 B 0 )
PC 0 - PC7
D0
0 D6 D5 D4 D3 D2 D1 D0
BIT SET/RESET
1 - SET
0 - RESET
Don't care
BIT SELECT
0 1 2 3 4 5 6 7
0 1 0 1 0 1 0 1 B0
0 0 1 1 0 0 1 1 B1
0 0 0 0 1 1 1 1 B2
BIT SET/RESET FLAG

0 = ACTIVE
PC 3 PC 4

 
D7
D7
1 D6 D5 D4 D3 D2 D1 D0
GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
GROUP A
PORT C (UPPER)
1 = INPUT
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 =MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG

1 = ACTIVE
CL
CU
1 0 0 1 1 0 0 0 = 98H
Port CL - Output
Port B - Output
Mode 0 Port B - Simple I/O
Port CU - input
Port A - Simple input
Mode 0 Port A - Simple I/O
I/O Mode
CL
CU
1 0 1 0 1 1 1 0 = AEH
Port CL - Output
Port B
Mode 1 Port B - Handshake
Port CU
Port A
Mode 1 Port A - Handshake
I/O Mode
0 X X X 0 0 0 1 = 01H
Make bit = 1
Bit 0 of Port C
Don't care
BSR Mode
Control word to make bit 0 low
0 X X X 0 0 0 0 = 00H
Make bit = 0
Bit 0 of Port C
Don't care
BSR Mode
Start
Make PC0 high
Call delay
Make PC0 low
Call delay
End
PC0
PC
1 0 1 1 0 1 0 X = B4 or B5
{
PA PCU Mode PB
Mode PA Input
PB Output
1 0 1 1 0 1 0 = B4H
I/O Port A Port C Mode 1 Port B Port C
Mode Mode 1 Input output Port B output
Port A
D7 D6 D5
D2
D 4 D 3 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
RD
Input
CS, A1, A0
D7-D0 Data
WR
D7-D0
CS, A1, A0
Output
PC 3 , PC 4 PC 5
PC 6 PC 7 D3
PC 3 , PC 6 PC 7
PC 4 PC 5 D3
PC 0 , PC1 PC 2
MODE 1(PORT A)
PA7-PA0 8
Control word
D7 D6 D5 D4 D3 D2 D1 D0 INTE PC4 STBA

A
1 0 1 1 1/0 PC5 IBFA
PC7, PC6
1 = INPUT
0 = OUTPUT
PC3 INTRA
RD 2
PC7-PC6 I/O
STBA
IBFA
INTR
RD
DATA ON
PA0-PA7
INTE A
PC 4
INTE B PC 2
MODE 1(PORT B)
PB7-PB0 8
Control word
D7 D6 D5 D4 D3 D2 D1 D0 INTE PC2 STBB

B
1 1 1 PC1 IBFB
PC0 INTRB
RD
IBFA
INPUT CONFIGURATION
A1 A 0 D7 D6 D5 D4 D3 D2 D1 D0
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
GROUP A GROUP B
MODE 1(PORT A)
PA7-PA0 8
Control word
D7 D6 D5 D4 D3 D2 D1 D0 PC7 OBFA
1 0 1 0 1/0 PC6 ACKA

INTE
A
PC5, PC4
1 = INPUT
0 = OUTPUT
PC3 INTRA
WR 2
PC5-PC4 I/O
WR
OBFA
INTRA
ACKA
DATA
OUTPUT PREVIOUS DATA NEW DATA
ON
PA0-PA7
PC 6
PC 2
MODE 1(PORT B)
PB7-PB0 8
Control word
D7 D6 D5 D4 D3 D2 D1 D0 PC1 OBFB
1 1 0 PC2 ACKB
INTE
B
PC0 INTRB
WR
D7 D6 D5 D4 D3 D2 D1 D0
OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB
GROUP A GROUP B
PC 0 - PC 2
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1/0 1/0 1/0
PC2-PC0
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
GROUP B MODE
0 = MODE 0
1 = MODE 1
PC 6
PC3 INTRA
PA7-PA0 8
PC 4
PC7 OBFA
INTE
PC6 ACKA
1
INTE PC4 STBA

2
PC5 IBFA
WR
3
RD PC2-PC0 I/O
PC 3
D7 D3 OBF A INTE 1 , IBFA , INTE 2 ,

INTR A
D2 D0
D2 D0 PC 2 PC 0
D2 D0
D7 D6 D5 D4 D3 D2 D1 D0
OBFA INTE1 IBFA INTE2 INTRA
GROUP A GROUP B
(DEFINED BY MODE 0
OR MODE 1 SELECTION)
Data from
CPU to 8255A
WR
tAOB
OBF
tWOB
INTR
tAK
ACK
tST
STB
tSIB
IBF
tPS
tAD tKD
Peripheral
bus
tPH tRBI
RD
Data from Data from
peripheral to 8255A 8255A to peripheral
Data from
8255A to 8080
28
( 2 16 )
PC 3 PC 0
D0 D0
D7 PA0
D7
A1 A0 PA7
A2 A1
PB0
M/IO
RD RD PB7
A0 PC0
8255
WR
WR PC7
A7 Reset
Reset CS
A6
A5
A4
A3
D0 D0
D7 D7 PA0 - PA7
A1 A0
PB0 - PB7
M/O A2 A1
RD RD 8255
PC0 - PC7
BHE
WR
WR
Reset out Reset
A15
CS
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A 0 -A 1
D0 D0
D7 PA0
D7
A1 A0 PA7
A2 A1
PB0
M/IO
RD RD PB7
A0 PC0
8255
A19 WR
WR PC7
A18 Reset
A17 Reset Out CS
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
VCC

CLOCK CLK S0 S0
RES 8288
RDY CTRLR
DEN IOWC I/O WRITE
8086
GND CPU AIOWC ADVANCED I/O W
DT/R
INTA INTERRUPT
LOCK N.C. ALE
WAIT ACKNOWLEDGE
STATE
GENERATOR
STB
GND OE 1 MEGABYTE
ADDR/DATA 8282
A16-A19 LATCH
(2 OR 3)
BHE
T
OE 16-BIT
8286 DATA BUS
TRANSCEIVER
(2) A2 A1
8
Y0
Y1
Reset A1 A0 RD WR D0 – D7
Addr Decoder
Y6 8255
EN Y7
PA0-PA7 PB0-PB7 CS PC0-PC7

VCC
2.5 K
AD0 AD0 13 14 Vref
PA0
A8
AD7 AD7 2.5 K
A1 2.5 K
PA7
IOR RD
8 0
IOW WR
2 8 4
–
5 0 Io
From Reset Reset 8 +
5
8086 out 2.5 K +
15 Vo
A1 A0
(1408)
A2 A1 –
CS
16 3 1 2
15 pF
VEE
A3
A4
A5
A6
A7
T = 10 ms
2.5 V
5 ms
0V
s –2.5 V
5 ms 5 ms
1
0.2 s
5  10 6
5.8 s
s s s 



s

5 ms
8 s

AD0
D0
AD7 Vref
D7 8 D0
PA Rf
D7
IOR RD
PCL D8
4 D11 DAC
IOW WR 8255 IOUT –
Reset Reset +
A0 A0 + Vout
–
A1 A1
From
CS
address
decoder
5 ms
s
585
1
 s
5 MHz
8.547 s

0.2 s
+2.5 V
0V 180º 360º
90º t
FFH
80H
96H
ABH
COH FEH
D2H
–2.5 V
E2H
EFH
F8H
   

 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

3 1 28 2
Analog
4 2 27 1 inputs
Analog
inputs 5 3 26 0
6 4 25 A
7 5 24 B Address
SOC 6 23 C
EOC 7 ADC 22 ALE
0808/
DB3 8 0809 21 DB7
OUTPUT CONTROL 9 20 DB6
CLK 10 19 DB5
VCC 11 18 DB4
REF + 12 17 DB0
GND 13 16 REF
DB1 14 15 DB2
A
B Address
C 50 ns
ALE
25 s
SOC
EOC
DB0
Valid data
DB7
OE
VCC
+VREF
DB0 IN0
DB1 IN1
DB2 IN2
Input DB3 IN3 Analog
DB4 A IN4 inputs 1K
Port
DB5 D IN5
DB6 C IN6
DB7 0 IN7
EOC 8
0 CLK
8 +5 V
A 0.01 F
B Output
OUTPUT enable 7414
C
PORT VCC
SOC
ALE +REF 12 V
–REF GND
2K
+
LM308 2K 6.8 V
+ 10 mF –
1f solid
– Tantalum
10 K
Vin
Resolution
6.000

40  10 3
6 .035
 
40  10 3
(TC ) max 
1 ( 255)

f 2 . 5  10 6
(TC ) max
(TC ) average
2
Start (Start of conversion)
Clock 1 2 3 4 5 6 7 8
1
B8
B7 0
1
B6
1
B5
1
B4
B3 0
1
B2
1
B1
10
256
       
  
R 1
Y 1
G 1
W E
R Y G R Y G
3 3 3 4 4 4
R 2
Y 2
S G 2
+12 V
Free
wheeling
diode 230 V AC
50 Hz
5.1 K
AD0 PA0 BC 547
D0
AD7 D7 PA1
PA2
PA3
A0 A0
PA4
A1 A1 PA5
PB0 +12 V
IOR RD
PB1
Free
IOW WR PB2 wheeling
PB3 diode
RESET OUT RESET PB4
OF 8085/8086 5.1 K
PB5 BC547
CS
8255
A2 A
A3 B
A4 C Y0
A5 G1
A6 G2
A7 G 74LS138
MODE A
P
p
OBF
OBF
0 X X X 0 0 0 1 = 01H
BSR Mode PC0 Set
0 X X X 1 0 0 0 = 08H
BSR Mode PC4 Reset
D3 - D1 ( B 2 B1 B 0 )
PC 0 - PC7
D0
Vref
2n
TM

Always high
Marking
Start
Transmitter D0 D1 D2 D3 D4 D5 D6 D7 Stop Receiver

bits
ASCII
CLK characters CLK
Time
Always low
1 Stop bit
Start bit
Mark
1 1 0 0 1 0 1 0
Transmitter Receiver
1 Frame
Time
11
2
Clock
Sync Sync
Transmitter Receiver
Data
Start Time
D2 D1
D3 D0
RxD VCC
GND RxC
D4 DTR
D5 RTS
D6 DSR
8251 A
D7 RESET
TxD CLK
WR TxD
CS TxEmpty
C/D CTS
RD SYN DET / BD
RxRDY Tx RDY
Data Transmit
D7-D0 bus buffer TxD
buffer (P-S)
RESET
CLK Read/Write
C/D control TxRDY
RD
Transmit
logic TxE
control
WR TxC
CS
DSR Receive
DTR Modem buffer RxD
CTS control (S-P)
RTS
Internal RRDY
data bus Receive
control RxC
SYNDET
1
2
D7 D6 D5 D4 D3 D2 D1 D0
Baud rate factor
00 SYN mode
01 ASYN1
10 ASYN16
11 ASYN64
Character length
00 5 bits
ASYN (D1D0 = 00) 01 6 bits
10 7 bits
11 8 bits
Framing control Parity control

00 Not valid X0 No parity
01 1 stop bit 01 Odd parity
10 11 2 stop bits 11 Even parity
11 2 stop bits

D7 D6 D5 D4 D3 D2 D1 D0
EH IR RTS ER SBRK RxE DTR TxEN
Enable hunt mode* Transmit enable

1 = Enable search for 1 = Enable
sync characters 0 = Disable
Internal reset
Data terminal ready
1 = Resets
1 = Enable DTR
8251 to mode
Receive enable
Request to send
1 = Enable
1 = Enable RTS
0 = Disable
Error Reset Send break character

1 = Reset error flags 1 = Forces TxD "Low"
PE.OE.FE 0 = Normal operation
*(Has no effect in Async mode)
Note : Error reset must be performed whenever
Rx enable and enter hunt are programmed
D7 D6 D5 D4 D3 D2 D1 D0
SYNDET/
DSR FE OE PE TEMPTY RRDY TRDY
BRKDET
Note 1
Same definitions as I/O pins
Parity error
The PE flag is set when a parity error is
detected. It is reset by the ER bit of the
command instruction. PE does not inhibit
operation of the 8251A.
Overrun error
The OE flag is set when the CPU does
not read a character before the next one
becomes available. It is reset by the ER
bit of the command instruction.OE does
not inhibit operation of the 8251 A. However,
the previously overrun character is lost.
Framing error (Async only)

The FE flag is set when a valid stop bit is not
detected at the end of every character.It is
reset by the ER bit of the command instruc-
tion.FE does not inhibit the operation of the
8251A
Data set ready

Indicates that the DSR is at a zero level.
TxD Marking Start Parity Stop
Data bits bit(s)
bit bit
1 1
16 64
Start Parity Stop
RxD Data bits
bit bit bits
TxD Data Data SYNC1 SYNC2 Data
TxEMPTY
D0 D0-D7
D7 TxD
Reset out Reset RxD
Clock out CLK
M/IO
RD RD
A0
8251A
WR
WR
A2 RxC From pulse

A1 C/D generator or
A3 TxC timer
A4
CS
A5
A6
A7 CTS GND
D0-D7
TxD
Reset out Reset RxD
Clock out CLK
M/IO
RD RD
A0
8251A
WR
WR
A2 RxC From pulse

A1 C/D generator or
TxC timer
CS
A19 CTS GND
DSR DTR
TxD Marking Start Parity Stop
Data bits bit(s)
bit bit
TM

D7 1 24 VCC
D6 2 23 WR
D5 3 22 RD
D4 4 21 CS
D3 5 20 A1
D2 6 19 A0
8254
D1 7 18 CLK2
D0 8 17 OUT 2
CLK0 9 16 GATE 2
OUT0 10 15 CLK1
GATE 0 11 14 OUT 1
GND 12 13 GATE 1
CLK0
D7 Data Counter
8 bus GATE0
D0 buffer 0
OUT0
RD CLK1
Read/ Counter
WR
write GATE1
A0 logic 1
A1 OUT1
CS
CLK2
Control Counter
word GATE2
register 2
OUT2
Internal bus
A0
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
SC - Select counter M - Mode

SC1 SC0 M2 M1 M0
0 0 Select counter 0 0 0 0 Mode 0

0 1 Select counter 1 0 0 1 Mode 1
1 0 Select counter 2  1 0 Mode 2
Illegal for 8253
 1 1 Mode 3
1 1 Read -Back command for 8254
(See Read operations) 1 0 0 Mode 4
1 0 1 Mode 5
RW - Read /Write
RW1 RW0
Counter latch command BCD :

0 0
(See Read operations)
0 1 Read / Write least significant byte only 0 Binary counter 16 - bits
1 0 Read / Write most significant byte only 1 Binary coded decimal (BCD)
Counter (4 Decades)
Read / write least significant byte first,
1 1 then most significant byte
Note : Don't care bits () should be 0 to ensure compatibility with future Intel products
CW = 10 LSB = 4 (a) Normal operation
WR
CLK
GATE
OUT
0 0 0 0 0 FF FF
N N N N
4 3 2 1 0 FF FE
CW = 10 LSB = 3 (b) Gate disable
WR
CLK
GATE
OUT
0 0 0 0 0 0 FF
N N N N
3 2 2 2 1 0 FF
CW = 10 LSB = 3 LSB = 2 (c) New count
WR
CLK
GATE
OUT
0 0 0 0 0 0 FF
N N N N
3 2 1 2 1 0 FF

WR
CLK
GATE
OUT
0 0 0 0 FF 0 0
N N N N N
3 2 1 0 FF 3 2
CW = 12 LSB = 2 (b) Retriggering
WR
CLK
GATE
OUT
0 0 0 0 0 0 0
N N N N N
3 2 1 3 2 1 0
WR
CLK
GATE
OUT
0 0 0 FF FF 0 0
N N N N N
2 1 0 FF FE 4 3
WR
CLK
GATE
OUT
0 0 0 0 0 0 0
N N N N
3 2 1 3 2 1 3
CW = 14 LSB = 3 (b) Gate disable
WR
CLK
GATE
OUT
0 0 0 0 0 0 0
N N N N
3 2 2 3 2 1 3
WR
CLK
GATE
OUT
0 0 0 0 0 0 0
N N N N
4 3 2 1 5 4 3
Note : A GATE transition should not occur one clock prior to terminal count.
CW = 16 LSB = 4 (a) Even count
WR
CLK
GATE
OUT
0 0 0 0 0 0 0 0 0 0
N N N N
4 2 4 2 4 2 4 2 4 2
CW = 16 LSB = 5 (b) Odd count
WR
CLK
GATE
OUT
0 0 0 0 0 0 0 0 0 0
N N N N
4 2 0 4 2 4 2 0 4 2
CW = 16 LSB = 4 (c) Gate disable
WR
CLK
GATE
OUT
0 0 0 0 0 0 0 0 0 0
N N N N 2
4 2 4 2 2 2 4 4 2
Note : A GATE transition should not occur one clock prior to terminal count.
WR
CLK
GATE
OUT
0 0 0 0 FF FF FF
N N N N
3 2 1 0 FF FE FD
CW = 18 LSB = 3 (b) Gate disabled
WR
CLK
GATE
OUT
0 0 0 0 0 0 FF
N N N N
3 3 3 2 1 0 FF
WR
CLK
GATE
OUT
0 0 0 0 0 0 FF
N N N N
3 2 1 2 1 0 FF
CW = 1A LSB = 3 Normal operation
WR
CLK
GATE
OUT
0 0 0 0 FF 0
N N N N N
3 2 1 0 FF 3
CW = 1A LSB = 3 Retriggering
WR
CLK
GATE
OUT
0 0 0 0 0 0 FF
N N N N N N
3 2 3 2 1 0 FF
CW = 1A LSB = 3 LSB = 5 New count
WR
CLK
GATE
OUT
0 0 0 0 FF FF 0 0
N N N N N
3 2 1 0 FF FE 5 4
1 MHz
1 kHz
1  10 3
1 1 . 5  10 6
A0
A15
A2 A1
D0
D15
M/IO
IOR
RD
A0
IOW
WR
D7 - D0 A1 A0 RD WR
CS 8253
Gate0 Clk0 Out0
Output
square wave
+5 V
74LS138 1.5 MHZ
Clock
A7 A D generator
A6 B E
C
A5 C O
D Y1
A4 G1
A3 E
G2 R
D0 D0 CLK0
GATE0
D7 D7 OUT0
A1 A0
A2 A1 CLK1
GATE1
M/IO
RD OUT1
RD
IOR
A0
CLK2
WR
WR IOW GATE2
8253/54 OUT 2
A3
A4
A5 CS
A6
A7
D0 D0 CLK0
GATE0
D7 D7 OUT0
A1 A0
A2 A1 CLK1
GATE1
M/IO
RD OUT1
RD
A0 IOR
WR CLK2
WR IOW GATE2
8253/54
OUT2
A3
A4
A5
A6
A7
A8
A9 CS
A10
A11
A12
A13
A14
A15
RD WR IO
A 1 -A 2
A 3 - A 19
D0 D0 CLK0
GATE0
D7 D7 OUT0
A0 A0
A1 A1 CLK1
GATE1
RD OUT1
RD
A0 M/IO
WR CLK2
WR GATE2
8253/54
OUT2
CS
A3 A4 A5 A6 A7 A8 A9A
10 A11 A12 A13 A14 A15 A16 A17A18 A19
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A0
A15
A2 A1 A2 A1
D0
D7
M/IO
RD IOR
A0
IOW
WR
Reset out
D7 D0 A1 A0 RD WR D7 D0 A1 A0 RD WR Reset
CS 8253 / 54 PC0 8255 CS
G2 G1 G0 PA7 PA4 PA3 PA0 PB7 PB4 PB3 PB0

C2 C0
O2 O0
O1
VCC
VCC
A3 A Y0
A4 B
3:8 CLK1
A5 C 10 kHz
Decoder Y1
A6 G1 R
A7 G2 CLK
generator
230 V Alarm
AC
Required period
Clock period
1 sec
1  10 4
100s

TM

+ VCC
IRQ RL2 1 40 VCC

RL0 -7 8 RL3 2 39 RL1
DATA Key CLK 3 38 RL0

8
BUS data
SHIFT IRQ 4 37 CNTL/STB
CNTL/ RL4 5 36 SHIFT

STB
CPU Interface
RD RL5 6 35 SL3
WR 8 RL6 7 34 SL2
2 SL0 -3 4 Scan
RL7 8 33 SL1
7
CS 9 RESET 9 32 SL0
A0 OUT A0-3 4 RD 10 31 OUT B0

8279
WR 11 30 OUT B1
RESET DB0 12 29 OUT B2

OUT B0-3 4
Display
DB1 13 28 OUT B3
CLK
data
DB2 14 27 OUT A0
DB3 15 26 OUT A1
BD DB4 16 25 OUT A2
DB5 17 24 OUT A3
VSS DB6 18 23 BD
DB7 19 22 CS
Vss 20 21 A0
(a) Functional pin diagram (b) Pin diagram

DB0-DB7
WR A0 IRQ
RD CS
RESET Data I/O FIFO/sensor

Buffers control RAM status
CLK
Internal data bus (8)
Display 16  8 Control and 88 Keyboard

address display timing FIFO / sensor debounce
registers RAM registers RAM and control
Display Timing
registers and
control Scan counter Return
8
Shift
-
OUT A0 A3 OUT B0 B3 - BD SL0-SL3 RL0-RL7 CNTL/ STB
SC 3 - SC 0 
SC 3 - SC 0 
8 4
RL 7 - RL 0 
88
16  8
SL 2 - SL 0 
88
(28 )

SC 3 – SC 0 
8 4
(27 )
88
8 4
8 8
A0
WR
8 4
8 4
8 4
External clock
100 kHz
2  10 6
10100 2
100  10 3
 00110100 2
B4
B4 B4
B4 B4
B3 B0
CD2 CD1 CD0

(CD 0 - CD 1 )
CD1 CD0
CD 2
CD 1 CD 2
CD2 CD1 CD0
CD2 CD1 CD0

B7 B6 B5 B4 B3 B2 B1 B0
DU S/E O U F N N N
Indicates number
of characters in FIFO
FIFO full
Error under run
Error overrun
Sensor closure / Error flag for multiple closures
Display unavailable
D0 D0 SHIFT
D7 D7
CNTL
A1 A0 RL0 Return lines
RL7
IOR RD 8
2 BD Blank display
IOW WR 7
S0
9 Scan lines
S3
RESET RESET
A0
CLOCK CLK A3
Display
To 8086 Interrupt B0 lines
INT
B3
CS
A15
A2
A19
A18
A17
A16
D0 D0 SHIFT
A15 D7 D7
CNTL
A14 A1 A0 RL0
RL7 Return lines
A13
MEMR RD
8 BD Blank display
A12 2
MEMW WR 7
A11 S0
9 S3 Scan lines
RESET RESET
A10
A0
CLOCK CLK A3
A9 Display
To 8086 Interrupt B0 lines
A8 INT
B3
CS
A7
A6
A5
A4
A3
A2
Microprocessors and Microcontrollers 12 - 23 Keyboard / Display Controller - 8279
12.8 Application AU : May-10, 17, Dec.-12
In this section we will discuss many useful applications with different modes of
keyboard and display interfacing. In addition to this we are going to see the software
requirement to control the interfacing circuits. All these applications are illustrated using
different examples.
Program 1 : Hardware and software for 8  8 keyboard interface using 8279.
Program Statement : Interface an 8  8 matrix keyboard to 8086 through 8279 in 2-key

lockout mode and write an assembly language program to read keycode of the pressed
key. The external clock frequency is 2 MHz. Use I/O mapped I/O technique.
Solution : The 8  8 matrix keyboard can be interfaced to 8086 through 8279 in two ways.
1. Without interrupt signal
2. With interrupt signal (Interrupt driven Input)
We will see both the ways one by one.
1. Without Interrupt Signal
Hardware : Fig. 12.8.1 shows the interfacing of 8  8 matrix keyboard.
Scan lines
D0 D0 RL0
D7 D7
RL1
RL2
A1 A0
Return lines
RL3
IOR RD
RL4
IOW WR
RL5
RESET OUT RESET
RL6
CLK OUT CLK
RL7
Y0
8279
S0
S1 3:8
Decoder
S2
INT S3
Y7
A7
SHIFT
A6
CNTL
A5 CS
A4
A3
A2
Fig. 12.8.1 Interfacing of 8  8 matrix keyboard
®
I/O Map
Address lines
Data/Control Register Address
A7 A6 A5 A4 A3 A2 A1 A0
Data Register 1 0 0 0 0 0 0 0 80H
Control Register 1 0 0 0 0 0 1 0 82H
Software :
Step 1 : Find keyboard/display command word. To interface 8  8 matrix keyboard

we need 8 scan lines and 8 return lines. To get 8 scan lines. We have to select encoded
scan keyboard mode. Therefore, the keyboard/display command word for above
keyboard configuration is given as follows :
0 0 0 D D K K K
0 0 0 X X 0 0 0 = 00H
Note : 000  Encoded scan keyboard - 2 key lockout

X  Don’t care
Step 2 : Find program clock command word.

External clock frequency is 2 MHz.
2 MHz
 Prescaler value =
100 kHz
= 20 = 10100 2
Therefore, the program clock command word is as given below :

P P P P P
0 0 1 1 0 1 0 0 = 34H
Step 3 : Find Read FIFO/sensor RAM command word we want to read first entry
from the FIFO RAM. Therefore command word is as given below.
AI A A A
0 1 0 0 X 0 0 0 = 40H
®
Flowchart :
Start
Initialize keyboard /
display mode of 8279
Initialize prescaler
count
Read FIFO status

word
Is
no. of
Yes characters
in FIFO = 0
?
No
Read FIFO RAM
End
Program :
MOV AL, 00H
OUT 81H, AL ; Initialize keyboard/display
; in encoded scan keyboard-2 keylockout mode
MOV AL, 34H
OUT 81H, AL ; Initialize prescaler count
BACK : IN AL, 81H ; Read FIFO status word
AND AL, 07H ; Mask bit B3 to B7
JZ BACK ; If 0, key is not pressed wait for key
; press otherwise read FIFO RAM
MOV AL, 40H ; Initialize 8279 in read
OUT 81H, AL ; FIFO RAM mode
IN AL, 80H ; Read FIFO RAM (keycode)
2. With Interrupt Signal
Hardware :
Fig. 12.8.2 shows the interfacing of 8  8 matrix keyboard in interrupt driven keyboard
mode.
In the interrupt driven mode interrupt line from 8279 is connected to the INTR the
interrupt input of 8086.
®
D0 D0 RL0
D7 D7
RL1
RL2
A1 A0
RL3
IOR RD
RL4
IOW WR
RL5
RESET OUT RESET
RL6
CLK OUT CLK
RL7
To RST 7.5 INT 8279
S0 A
A7
S1 B
A6 S2 C
3:8
A5 Decoder
A4 CS
A3
A2
Fig. 12.8.2 Interfacing of 8  8 matrix keyboard in interrupt driven keyboard mode
Software : All the command words required to initialize 8279 are same as in the non
interrupt mode
Flowchart :
Start Start
Initialize keyboard / Initialize FIFO RAM

display mode of 8279
Enable interrupt
Initialize prescaler count
Return
Enable interrupt
Wait for the interrupt
Fig. 12.8.3
®
Main Program
MOV AL, 00H
OUT 82H, AL ; Initialize keyboard/display in encoded
; scan keyboard 2 key lockout mode
MOV AL, 34H
HERE : JMP HERE ; Wait for the interrupt
Interrupt Subroutine
MOV AL, 40H ; Initialize 8279 in read FIFO
OUT 82H, AL ; RAM mode
RET ; Return to main program
In the interrupt driven keyboard, when key is pressed, key code is loaded into FIFO
RAM and interrupt is generated. This interrupt signal is used to tell CPU that there is a
keycode in the FIFO RAM. CPU then initiates read command with in the interrupt
service routine to read keycode from the FIFO RAM.
Program 2 : Hardware and software to interface 8  4 matrix keyboard using 8279
Program Statement : Interface an 8  4 matrix keyboard to 8086 through 8279.
Solution : Fig. 12.8.4 shows interfacing of an 8  4 matrix keyboard to 8086 through 8279.
As keyboard is having 8 rows and 4 columns, only 4 scan lines are required and we can
avoid external decoder to generate scan lines by selecting decoded scan keyboard mode.
D0 D0 RL0
D7 D7
RL1
RL2
A1 A0
RL3
IOR RD
RL4
IOW WR 8279
RL5
RESET OUT RESET
RL6
CLK OUT CLK
RL7
To RST 7.5 INT S0
S1
S2
S3
A7
SHIFT
A6
CNTL
A5 CS
A4
A3
A2
Fig. 12.8.4 Interfacing 8  4 keyboard matrix in decoded scan keyboard mode
®
Main Program
MOV AL, 00H
OUT 82H, AL ; Initialize keyboard/display in encoded
; scan keyboard 2 key lockout mode
MOV AL, 34H
HERE : JMP HERE ; Wait for the interrupt
Interrupt Subroutine
MOV AL, 40H ; Initialize 8279 in read FIFO
RET ; Return to main program
Program 3 : Hardware and software to interface eight 7-segment digits using 8279
Program Statement : Interface 8/7-segment digits (common cathode) to 8086 through

8279 and write an 8086 assembly language program to display 1 to 8 on the eight seven
segment digits. External clock frequency is 3 MHz.
Solution : Fig. 12.8.5 shows the interfacing of eight 7-segment digits to 8086 through 8279.
(Refer Fig. 12.8.5 on next page)
As shown in the Fig. 12.8.5, eight display lines (B 0 - B 3 and A 0 -A 3 ) are buffered with
the help of transistor and used to drive display digits. These buffered lines are
connected in parallel to all display digits. S 0 , S1 and S 2 lines are decoded and decoded
lines are used for selection of one of the eight digits.
Software : To display 1 to 8 numbers on the eight 7-segment digits we have to load

7-segment codes for 1 to 8 numbers in the corresponding display locations.
Number h g f e d c b a Code
1 0 0 0 0 0 1 1 0 06
2 0 1 0 1 1 0 1 1 5B
3 0 1 0 0 1 1 1 1 4F
4 0 1 1 0 0 1 1 0 66
5 0 1 1 0 1 1 0 1 6D
6 0 1 1 1 1 1 0 1 7D
7 0 0 0 0 0 1 1 1 07
8 0 1 1 1 1 1 1 1 7F
Table 12.8.1 7-Segment codes for common cathode display
®
h
a
Y0
Y7
+VCC
B 74138
G2
G
+VCC
+VCC
VCC
G1
C
A
S0
S1
S2
B0
A3
8279
CS
RESET
CLK
WR
INT
RD
A0
D0
D7
A1
CLK OUT
RESET OUT
IOR
IOW
D0
D7
A7
A6
A5
A4
A3
A2
Fig. 12.8.5
Step 1 : Find keyboard/display command word. To interface 8 digit 7 segment display

we need 8/8-bit character display mode with left entry. For selection of 8 digits we need
encoded scan mode. Therefore, the keyboard/display command word is as given below.
®
D D K K K
0 0 0 0 0 0 0 0 = 00H
Step 2 : Find program clock command word. External clock frequency is 3 MHz.
3 MHz
 Prescaler value = = 30 = 11110 2
100 MHz
Therefore, the program clock command word is as given below.
P P P P P
0 0 1 1 1 1 1 0 = 3EH
Step 3 : Find write display RAM command word. We want to write first eight
locations of display RAM with corresponding 7 segment codes. So we start from first
location with autoincrement mode by command word given below.
AI A3 A2 A1 A0
1 0 0 1 0 0 0 0 = 90H
Flowchart :
Start
Initialize lookup table

pointer and counter
Initialize Keyboard /
Display mode of 8279
Initialize prescaler count
Initialize 8279 in display

RAM write mode
Get 7 segment code
Write 7 segment code

in the Display RAM
Increment lookup table

pointer
Decrement counter
No Is
counter = 0
?
Yes
End
Fig. 12.8.6
®
Program :
MOV SI, LOOK_UP_TABLE ; Initialize lookup table pointer
MOV CL, 08H ; Initialize counter
MOV AL, 00H ; Initialize keyboard/display
OUT 82H, AL ; Mode
MOV AL, 3EH ; Initialize prescaler count
OUT 82H, AL
MOV AL, 90H ; Initialize 8279 in write Display
BACK : MOV AL, [SI] ; Get the 7-segment code
OUT 80H, AL ; Write 7-segment code in display RAM
INC SI ; Increment lookup table pointer
DCR CL ; Decrement counter
JNZ BACK ; if count = 0 stop otherwise go to back
LOOK_UP-TABLE dB 66H, 5BH, 4FH, 66H, 6DH, 7DH, 07H, 7FH
Example 12.8.1 Interface 4  4 matrix keyboard and 6 displays to the 8086 system using
8279 IC. Write an initialization program for encoded key scan and left entry for display.
PU : May-06
Solution : Refer Fig. 12.8.7 on next page.
Software : Find keyboard/display command word.

D D K K K
X X X 0 0 0 0 0 = 00H
Fig. 12.8.8
DD = 00 : 8, 8-bit character display - left entry

KKK = 000 : Encoded scan keybord - 2 key lockout
MOV AL, 00H ; [Initialize 8279 for encoded
OUT 81H, AL ; keyscan and left entry for display]
Review Questions
1. Explain how to interface the hex key pad and 7-segment LEDs using 8279.
AU : May-10, Marks 16
2. How do you interface a keyboard and the display using keyboard / display controller ?
AU : Dec.-12, Marks 8
3. Develop a 8086 based system to display in the word HELLO for every 2 ms in the common
cathode seven segment. LED display and check how many times the work displayed for one hour.
AU : May-17, Dec.-17, Marks 15
®
+ VCC
D0 D0 B0
D7 D7
A3
A1 A0
Microprocessors and Microcontrollers
IOR RD
IOW WR
0
RESETOUT RESET S0 1
S1 3:8 2
TECHNICAL PUBLICATIONS
8279 Decoder 3
CLK OUT CLK
®
12 - 32
S2 4
Fig. 12.8.7
5
INTR INT
A7
RL0
A6 RL1
A5 RL2
CS
RL3
- An up thrust for knowledge

A4
44 Keyboard matrix

A3 SHFT CNTL GND
A2
Keyboard / Display Controller - 8279
Two Marks Questions with Answers
Q.1 Define scan counter.
Ans. : The scan counter has two modes to scan the key matrix and refresh the display.
In the encoded mode, the counter provides binary count that is to be externally
decoded to provide the scan lines for keyboard and display. In the decoded scan mode,
the counter internally decodes the least significant 2 bits and provides a decoded 1 out
of 4 scan on SL0-SL3. The keyboard and display both are in the same mode at a time.
Q.2 What is the output modes used in 8279 ?
Ans. : 8279 provides two output modes for selecting the display options.
1. Display scan : In this mode, 8279 provides 8 or 16 character-multiplexed displays

those can be organized as dual 4-bit or single 8-bit display units.
2. Display entry : 8279 allows options for data entry on the displays. The display
data is entered for display from the right side or from the left side.
Q.3 What are the modes used in keyboard modes ?
Ans. : 1. Scanned keyboard mode with 2 Key lockout. 2. Scanned keyboard with N-key
rollover. 3. Scanned keyboard special error mode. 4. Sensor matrix mode.
Q.4 What are the modes used in display modes ?
Ans. : 1. Left entry mode : In the left entry mode, the data is entered from the left
side of the display unit.
2. Right entry mode : In the right entry mode, the first entry to be displayed
is entered on the rightmost display.
Q.5 What is 8279 ?
Ans. : The 8279 is a programmable keyboard/display interface.

Q.6 List the major components of the keyboard/display interface.
Ans. : a. Keyboard section b. Scan section c. Display section d. CPU interface section
Q.7 What is key bouncing ? AU : June-06, 08, 16
Ans. : Mechanical switches are used as keys in most of the keyboards. When a key is
pressed the contact bounce back and forth and settle down only after a small time
delay (about 10 ms). Even though a key is actuated once, it will appear to have been
actuated several times. This problem is called key bouncing.
Q.8 How much current is needed to drive an LED ? Draw a typical driver circuit for
it. AU : May-05
Ans. : Around 15 mA current is needed to drive LED. The typical driver circuit for
LED is shown in Fig. 12.1.
®
+ VCC
LED
R
RB
Port pin
Fig. 12.1
Q.9 How keyboard debouncing is done by software ? AU : Dec.-07

Ans. : In the software technique, when a key press is found, the microprocessor waits
for at least 10 ms before it accepts the key as an input. This 10 ms period is sufficient
to settle key at steady state. In this way key debouncing is done by software.
Q.10 What is the difference between two key lockout and N-key rollover modes in
8279 ? AU : May-05, Dec.-10
Ans. : 2-key lockout : In this mode, simultaneous key depression is not allowed.
N-key rollover : In N-key rollover, each key depression is treated independently
from all others.
Q.11 List the functions performed by 8279. AU : Dec.-06
Ans. : The functions performed by 8279 are :
1. It independently keeps display refresh with its multiplexed display interface in
right entry mode or left entry mode.
2. It scans the matrix keyboard upto 64 keys with three input modes : scanned
keyboard mode, scanned sensor matrix mode and stored input mode.
Q.12 What is the internal operating frequency of 8279 ? How can you derive it from
any available clock signal ? AU : May-07
Ans. : The internal operating frequency of 8279 is 100 kHz. We can derive the internal
operating frequency from any available clock signal using internal prescaler.
This prescaler divides the external clock by a programmable integer value given in
the program clock command word, to generate internal frequency.
Q.13 Describe the three major tasks needed to get meaningful information from
matrix keyboard. AU : May-08
Ans. : 1. Initialize keyboard in proper mode.
2. Initialize prescaler count.
3. Read keyboard entry from FIFO RAM.
®
Q.14 What is the necessity for a separate 8279 keyboard display controller ?
Ans. : In software approach, to drive multiplexed displays CPU has to look after digit
selection in synchronism with the data for specific digit and these displays need
continuous refreshing. This puts a lot of burden on the CPU. In keyboard interface to
provide facilities such as 2-key lockout, N-key Rollover CPU needs to execute necessary
programs which further increases the burden on CPU and hence it is necessary to have
separate 8279 keyboard/display controller.
Q.15 How a keyboard matrix is formed in keyboard interface using 8279 ?
(Refer section 12.8)
Q.16 What is the function of scan section in 8279 programmable keyboard/display
controller ? (Refer section 12.5.1) AU : May-11
qqq
®
Notes
®
TM

IR0
AD0 D0
IR1
AD7 D7
IR2
IR3
8086 8259
IR4
INTA INTA IR5
IR6
INTR INT IR7
INTA INT
CONTROL LOGIC
D7-D0 DATA
BUS
BUFFER
INTERNAL BUS
RD
READ/
WR WRITE IR0
LOGIC IR1
A0 INTERRUPT INTERRUPT IR2
SERVICE PRIORITY REQUEST IR3
REG RESOLVER REG IR4
CS IR5
(ISR) (IRR)
IR6
CAS0 IR7
CASCADE
CAS1 BUFFER
COMPARATOR
INTERRUPT MASK REG (IMR)
CAS2
SP/EN
CAS 0 CAS 2
R3



ICW1
ICW2
Is
NO (SNGL = 1) CASCADE
MODE
?
YES (SNGL = 0)
ICW3
Is
NO (ICW4 = 0) ICW4
NEEDED
?
YES (IC4 = 1)
ICW4
READY TO ACCEPT
INTERRUPT REQUESTS
A0 D7 D6 D5 D4 D3 D2 D1 D0
0 A7 A6 A5 1 LTIM ADI SNGL IC4
1 = ICW4 NEEDED
0 = NO ICW4 NEEDED
1 = SINGLE
0 = CASCADE MODE
CALL ADDRESS INTERVAL

1 = INTERVAL OF 4
0 = INTERVAL OF 8
1 = LEVEL TRIGGERED MODE

0 = EDGE TRIGGERED MODE
A7-A5 OF INTERRUPT
VECTOR ADDRESS
(MCS - 80/85 MODE ONLY)
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 A15 A14 A13 A12 A11 A10 A9 A8
A15-A8 OF INTERRUPT VECTOR

ADDRESS (MCS 80/85 MODE)
T7-T3 OF INTERRUPT VECTOR
ADDRESS (8086/8088 MODE)
ICW3 (MASTER DEVICE)

A0 D7 D6 D5 D4 D3 D2 D1 D0
1 S7 S6 S5 S4 S3 S2 S1 S0
1 = IR INPUT HAS A SLAVE

0 = IR INPUT DOES NOT
HAVE A SLAVE
ICW3 (SLAVE DEVICE)

A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 ID2 ID1 ID0

SLAVE ID
0 1 2 3 4 5 6 7
0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 0 0 0 1 1 1 1
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 SFNM BUF M/S AEOI PM
1 = 8086/8088 MODE
0 = MCS - 80/85 MODE
1 = AUTO EOI
0 = NORMAL EOI
0 X NON BUFFERED MODE

1 0 BUFFERED MODE/SLAVE
1 1 BUFFERED MODE/MASTER
1 = SPECIAL FULLY
NESTED MODE
0 = NOT SPECIAL FULLY
NESTED MODE
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 M7 M6 M5 M4 M3 M2 M1 M0
INTERRUPT MASK
1 = MASK SET
0 = MASK RESET
A0 D7 D6 D5 D4 D3 D2 D1 D0
0 R SL EOI 0 0 L2 L1 L0
0 1 2
0 1 0
0 0
0 0
A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 ESMM SMM 0 1 P RR RIS
READ REGISTER COMMAND

0 1 0 1
0 0 1 1
NO READ READ
ACTION IR REG IS REG
ON NEXT ON NEXT
RD PULSE RD PULSE
1 = POLL COMMAND
0 = NO POLL COMMAND
SPECIAL MASK MODE

0 1 0 1
0 0 1 1
RESET SET
NO
SPECIAL SPECIAL
ACTION
MASK MASK

+5 V
A15 VCC G
G2 Y0
Address
bus A4
A3 C 74LS138
A2 B
A1
A0 A +5 V
M/IO G1
GND
SP/EN VCC
CS IR0
Control
bus A0 IR1
RD RD IR2
WR WR IR3
INTR INT IR4
INTA INTA IR5
D0 D0 8259A IR6
D1 D1 IR7
D2 D2 CAS0
Data D3 D3 CAS1
bus D4 D4 CAS2
D5 D5
D6 D6
D7 D7 GND
F F F 0/ 2
+5 V
A 15
VCC G
G2 Y0
Address Y2
bus A4
Y4
A3 C 74LS138
A2 B
A0 A +5 V
M/IO G1
GND
SP/EN
/ VCC
CS IR0
Control
bus A1 A0 IR1
RD RD IR2
WR WR
INT INT IR3
INTA INTA IR4
D0 D0 8259-1 IR5
D1 D1 IR6
D2 D2 IR7
Data D3 D3
bus CAS0
D4 D4
CAS1
D5 D5
CAS2
D6 D6
D7 D7 GND
+5 V
SP/EN
/ VCC
CS IR0
A0 IR1
RD IR2
WR
IR3
INTA IR4
D0 8259-2 IR5
D1 IR6
D2 IR7
D3
D4
D5 CAS0
D6 CAS1
D7 CAS2
GND INT
+5 V
VCC
8259-3
SP / EN INT
GND CAS0 CAS1 CAS2
TM

Address
Latches
AD0 -AD15 A
Address Bus
ALE B
Data Bus
A
Micro Data Bus
Memory
Processor
B
Control Bus A
Control Bus
IOR , IOW
HLDA HOLD MEMR , MEMW B
HRQ
DMA
HLDA Controller Control Bus
Peripheral
IOR , IOW Device
MEMR , MEMW
(disk
DREQ Controller)
DACK0
IOR 1 40 A7
IOW 2 39 A6
MEMR 3 38 A5
MEMW 4 37 A4
VCC 5 36 EOP
READY 6 35 A3
HLDA 7 34 A2
ADSTB 8 33 A1
AEN 9 8237A/ 32 A0
HRQ 10 8237A-4/ 31 VCC (+5 V)
CS 11 8237A-5 30 DB0
CLK 12 29 DB1
RESET 13 28 DB2
DACK2 14 27 DB3
DACK3 15 26 DB4
DREQ3 16 25 DACK0
DREQ2 17 24 DACK1
DREQ1 18 23 DB5
DREQ0 19 22 DB6
(GND)Vss 20 21 DB7
MEMR, MEMW
MEMR
MEMW
IOR IOW
IOR IOW
EOP
EOP
EOP
EOP Decrementor Inc/decrementor
A0-A3
RESET Temp Word Temp Address I/O Buffer
CS Count Reg (16) Reg (16)
READY 16 BIT BUS
CLOCK 16 BIT BUS Output A4-A7
Timing
AEN And
Read Buffer Read / Write Buffer
Buffer
Control
ADSTB Base Current A -A
Base Current 8 15
Word Word
MEMR Address Count Address Count
(16) (16) (16) (16) Command
MEMW Control
IOR
IOW
Write Buffer Read Buffer D0 -D1
DB0 -DB7
DREQ0- 4 Command (8) Internal Data Bus I/O Buffer
DREQ3 Priority
Encoder
HLDA
And
Rotating Mask (4)
HRQ
Priority
DACK0- 4
Logic Read Write
DACK3
Mode Status (8) Temporary (8)
Request (4) (4x8)
EOP
Start Start Start
Is
Is Is
I/O device No
I/O device No I/O device No ready for
ready for ready for
data transfer
data transfer data transfer
?
? ?
Yes
Yes Yes
DMA acquires
DMA acquires DMA acquires the control of
the control of the control of buses from processor
buses from processor buses from processor
Transfers one byte

Transfers one Transfers one
byte byte
Is
No terminal
DMA relinguishes count exhausted
control of buses to Is ?
terminal Is
processor No
count Yes I/O device Yes
exhausted ready for
? data transfer
Is ?
Is No I/O device
Yes No
terminal ready for
No data transfer
count
exhausted ? DMA relinguishes
control of buses to DMA relinguishes
? control of buses to
Yes processor
processor
Yes
Stop Stop Stop
(a) Single transfer (b) Block transfer (c) Demand transfer

2ND LEVEL
1ST LEVEL 8237A

MICROPROCESSOR
HRQ DREQ HRQ
HLDA DACK HLDA
8237A
DREQ HRQ
DACK HLDA
8237A
ADDITIONAL
DEVICES
EOP
TC
DRQ7 HOLD
DAK7 HLDA
DRQ6
AEN
Microprocessor
DAK6
DRQ5 Master
DMA
DAK5 Controller
DRQ4
TC DAK4
IOWC
IORC
MWTC
MRDC
TC
A8-A1
HOLD
HLDA
DRQ3
DAK3
DRQ2
DAK2 Slave AEN

DRQ1 DMA
MRDC
Controller
DAK1 MWTC
DRQ0 IORC
DAK0 IOWC
A7-A0
D7-D0
EOP
st nd rd
1 2 3
Service Service Service
Highest 0 2 Service 3 Service
1 Service 3 Request 0
2 0 1
Lowest 3 1 2
A15 - A2 ADDRESS BUS
A15 A8
OE
STB
A3 - A0 A7- A4 AEN LATCH
ADSTB
HLDA
8237A-5
HRQ DB0
DACK0-3
DRQ0-3
RESET
MWRC
MRDC
CLK
IOW
DB7
IOR
4 4
CLK
RESET
MRDC
MWRC
IOR
IOW
D7 - D0 DATA BUS
TM


External
interrupts
ON-CHIP Counter inputs
INT0 INT1 ROM
for T1 T0
Interrupt program ON-CHIP
control code RAM Timer 0
(4 Kbytes) (128 Bytes) Timer 1
CPU Internal bus
Bus Four (8-bit) Serial

OSC I/O ports port
control
30 pF 30 pF P0 P1 P2 P3 TxD RxD
Multiplexed
data/address
4 to 30 MHz
Higher order Multi-functional
normally 11.0592 MHz address
16-bit DPTR
Memory
DPH DPL
(83H) (82H)
Address
16
8-bit 8-bit
B7 B6 B5 B4 B3 B2 B1 B0
ADDITION SUBTRACTION
9B H 1001 1011 89 H 1000 1001

+ 75 H + 0111 0101 – AB H – 1010 1011
Carry 1 10 H 1 0001 0000 Borrow 1 DE H 1 1101 1110
1 1 1 1 1 1 1 Carry
9B H 1 0 0 1 1 0 1 1
+
65 H 0 1 1 0 0 1 0 1
1 0 0 0 0 0 0 0 0
Accumulator
Direct Bit address Hardware
byte register
address symbol
(MSB) (LSB)
0FFH
0F0H F7 F6 F5 F4 F3 F2 F1 F0 B
0E0H E7 E6 E5 E4 E3 E2 E1 E0 ACC
0D0H D7 D6 D5 D4 D3 D2 D1 D0 PSW
0B8H --- --- --- BC BB BA B9 B8 IP
0B0H B7 B6 B5 B4 B3 B2 B1 B0 P3
0A8H AF --- --- AC AB AA A9 A8 IE
0A0H A7 A6 A5 A4 A3 A2 A1 A0 P2
98H 9F 9E 9D 9C 9B 9A 99 98 SCON
90H 97 96 95 94 93 92 91 90 P1
88H 8F 8E 8D 8C 8B 8A 89 88 TCON
80H 87 86 85 84 83 82 81 80 P0
P1.0 1 40 VCC + 5 V
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
Port 1
P1.4 5 36 P0.3 (AD3)
Port 0
P1.5 6 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
RST 9 32 P0.7 (AD7)
P3.0 (RXD) 10 8051 31 EA (VPP)
P3.1 (TXD) (40-pin)
11 D IP 30 ALE (PROG)
P3.2 (INT0)
12 29 PSEN
P3.3 (INT1) P2.7 (A15)
13 28
Port 3 P3.4 (T0)
14 27 P2.6 (A14)
P3.5 (T1) 15 26 P2.5 (A13)
P3.6 (WR) 16 25 P2.4 (A12)

Port 2
P3.7 (RD) 17 24 P2.3 (A11)
Oscillator XTAL 2 18 23 P2.2 (A10)

signals XTAL 1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
EA PSEN
R0 R7
Program memory
FFFFH FFFFH
EA = 0
60 kbytes Access
External External
memory 64 kbytes
OR External
1000H
0FFFH
4 kbytes EA = 1
Internal Access
0000 Internal 0000
memory
Data memory
Internal data memory External data memory
(SFRs)
FFH FFFFH
Accessible by
Accessible by
indirect
Upper direct
addressing
128 addressing
only
AND 64 kbytes
80H external
7FH memory
Accessible by
Lower direct & indirect
128 addressing
0 0000H
Byte
address Byte
address
1F R7 7F
1E R6
1D R5
1C R4
Bank 3
1B R3
1A R2
19 R1
18 R0
17 R7
16 R6
15 R5
14 R4
Bank 2
13 R3
12 R2
11 R1
10 R0 B7 B6 B5 B4 B3 B2 B1 B0
0F R7 7F 7E 7D 7C 7B 7A 79 78 2F
0E R6 77 76 75 74 73 72 71 70 2E
0D R5 6F 6E 6D 6C 6B 6A 69 68 2D
0C R4 67 66 65 64 63 62 61 60 2C
Bank 1
0B R3 5F 5E 5D 5C 5B 5A 59 58 2B
0A R2 57 56 55 54 53 52 51 50 2A
09 R1 4F 4E 4D 4C 4B 4A 49 48 29
08 R0 47 46 45 44 43 42 41 40 28
07 R7 3F 3E 3D 3C 3B 3A 39 38 27
06 R6 37 36 35 34 33 32 31 30 26
05 R5 2F 2E 2D 2C 2B 2A 29 28 25
04 R4 27 26 25 24 23 22 21 20 24
Bank 0
03 R3 1F 1E 1D 1C 1B 1A 19 18 23
02 R2 17 16 15 14 13 12 11 10 22
01 R1 0F 0E 0D 0C 0B 0A 09 08 21
00 R0 07 06 05 04 03 02 01 00 20
30
Register Bit addresses Byte General purpose
bank addresses
On-chip RAM On-chip RAM On-chip RAM
08 09
09
SP 07 08
Data 08
06 SP 07
Stack pointer SP SP+1 07
(a) Status of stack and (b) Store operation

stack pointer of reset
Data 1 09 Data 2 09
SP Data 2 08 Read 08
Data 3 07 SP SP–1 07
Stack pointer
(c) Read operation

1 12 
VCC I CC
PSEN
TM

Destination register Source register
Memory
Destination register
Address of memory
within the instruction
Data from
selected memory
location
Memory
Register
Contents of register are
used to point memory
Data from
selected memory
location
Data specified
in the instruction
DPTR Register
Program memory
A Register Contents of DPTR register
+
Data from Address of
selected memory memory
Contents of register A
1 1 1 1 0 0 0 0 Masking pattern
X X X X 0 0 0 0 Result
Masked bits
+ 1 1 1 1 0 0 0 0 Setting pattern
1 1 1 1 X X X X Result
Set bits
+ 0 0 0 0 1 1 1 1 Pattern for inverting lower 4-bits
X X X X X X X X Result
Inverted bits

7 6 5 4 3 2 1 0
C 7 6 5 4 3 2 1 0
Carry flag
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 C
Carry
flag
7 4 3 0
Higher nibble Lower nibble
12

Crystal frequency
12
11.0592  10 6



12
11.0592  10 6
 

12

11.0592  10 6
  
Mnemonic Source operand
AGAIN : MOV R1, A ; Copy contents of A to R1
Label Destination operand Comment

Editor
Assembly language
program text written
in any text editor
. asm
. lst
Assembler
Program listing
Converts assembly
instruction to object
code Error messages
. obj (Object code)

Other object
code files (optional)
Linker
Produces absolute
object code file
. abs
0H Program
Converts object code
file into executable file
. hex
Executable file







 

Start


Get the number
Number  100
Number Remainder
Hund_digit Quotient
Number  10
Ten_digit Quotient
One_digit Remainder
Stop
Start
Load the first 16-bit BCD number
Load the second 16-bit BCD number
Add two lower-digits
Adjust result to valid BCD number
Store lower byte of result
Add two higher - digits considering

carry of lower byte addition
Adjust result to valid BCD number
Store higher byte of result
Stop



Start
Initialize pointer
to memory
Initialize counter
Maximum number = 0
Get the number
Is
Number > Yes
Max. number
?
Max. number Number
No
Increment memory pointer
Decrement counter
No Is
counter = 0
?
Yes
Stop
Start
Initialize counter 1
Initialize memory pointer
Initialize counter 2
Get the number
Increment
memory pointer
Get the number
Is
(pointer) > Yes
(pointer + 1)
?
Interchange contents of
compared memory locations
No
Decrement counter 2
No Is
counter 2 = 0
?
Yes
Decrement counter 1
Fig. 1
No Is
counter 1 = 0
?
Yes
Stop
Start
Initialize count = 0
Initialize counter = 8
Get the contents of

 R0 register in the
accumulator
Rotate contents of
accumulator so that
LSB will go in carry
No Is
carry = 1
?
Yes
Increment count
Decrement counter
No Is
counter = 0
?
Yes
Stop

Start
Sum=0
Pointer = 2201H
Count = (2200H)
Sum = Sum + (Pointer)

 Pointer = Pointer +1
Count = Count – 1
No Is
Count = 0
?
Yes
(2300H) = Sum
End

 Start

Sum high = 0
Sum low = 0
Pointer = 2201H
Count = (2200H)
Sum low = Sum low + (Pointer)
No Is
Carry 1
?
Yes
Sum high = Sum high + 1
Pointer = Pointer + 1
Count = Count – 1
No Is
Count = 0
?
Yes
(2300H) = Sum low
(2301H) = Sum high
End
Start
Initialize counter = 10
Initialize source memory pointer
Initialize destination memory pointer
Get the byte from source memory block
Store byte in the destination memory block
Increment source memory pointer, increment

destination memory pointer and decrement counter
No Is
Count = 0
?
Yes
End

R0
TM

Addr/data bus VCC
Control
Read latch
P0.X
Pin
Internal bus D Q
P0.X
Latch Mux
Write to latch CL Q
Control logic
Read pin
VCC
Read latch
Internal
pull-up
P1.X
Internal bus D Q Pin
P1.X
Latch
Write to latch CL Q
Read pin
VCC
Addr bus
Control
Read latch
Internal
pull-up
Internal bus D Q
P2.X
P2.X
Latch
Pin
Write to latch CL Q
MUX
Control logic
Read pin
VCC
Alternate
output
function Internal
Read latch
pull-up
P3.X
Pin
Internal bus D Q
P3.X
Latch
Write to latch CL Q
Read pin
Alternate
input
function
VCC
P0.0
P0.1
P0.2
P0.3
8051 Port 0
P0.4
P0.5
P0.6
P0.7
Timer 1 register Timer 0 register
TH1 TL1 TH0 TL0

(8 - bit) (8 - bit) (8 - bit) (8 - bit)
Timer control (TCON) register
Timer mode (TMOD) register
(MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0
Timer 1 Timer 0
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

OSC 12
C/T=0 TL1 TH1

(5 Bits) (8 Bits) TF 1 Interrupt
C/T=1
T1 PIN
TR1
GATE Control
INT1 PIN
Timer/ counter control logic
TH0 TL0
OSC 12 (8 Bits) (8 Bits) TF0 Interrupt
C/T=0
TR0
GATE(TMOD.3) Control
INT0 PIN
Timer0 control logic

7 6 5 4 3 2 1 0
TMOD X X X X 0 0 0 1 = 01
OSC 12 TH0 TL0

(8 Bits) (8 Bits) TF0 Interrupt
C/T=0
TR0
Timer0 control logic when GATE = 0 and INT0 =1
TH1 TL1
OSC 12 (8 Bits) (8 Bits) TF1 Interrupt
C/T=0
TR1
INT1 PIN

7 6 5 4 3 2 1 0
TMOD 0 0 0 1 X X X X = 10H
OSC 12 TH1 TL1

C/T=0
TR1
Timer1 control logic when GATE = 0 and INT1 =1
TL0
OSC 12 (8 Bits) TF0 Interrupt
C/T=0
TR0
GATE(TMOD.3) TH0
Control (8 Bits)
INT0 PIN

7 6 5 4 3 2 1 0
TMOD X X X X 0 0 1 0 = 02H
OSC 12 TL0

(8 Bits) TF0 Interrupt
C/T=0
TR0
Timer0 control logic when GATE = 0 and INT0 =1 TH0

(8 Bits)
TL1
OSC 12 (8 Bits) TF1 Interrupt
C/T=0
TR1
GATE(TMOD.7) TH1
Control (8 Bits)
INT1 PIN

7 6 5 4 3 2 1 0
TMOD 0 0 1 0 X X X X = 20H
OSC 12 TL1

C/T=0
TR1
Timer1 control logic when GATE = 0 and INT1 =1 TH1

(8 Bits)
OSC 12 1/12 f OSC
C/T=0 TL0
(8 Bits) TF 0 Interrupt
C/T=1
T0 PIN
TR0
GATE Control
INT0 PIN
TH0
1/12 f OSC (8 Bits) TF 1 Interrupt
Control
TR1
C T T
T
TH0 TL0
T0(P3.4) (8 Bits) (8 Bits) TF0 Interrupt
C/T=1
TR0
INT0 PIN
Counter0 control logic
T0(P3.4) TH0 TL0

C/T=1
TR0
Counter 0 control logic when GATE = 0 and INT0 =1

7 6 5 4 3 2 1 0
TMOD X X X X 0 1 0 1 = 05H
7 6 5 4 3 2 1 0
TCON 0 0 0 1 0 0 0 0 = 10H
TH1 TL1
T1(P3.5) (8 Bits) (8 Bits) TF1 Interrupt
C/T=1
TR1
INT1 PIN
T1(P3.5) TH1 TL1

C/T=1
TR1
Counter1 control logic when GATE = 0 and INT1 =1

7 6 5 4 3 2 1 0
TMOD 0 1 0 1 X X X X = 50H
7 6 5 4 3 2 1 0
TCON 0 1 0 0 0 0 0 0 = 40H
TL0
T0(P3.4) (8 Bits) TF0 Interrupt
C/T=0
TR0
GATE(TMOD.3) TH0
Control (8 Bits)
INT0 PIN
T0(P3.4) TL0
C/T=0
TR0
Counter0 control logic when GATE = 0 and INT0 =1 TH0

(8 Bits)

s
500 s
TON TOFF   250 s
2
12
 1.085 s
11.0592  10 6
TON 250 s

T of clock 1.085 s

 TH1

12 12
  1.085 s
Crystal frequency 11.0592  10 6
30.38 s
 28
1.085 s

1
 2 ms
500
 TON TOFF T 2  1 ms
s
 
  B83E  1)
(FFFF (18370) 10
12
 1.085  10  6
11.0592  10 6
 1.085  10  6  18370
25 ms
 23041
1.085  10  6
 

1 12 MHz  12
s.
s
P1
RxD D
(P3.0) SBUF
Shift register CLK (Write only) Q TxD
(P3.1)
CLK
Baud rate clock

(Transmit)
Baud rate clock
(Receive)
SBUF
(Read only)
8051 Internal bus

1 1
32 64
1
12
1 1
32 64
Oscillator frequency
12
K  Oscillator frequency
32  12  [(256  TH1)]
K  Oscillator frequency
384  Baud rate
Timer 2 overflow rate
16
32  [ 65536  (RCAP2H, RCAP2L)]
32  Baud rate
1 1
32 64
1
32
1
64
k  Oscillator frequency
384  Baud rate
1  11.0592  10 6
384  9600
8051
TxD
(P3.1)
To PC
COM Port
RxD
(P3.0)
8051 MAX 232

TTL RS 232 5
side side
P 3.0
RxD 3
R1 OUT R1 IN
P 3.1
TxD 2
T1 IN T2 OUT
R2 OUT R2 IN DB-9P
connector
RS 232C
T2 IN T2 OUT
0 IT0
INT0 IE0
1
TF0
0 IT1 Interrupt
INT1 IE1 sources
1
TF1
TI
RI

 
11.0592  10 6
12
 256  250 s  921.6  10 3

12

12  10 6
TM

 20  20   
R W
R W R W

P1.0 DB0 VCC
P1.1 DB1
20 character  2 line
P1.2 DB2
P1.3 DB3 VEE
LCD
P1.4 DB4
display
P1.5 DB5 module
P1.6 DB6 VSS
P1.7 DB7
8051
RS R/W E
P3.2
P3.3
P3.4
 
R W

16  2
+5V
R R R R R R R R
K1
K2
K3
8051 K4
Input K5
port
(P1) K6
K7
K8
Column Column Column Column
3 2 1 0
Row 3
Row 2
Row 1
Row 0
+5 V
Column Column Column Column
3 2 1 0
R R R R
Row 3
Row 2
Data Input
bus port A Row 1
Row 0
Output port B
Data bus

5V
8 VCC
19 P17 7
XTAL1 P16
18 6
P15 5 Return
XTAL2 P14 4 lines
P13 3
P12 2
P11 C 8 4 0
1
P10
P 1.0
28
P27
27 D 9 5 1
P26
26
9 P25 P 1.1
RST 25
P24
24
P23 E A 6 2
23
P22
22
8051 P21
21
P 1.2
P20
31 F B 7 3
P07 32
EA/VCC
P06 33 P 1.3
P05 34
10 P04 35
11 RXD 36
TXD P03
P02 37
P01 38
P00 39 P 1.7 P 1.6 P 1.5 P 1.4
13 INT1 PSEN
29 Scan lines
12 INT0 30
ALE
15 T1 16
WR
14 T0 17
RD


+12 V
Stepper
X1 motor
P1.0
7407 X2
Y1 Y2
P1.1 +12 V
7407
P1.2
7407
P1.3
7407
X1
X'1
X2
X'2

+5V
+5V
4.7 K 4.7 K 4.7 K 4.7 K
P 1.0
P 1.1
P 1.2
P 1.3
8051 ULN 2003
4  2º  8º
TM

+5 V
VCC
POT Vin(+) RD P2.5
Vin(–) WR P2.6
ANLGGND
REF/2
D0 P1.0
D1 P1.1
10 K 8051
CLK OUT D2 P1.2
R D3 P1.3
CLK IN D4 P1.4
D5 P1.5
150 pF C CS D6 P1.6
D7 P1.7
GND INTR P2.7
ADC 0803/0804/0805
1
11
. RC
110 s
A1 A8
R 14
R 15 R 14
Output
range control 1 16 Compensation
GND 2 15 –Vref
VEE 3 14 +Vref
Current output 4 13 VCC

IC 1408
(MSB) A1 5 12 A8 (LSB)
A2 6 11 A7
A3 7 10 A6
A4 8 9 A5
MSB LSB
A1 A2 A3 A4 A5 A6 A7 A8
5 6 7 8 9 10 11 12
1 Io
Current switches
Range 4
control
2 GND
R/2R ladder Basic circuit
(+) Vref
13 VCC
14
Reference
15 current
(–) Vref amplifier
16
Compensation
3
VEE
NPN Current source pair

VCC
(MSB) 13
A1 2.5 K +5 V
14
Vref
A2 R14
A3 2.5 K
8-bit A4
Rf
digit
input A5 IC 1408 –
4
A6 Io
+ +
A7 Vo
A8
(LSB) 15
16 R15
3 1 2
15 pF 2.5 K
VEE
–15 V
Vref  A1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 
 + + + + + + + 
R 14  2 4 8 16 32 64 128 256 
A1 A8
5 1 1 1 1 1 1 1 1 
Io         
2 . 5 K  2 4 8 16 32 64 128 256 
2 mA  255
256
Vo 1 . 992  2 . 5
( 0000 0000) 2
(1111 1111) 2
(1111 1111) 2
VCC
+5 V
5 13 R14
A1 +5 V
14 Vref
6 A2 2.5 K
7
A3 IB If Rf
5K
8-bit 8 A4 RB
1 mA 5K
digital
9 IC 1408
input A5 –
4
10 Io A
A6
+ +
11 A Vo
7
–
12 A
8
15
COMP 16 R15
3 1 2
15 pF 2.5 K
VEE
RB
– IB + Io + If
Io
– IB + Io + If

4 MHz
VCC
X1 X2
C P20
P27
RST L
A0 - A15
P00 A
T
P07 C
R
8051 H
ALE D0 - D 7
PSEN PSEN
RD RD
P10 P17 WR WR
OE D7 -D0 A12-A0 WR OE D7 - D0 A12 - A0

2764 (EPROM) 6264 (RAM)
CS CS
Y1 D A A13
E B A14
C C A15
Y0 O
D
E G1
VCC R
GND G2
+5 V
2.5 K
13 14
2.5 K
2.5 K
DAC
4
–
0808
Vo
+
15
16 3 1 2
2.5 K
VEE
+2.5 V
0V 180º 360º
90º t
FFH
80H
96H
ABH
COH FEH
D2H
–2.5 V
E2H
EFH
F8H
º º º º
º 
º 
º 
º 
º 
º 
º 
º 
º 
º  
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
º 
+V (4 - 30 V)
LM35 Vout
R1 – Vs
R2 = –––––
50 A
– Vs
º

Current
AD590 to voltage Amplifier Vout
IT converter
VCC
+5 V ADC 0808 R 10K

OE XTAL1 XTAL2 VCC EA DB0
CH0 EOC P3.0 P0.0 VCC
IN0 DB1
CH1 P0.1
IN1 SOC P1.3 DB2 20 character
CH2 ALE P1.4 P0.2 × 2 line
IN2 DB3
ADC P1.2 P0.3 VEE
CH3 DB4 LCD
IN3 ADB P1.1
CH4 P0.4 display
IN4 ADA P1.0 DB5
P0.5 module
CH5
IN5 DB6
CH6 P0.6 VSS
IN6 DB7
CH7 P0.7
IN7 8051
P1.5 RS R/W E
Clock
CLOCK P1.6
Input
P1.7
D7 P1.0 +5V
D6 P1.1
+5 V D5 P1.2
VCC D4 P1.3 Buzzer
+REF D3 P1.4 +5V
D2 P1.5
–REF
D1 P1.6 MOSFET
P1.7 P3.7 2.5 K
GND D0
GND
Set to BZX284
2.56 V
10 K
+5V Vref (+)
(zener
diode 3.9 V)
Vout
LM35
Start
Initialize Ports,
Initialize LCD
Start A/D
conversion
No Is
conversion
over ?
Yes
Read ADC output
Calculate temperature
Is No
temperature
> 100
Yes Make Buzzer OFF
Make Buzzer ON
Display temperature
on LCD
End

FFFF H FFFF H
60 kbytes
External
64 kbytes
OR External
1000 H
0FFF H
4 kbytes
Internal 0000
0000
VCC
P0 D0
P1
D7
ROM/EPROM
L
8051 A A0
T
C A7
ALE
CLK H Addr.
P3 A8
P2
A15
PSEN OE
ALE
PSEN
PORT 0 INSTR
A0 - A7 A0 - A7
IN
PORT 2 A8 - A15 A4 - A15
0033 H
002B H
Serial Port 0023 H
Timer 1 001B H
Interrupt 8 Bytes
Locations External Interrupt 1 0013 H
Timer 0 000B H
External Interrupt 0 0003 H
RESET 0000 H
Internal Memory
FFFF H
(SFRs)
FF H
Accessible by
Accessible by
Indierct
Upper Addressing
Dierct
128 Addressing 64 kbytes
Only
External
80 H Memory
AND
7F H
Accessible by
Lower Direct and
128 Indierct
Addressing
0000 H
0
D0
P1 P0
D7
VCC
EA RAM
L
A A0
T
A7
C
8051 ALE H
CLK ADDR
P3 P2 PAGE
BITS
RD I/O
WR WR OE
ALE
PSEN
RD
PORT 0 A0 - A7 DATA A0 - A7 INSTR

IN IN
FROM RI OR DPL FROM PCL
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A8 - A15 FROM PCH

ALE
PSEN
WR
PORT 0 A0 - A7 DATA A0 - A7 INSTR

OUT IN
FROM RI OR DPL FROM PCL
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A8 - A15 FROM PCH


2 N  2 12
Input
data
WR
Input buffer EPROM
CS
4096 x 8
Internal decoder
Internal decoder
A10 A11
R/W
Memory
2048 x 8
A0 (N x M) A0
CS
Output buffer Output buffer
RD RD
Output Output
data data
(a) Logic diagram for RAM (b) Logic diagram for EPROM
D0
D7
A0
A7
A8
A15
RD
WR
PSEN
D7 - D0 A9 A8 A7 - A0 OE D7-D0 A9 A8 A7 - A0 OE WR
EPROM (1 K) RAM (1 K)
VCC
CS CS
G
A13 A Y0
A14 B Y1
A15 C B
G1 G2
74LS138
A10
A12 A11
D0 - D7
A0 - A7
A8 - A15
RD
WR
PSEN
D7-D0 A9 A8 A7-A0 OE D7-D0 A9 A8 A7-A0 OE WR
EPROM (1 K) RAM (1 K)
CS CS
A15
X1 X2 P2.0
P2.7
VCC L
A
P0.0 T A0-A15
C P0.7 C
RST H
R 8051 D0-D7
PSEN PSEN
EA WR WR
RD RD
ALE ALE
Reset
OE D7-D0 A11-A0 WR OE D7-D0 A10-A0 OE D8-D15 A1-A14

4 K (RAM) 2 K (EPROM) 2 K (EPROM)
CS CS CS
EPROM 0 EPROM 1
RAM 1
RAM 2
A11
RAM 3 EPROM 0
RAM 4
A14 A Y2
A13 D
B
E
A12 C C Y3 RAM 1
O EPROM 1
D Y4 RAM 2 A11
G1 E
R Y5 RAM 3
G2
GND Y6 RAM 4

X1 X2 P2.0
P2.7
VCC L
A
P0.0 T A0-A15
C P0.7 C
RST H
R 8051 D0-D7
PSEN PSEN
EA WR WR
RD RD
ALE ALE
Reset
OE D0 D7 A0 A13 OE D0 D7 A0 A13 OE D0 D7 A0 A13 OE D0 D7 A0 A13 WR OE D0 D7 A0 A13 WR OE D0 D7 A0 A13 WR OE D0 D7 A0 A13 WR OE D0 D7 A0 A13
EPROM EPROM EPROM EPROM RAM RAM RAM RAM

16 K x 8 16 K x 8 16 K x 8 16 K x 8 16 K x 8 16 K x 8 16 K x 8 16 K x 8
5V
1 2 3 4 1 2 3 4
CS CS CS CS CS CS CS CS
A14 A VCC G Y0
A15 D
B
E Y1
C C
O Y2
D
G1 E
Y3
R
G2
GND
74 LS 138
A15 A14 A13 A12 A11 A10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A1 A 0

EA
TM

13 Data Bus 8
Program Counter
Flash/ROM EEPROM Data Memory
Program
Memory
PIC16F83/CR83
RAM
512 × 14 EEPROM
File Registers
PIC16F84/CR84 8 Level Stack EEDATA Data Memory
PIC16F83/CR83
1K × 14 (13-bit) 64 × 8
36 × 8
PIC16F84/CR84
68 × 8
Program
Bus 14
7 RAM Addr EEADR
Addr Mux
Instruction reg
5 Direct Addr 7 Indirect TMR0

Addr
FSR reg
RA4/T0CKI
STATUS reg
8
MUX
Power-up
I/O Ports
Timer 8
Instruction Oscillator
Decode & Start-up Timer
Control ALU
Power-on RA3:RA0
Reset
Timing Watchdog W reg RB7:RB1

Generation Timer
RB0/INT
OSC2/CLKOUT MCLR VDD, VSS

OSC1/CLKIN
Data Bus 8-bit
Flash Program Status

Program Counter and Control
Memory
Interrupt
32 × 8 Unit
Instruction General
Register Purpose
Registers SPI
Unit
Instruction
Indirect Addressing
Decoder Watching
Data Addressing
Timer
ALU
Control Lines
Analog
Comparator
I/O Module 1
Data
SRAM I/O Module 2
I/O Module n
EEPROM
I/O Lines
Cortex-M3
Processor core system
Trace interface
Register
bank
Instruction
Interrupts (NVIC) Decoder Debug
fetch unit Trace
Interrupt system
controller ALU
Memory interface
Memory
Instruction bus protection Data bus
unit
Debug Debug
Bus interconnect
interface
Code Memory system Private Optional

memory and peripherals peripherals
Start
Display menu
1. HEX to BCD
2. BCD to HEX
3. EXIT
Read option
Yes If
option = 3
No
If Yes
option = 1 CALL HTB
?
No
If Yes
option = 2 CALL BTH
?
Stop




(TxC)
(TxC) 







( 341B) H
(123A) H
DS 123A0  implied zero
Offset  341B
157BB physical address











Raw
material
Processed
Process
Plant Product
reaction
Feedforward
Control Control Feedback

Control
action action action
Means of
Computer quality
Control measurement
action Appropriate
parameter
Reference
Display
Pressure sensor Relays
Flow sensor
Temperature sensor
Data
Input Micro Output D/A
acquisition
ports computer ports converters
system
Load cells
Keyboard Solenoid
PH meters valves

B4 B3


 
log 2 64 K log 2 65536 log 65536

2 2 2  log 2
log 16384
log 2 16 K
log 2


 (1101 0001 1001 0100) 2
PC 0
PC7
PC 1
12
0.6 s
20  10 6
0.5
0.6  10 6
[1  (255  14)]  0.6 sec
0.5 sec
2.142  10 3
MSB LSB
Gate C/T M1 M0 Gate C/T M1 M0
Timer 1 Timer 0
Bit configuration of the TMOD register
MSB LSB
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TCON bits used for timer programming
1 1
100 s
f 10 kHz
100 s
TON TOFF 50 s
2
12
0.6 s
20  10 6
TON 50 s

T of clock 0.6 s
 65536  83

Humidity Signal Driver Sound
sensor conditioner circuit alarm
Analog
inputs
Water
Temperature Signal Driver pump
sensor conditioner circuit relay
Port
pins
Microcontroller Data
LCD Module
To
Control
PC MAX Serial
232 interface
RS 232C
connector
Level
converter

EC8691 - Microprocessors and Microcontrollers (Ripped From Amazon Kindle Ebooks by Sai Seena)

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EC8691 - Microprocessors and Microcontrollers (Ripped From Amazon Kindle Ebooks by Sai Seena)

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SUBJECT CODE : EC8691

Strictly as per Revised Syllabus of

Dr. Deepali A. Godse

Semester - V (Computer Science & Engineering / Information Technology)

First Edition : June 2019

ã Copyright with Authors

9789333202312 [2] (ii)

Time required for execution of two

U = Undefined Carry flag : Set by carry out of MSB

7FFFFH Top of extra segment

70000H Extra segment base ES = 7000H

5FFFFH Top of stack segment

50000H Stack segment base SS = 5000H

4489FH Top of code segment

348A0H Code segment base CS = 348AH

2FFFFH Top of data segment

20000H Bottom of data segment

Top of code segment 4489FH CS 3 4 8 A 0 Implied zero

Code byte 38AB4H

End of stack segment 3FFFFH

Top of stack 38434H

SS = 3000H Start of stack segment 30000H

 BX  1, BX

Source address Destination address

+ 0 0 0 0 1 1 1 1 Pattern for inverting lower 4-bits

0 0 0 0 0 0 0 1 Bit pattern to test bit 0

CY Target register or memory

Sign bit (MSB)

near Disp Disp

AGAIN : ADD AX, price [BX] ; Add price of item to AX

Label Destination operand Comment

Locate time Locate BIN

Execution Run and test program Run and test program

Assemble time Assembler

Modules from Memory

Load time Loader

DATA for DATA for

Top of stack 49F20H

SS = 4000H Start of stack segment 40000H

(a) Before execution (b) After execution of PUSH AX and PUSH CX

End of stack segment End of stack segment 4FFFFH

(a) Before execution (b) After execution of POP DX and POP BX

CALL CALL CALL

NEXT MAINLINE RETURN

PROCEDURE PROCEDURE PROCEDURE

PROCEDURE RECURSIVE RET RET RET

Required delay time

AD0-AD15 Interrupt type

PUSH FLAGS, CS, IP

PUSH FLAGS, CS, IP

RETURN TO MAIN PROGRAM

INTR 18 23 TEST INTR 18 23 TEST

Data bus D15 D8 D7 D0

(Odd addressed memory bank) (Even addressed memory bank)

512 kbytes 512 kbytes

(Optional for increased

DI0 D Q DO0 DI0 D Q DO0

DI1 DO1 DI1 DO1

DI2 DO2 DI2 DO2

DI3 DO3 DI3 DO3

DI4 DO4 DI4 DO4

DI5 DO5 DI5 DO5

DI6 DO6 DI6 DO6