EBB 443

Dr. Sabar D. Hutagalung

School of Materials & Mineral Resources
Engineering, Universiti Sains Malaysia
Introduction
• Dielectric materials: high electrical resistivities, but an
efficient supporter of electrostatic fields.
• Can store energy/charge.
• Able to support an electrostatic field while dissipating
minimal energy in the form of heat.
• The lower the dielectric loss (proportion of energy lost
as heat), the more effective is a dielectric material.
• Another consideration is the dielectric constant, the
extent to which a substance concentrates the
electrostatic lines of flux.
 Dielectric Constant
• The capacitance, C, of a capacitor formed by two parallel plates
of area A spaced d apart with the area between the plates filled
with dielectric material with a relative dielectric constant of cis:

c = Ef:oA
. d

42

,'" IDOOO
Dielectric Loss
• For a lossy (imperfect) dielectric the dielectric
constant can be represented by a complex
relative dielectric constant:
g = e:ll-~E
• The imaginary part of this complex dielectric
constant, E at a frequency, (l) is equivalent to a
frequency-dependent conductivity, a( co), given
by:
Dielectric Loss
• €"is also known as the loss factor.
• The small difference in phase from ideal behaviour is
defined by an angle 0, defined through the equation
~I

- = tan 115
E'

• tan 0 is known as the loss tangent or dissipation factor.

• A quality factor, Q, for the dielectric is given by the
reciprocal of tan o.
Dielectric Loss
R

-
d
fiR V -
\!c
V
C
(b) (c)
(a)

Equivalent circuit diagrams: (a) capacitive cell, (b)

charging and loss current, (c) loss tangent for a typical
dielectric
Dielectric Loss
• From Q = 8 8fiVId = CV

• If V being sinusoidal, total charge Q may be written as

Q=CVo eiM
• Current flow on discharge of the capacitive cell in time, t:

I=dQ=iwCV
dt
• For a real dielectric the current I has vector components Ie and IR:
I = Ie + Ij?
Dielectric Loss
• From magnitude of these currents, also we can define a
dissipation factor, tan 8, as
I
tan6= R
Ie
• Quality factor Q is:
Q= 1 averageenergy stored
tan 8 energy dissipated per cycle
Alternating Current Theory

• Impedance of a resistance =R
• Impedance of a capacitance = 1Ii we
• Mean power, P, dissipated over a cycle in a lossy
capacitor with plates of area A separated by a distance
d:

2E/ Cr)
- ro -. . ." ,) 1 « ) ~1.,
,- . . :It: -'1
II A,
L.
.... ~
p=- Re {V) _Re'(l dr ,=-. Re tv]. = -, eoe EO -J!;o
2n: " ) 2 '" 2 d
o
Dielectric Strength
• Dielectric materials are insulators (conduction cannot
generally occur).
• However, under certain conditions, dielectric materials
can break down and conduct a significant current.
• Generally, the lattice of a dielectric has sufficient strength
to absorb the energy from impacting electrons that are
accelerated by the applied electric field.
• However, under a sufficiently large electric field, some
electrons present in the dielectric will have sufficient
kinetic energy to ionize the lattice atoms causing an
avalanching effect.
• As a result, the dielectric will begin to conduct a
significant amount of current.
Dielectric Strength
• This phenomenon is called dielectric breakdown and the
corresponding field intensity is referred to as the
dielectric breakdown strength.
• Dielectric strength may be defined as the maximum
potential gradient to which a material can be subjected
without insulating breakdown, that is

dV
DS=
dx max

where OS is the dielectric strength in kV/mm,

VBthe breakdown voltage, and dthe thickness.
 B
BREAKDOWN
REGION
CL
E 6
o
l7>

b
--;; 4

°O~------~--~--~--~
10 20
__~30
VOLTAGE (Kvl

current-voltage characteristic up to breakdown for

a typical dielectric materials
Dielectric Strength
• Dielectric strength depends on
~ material homogeneity,
~ specimen geometry,
~ electrode shape and disposition,
~ stress mode (ac, dc or pulsed) and
~ ambient condition.
 Ooelccuic

Capacitors
V", 10 ..olts
...

q= 20nC

'"etal plate s Vokmeler reeds l:!. V Tantalum capacitor

Capacitors
• The basic formula for the capacitance of a parallel-plate
capacitor is: A
C = GrGo-
d
• To increase C, one either increases E, increases A, or
decreases d.
• Early capacitors consisted of metal foils separated by
wax (8 - 2.5), mica (8 - 3 - 6), steatite (8 - 5.5 - 7.5), or
glass (8- 5 -10).
• The use of titania provided a significant increase (8-
170), was followed by perovskite-based, such as BaTi03
(8 - 1000).
Capacitors
C = "capacitance"
=q/!J,.V

Units: Coulomb/Volt
= Farad (F)

The capacitance of a Michael Faraday

capacitor is constant; (1791-1867)
if q increases, !J,.
V
increases proportionately.
 .~
# •
~ . . •
,.
\,

.......-...
- ... ~:
...
. ..._.-..
.....
Capacitors

++++++++ ++++++++

-------- ------- -a
E effective = E • Epolarization = -
For aJr, £==£0 ££0
,....----------,
The capacitance is
C=£oA increased by the
d factor e

E stored =
~CV2
2 ~VQ
2
 SMD Compomnt

Capacitors
VI. Hille

• DRAM chips currently utilize capacitors with Si3N4or Si02

as dielectric materials.
• The electrodes are made of doped Si or poly-Si.
• Capacitors can be fabricated onto IC chips.
• They are commonly used in conjunction with transistors in
DRAM.
• The capacitors help maintain the contents of memory.
• Because of their tiny physical size, these components have
low capacitance.
• They must be recharged thousands of times per second or
the DRAM will lose its data.
 Q=c,co--
AVl
dj
III
0)
L.
ro Q=CV
.c
u Q: charge (Coulomb)

V
'
......
..- _-- C: capacitance (Farad)
V: potential difference (Volt)

" ) - d: separation/thickness (meter)

eo: permitivity of vacuum =
8.854xlO-12 C2/m2 or F/m
e.: dielectric constant
Multilayer Ceramic Capacitolr

• The multilayer ceramic capacitor (MLCC):

Multi Layer Ceramic Capacitor
(MLCC)

• where N is the number of stacked plates.

• Ideally, the dielectric should have a low electrical
conductivity so that the leakage current is not too large.
Multilayer Ceramic Capacitor

Ceramic surface-mount
capacitors.
End term inal

Cut-away view of multilayer

ceramic capacitor.
High-K Dielectric
• The bit count of MOS DRAM devices is
continuously increasing. However, as bit count
goes up, capacitor cell area goes down.
• The capacitance per cell must remain in the 25-
30 fF range, which means the capacitance
density must increase.
• One approach for DRAM manufacturing is to
replace the traditional silicon nitride + silicon
oxide with a higher dielectric constant (k) such
as tantalum pentoxide (Ta20s), Hf-oxide (Hf02)
and Zr-oxide (Zr02).
 0.18 Tech 0.15 Tech 0.13 Tech 0.10 Tech 0.07 Tech

t999 2002 2005 2008

o 2J.1Tl

BST

SIS C,lilllcl I HS6 s

The road map of capacitor with DRAM technology.

0.-5. Yoon et al, I Progress in Materials Science 48 (2003) 275-371

High-K Dielectric
• High-k dielectric films are anticipated to be
required for certain applications with low power
and leakage current specifications.
• High-k materials should be compatible with
conventional industry standard MOSFET
process flows using a poly-Si gate electrode.
• Hf02, Zr02, and Ta20S as high-k gate-
dielectrics.
 Hf02/Poly-Si high-k transistor
~--- Ti..salicide

Oxide spac:«
-, Oxide spacer
/'

structure and sub-cxide growth underneath Hro~in the spacer region.

ftgure 10. IIR-TI:M micrograph o;howingdetml" of gate stack. (3) IOOf)''(',

I() sec itT", (b) HSO"C. 30. ec R rA,
 Zr02/Poly-Si high-k transistors
SID RTA: 900C, 10 sec
PolySi

Spacer Poly-SI

FIgure -I. IE'" aucrogrnpb of Zr01IPoly gftlestack sbOWUlg 4.8run zr01

Zr02 foot
sandwiched between two interfacial layers of 1.1run each.

Figure 5. T£.'I'!micrograph showing S. crystalline defects at the Poly-S. gate

edge after complete processing. No sign of gate-undercut was observed.
Typical material stack used in aTa205
DRAM capacitor
Cntlc1IIlrterfu.
__...,. TlNrr~o" o~
dithulon
1-----!"~---1 -.......
T~O~ISI,N, SI()Jt"
rorrNltJon
-...... 51tH. "'oty
,.oty
poty r_xldlGon

Doped Potyl 20 A SIN' 100A TI't2~ with 800" C N20Arneal

~-T. ~.
TlN_ :\1
~." I ( '"
..
•

.-
Dap.t '
"'Cltv
A Review of High H~gh-kDielectrjes

• Gate dielectric materials having high dielectric

constant, large band gap with a favorable band
alignment, low interface state density and good
thermal stability are needed for future gate
dielectric applications .
• Ultra high-k materials such as STO (SrTi03) or
SST (SaSrTi03) may cause fringing field
induced barrier lowering effect.
A Review ot High High-k Dielectrics

• High-k gate dielectrics have a number of

difficulties:
(1) crystallization upon heating,
(2) dopant penetration,
(3) fixed charge,
(4) low channel mobility and
(5) uncontrolled oxide formation at the Si/high-k
interface.
High-K Problems

• High-K and polySi gate are incompatible due

to Fermi level pinning at the high-K and
polySi interface which causes high threshold
voltages in transistors

• High-K/polySi transistors exhibit severely

degraded channel mobility due to the
coupling of SO phonon modes in high-K to
the inversion channel charge carriers
High-K and PolySi are Incompatible

Poly Si

Interface

High-K

• Defect formation at the polySi-high-K interface

Phonon Scattering in High-K
,
45E.05T"""----"""T'"----"""'T"--------,
,,

I-
4.0E-05
+--------.-'-------,'i------,j

"0_ 3.5E-05
~
High-KlPolySi
+--------.-. ------i'i-I-_.
,
-
--I..._--------f
• Coulombic Phonon

Ilpb J, T t
Surface
Roughness

E' :
,...., .,f • I-

1------::---:
~ 3OE·05 :-"""'~'-=='i==::1::====::::;_1:::t.
;: : Phonon scattering c_1_
~~E-05. I-----~~~.~-~==~==~F=======~~
:.
-1!L I aT >
0

. ,.
• '"T:'t III
-I------'·"'"---S
2.0E-05 i02lP 0 lyS i-.----::-.+.I.__,·..__-~ I

i •• i

.'
•
1.5E-05 l --=------i;i----+-------f
••
+-----.--1"":'., : E-Field
,
,
10E-05~--~-~----.'----~----~'----~----~--~
I

0.1 1.1 1.3 1.5 1 1 1 1

0.3 0.5 0] 0.9 --+ +--
E-Field (MV/cm) Jiph JISR
 ~12
l!!J NMOS
10 ; o 0 ....1
8 0...6'
The Gate Stack &
co
e 0 ·8
...
••• ~

~...
e 0 ~8""O
.
2 0
o .0' 0'"
o 6.1 D2 0.3 6.4
Gate electrode
Gal. Length l (11m)

~~.---------------,
PMOS 0 .,.(:>
o ..§....
~. I
20

t
- 15

I 000.···9··
i 10 Q ··6
111111111111111111111111 Channel layer ..9'...~.~
5
@••, .' 0
Si substrate o .'
o 01 02 0.3 0••

Expected performance trends for complementary

Schematic illustration of
important regions in a CMOS
FET gate stack
metal oxidesemiconductor (CMOS) transistor
technologies. The unrelenting reduction in transistor
size and the associated decrease in gate delay for (a)
an NMOS transistor and (b) a PMOS FET are
evident.
 Gate Length
=
LG 45 nm
=13nm

EOT = 0.5

Source and Drain

Extension Junction
Depth = 25 nm EOT- equivalent oxide
thickness

Schematic image of MOS transistors in the year 2003 and 2013.

 Hiqh-k Gate Dielectric

Gate

EOT= 1 nm
Drain
N·Channel

Physical and electrical thickness of high-k gate dielectric (ideal).

Si02 equivalent thickness EOT is smaller than high-k physical
thickness.
 Ing

Poli-
Silicon
W
e(5T
Source Drain
N-Channel

The depletion region of thickness Wd forms adjacent to the

poly-Si/oxide interface.
 c = J(e A
t J'
+

• For example, if the capacitor dielectric is

Si02, teq = 3.90co (AlC), Co = 8.85x1 0-3
fF/J.lm, thus a capacitance density of
CIA=34.5 fF/J.lm2 corresponds to teq =10 A .
• A dielectric with a relative permittivity of 16
o

results in a physical thickness of "'40 A, to

o

obtain teq = 10 A.
I
 High-lC
layer
.. - Interfacial
.
laver
( 'iO v

Comparison of (a) stacked and (b) single-layer gate dielectrics in a

hypothetical transistor gate stack.
Either structure results in the same overall gate stack capacitance or
o

equivalent oxide thickness, teq=10 A.