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FP6321A
Description Features
The FP6321A is designed to drive two N-channel ● Operates from +5V or +12V
MOSFETs in a synchronous rectified buck topology. ● Drives Two Low Cost N-Channel MOSFETs
It provides the output adjustment, internal soft-start, ● Fast Transient Response
frequency compensation networks, monitoring and ● Simple Single-Loop Control Design
protection functions into a single package. ( Voltage-Mode PWM Control)
● Internal Soft-Start
The IC operating at fixed 300kHz frequency provides
● Over-Current Fault Monitor
simple, single feedback loop, voltage mode control
● Over-Voltage Protection
with fast transient response. The resulting PWM duty
● Under-Voltage Protection
ratio ranges from 0-100%.
● SOP-8 Package
The FP6321A features over current protection. The ● RoHS Compliant
output current is monitored by sensing the voltage
drop across the RDS (ON) of the low side MOSFET
which eliminates the need for a current sensing Applications
resistor. ● Motherboard
This device is available in SOP-8 package. ● Graphic Card
● Telecomm Equipments
● High Power DC-DC Regulators
● Servers
P: Green
G: Green
Package Type
SO: SOP-8
Figure 1. Pin Assignment of FP6321A
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This pin provides bias voltage to the high side MOSFET Driver. A bootstrap circuit may be to create a BOOT
BOOT
voltage suitable to drive a standard N-Channel MOSFET.
Connect UGATE to the high side MOSFET gate. This pin is monitored by the adaptive shoot-through protection
UGATE
circuitry to determine when the high side MOSFET has turned off.
GND Ground.
Connect LGATE to the low side MOSFET gate. This pin is monitored by the adaptive shoot-through protection
LGATE
circuitry to determine when the high side MOSFET has turned off.
OCSET Shutdown Control and connect a resistance (ROCSET) for over current setting.
PHASE Connect the PHASE pin to the high side MOSFET source.
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Block Diagram
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Electrical Characteristics
(VCC=12V, TA=25°C, unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
INPUT
ERROR AMPLIFIER
OSCILLATOR
GATE DRIVERS
VBOOT-VPHASE=12V,
Upper Gate Source IUGATE 0.6 1 A
VUGATE-VPHASE=6V
VBOOT-VPHASE=12V,
Upper Gate Sink RUGATE 4 8 Ω
VUGATE-VPHASE=1V
PROTECTION
Note2:Guarantee by design.
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0.84 340
0.83 330
Reference Voltage (V)
0.82 320
Frequency (KHz)
0.81 310
0.80 300
0.79 290
0.78 280
0.77 270
0.76 260
0.75 250
-40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80
o
Junction Temperature ( C)
o Junction Temperature ( C)
Figure 4. Reference Voltage vs. Junction Temperature Figure 5. Frequency vs. Junction Temperature
100
VCC=12V
44
95 VIN=5V
VOUT=1.8V
OC Current Source (uA)
42
90
Efficiency(%)
40 85
80
38
75
36
70
-40 -20 0 20 40 60 80 0 2 4 6 8 10 12 14
o
Junction Temperature ( C) Output Current (A)
Figure 6. OC Current Source vs. Junction Temperature Figure 7. Efficiency vs. Output Current
VOUT VOUT
IL IL
VPHASE VPHASE
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VOUT VOUT
IL IL
VPHASE
VPHASE
Figure 10. Power On at 15A Loading Figure 11. Power OFF at 15A Loading
VUGATE
VUGATE
VPHASE
VPHASE VLGATE
VLGATE
Figure 12. Switching waveform (UGATE rising) IOUT=0A Figure 13. Switching waveform (UGATE rising) IOUT=15A
VUGATE
VUGATE
VPHASE
VPHASE
VLGATE VLGATE
Figure 14. Switching waveform (UGATE Falling) IOUT=0A Figure 15. Switching waveform (UGATE Falling) IOUT=15A
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VUGATE
VPHASE
VPHASE
VLGATE
VLGATE
Figure 16. Switching waveform (UGATE rising) IOUT=0A Figure 17. Switching waveform (UGATE rising) IOUT=15A
VUGATE
VUGATE
VPHASE
VPHASE
VLGATE
VLGATE
Figure 18. Switching waveform (UGATE Falling) IOUT=0A Figure 19. Switching waveform (UGATE Falling) IOUT=15A
IL IL
VOUT VOUT
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VOUT
VOUT
IL IL
Figure 22. Transient test:100Hz, Slew rate:2.5A/us Figure 23. Transient test:1KHz, Slew rate:2.5A/us
VOUT VOUT
IL IL
Figure 24. Transient test :100Hz, Slew rate: 2.5A/us Figure 25. Transient test: 1kHz, Slew rate:2.5A/us
VOUT VOUT
IL IL
VPHASE
VPHASE
Figure 26. OCP Using DC Loading Figure 27. OCP Using DC Loading
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Functional Description
Initialization Shutdown
The Power-On Reset (POR) function continually Connecting a small transistor to OCSET pin, and
monitors the input supply voltage VCC, VIN and the pulling the OCSET voltage less than 0.15V can
enable function. The POR monitors the bias voltage shutdown the FP6321A. At this condition, the
at the VCC pin UGATE will continuously generate FP6321A is shutdown and high side and low side
a 9.375kHz clock with1% duty cycle before VIN is MOSFETS are turned off. The output is floating.
ready. VIN is recognized ready by detecting VOPS
crossing 1.5V four times (rising & falling). When Under-Voltage Protection
VCC and VIN power are ready, the FP6321A starts
to ramp up the output voltage up to the target The under-voltage function monitors the FB
voltage to protection the converter against the
voltage.
output short-circuit condition. The under- voltage
Soft-Start threshold is 75% VREF. The UV has 20us triggered
delay. When UVP happens, the converter re-starts
The FP6321A features soft-start to limit inrush up without latching off.
current and control the output voltage rise at
start-up. The soft-start is accomplished by ramping Over-Voltage Protection
the internal reference input from 0V to 0.8V. The
soft-start interval is 3.5ms typical. The over-voltage function monitors the FB voltage
to protection the converter against the output from
Over-Current Protection over-voltage. When the output voltage rises to
120% VREF, the FP6321A turns on the low side
The over-current function protects the converter a MOSFET until the output voltage below the OVP
shorted output by using the low side MOSFET threshold.
on-resistance RDS-ON to monitor the current. This
method enhances the converter’s efficiency and
reduces cost by eliminating a current sensing
resistor.
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Application Information
Introduction The ESR can be calculated from the following
formula.
The FP6321A integrated circuit is a synchronous
PWM controller, it operates over a wide input voltage VRIPPLE
ESR =
range. Being low cost, it is a very popular choice of ΔIL
PWM controller. This section will describe the
FP6321A application suggestion. The operation and An aluminum electrolytic capacitor's ESR value is
the design of this application will also be discussed in related to the capacitance and its voltage rating.
detail. In most case, higher voltage electrolytic
capacitors have lower ESR values. Most of the
Design Procedures time, capacitors with much higher voltage ratings
may be needed to provide the low ESR values
This section will describe the steps to design required for low output ripple voltage.
synchronous buck system, and explains how to
construct basic power conversion circuits including b. The capacitor voltage rating should be at least 1.5
the design of the control chip functions and the basic times greater than the output voltage, and often
loop. much higher voltage ratings are needed to satisfy
the low ESR requirements needed for low output
(1) Synchronous buck converter ripple voltage.
Since this is a buck output system, the first quantity (3) Output N-channel MOSFETs Selection
to be determined is the duty cycle value. The formula
calculated the PWM duty ratio, apply to the system a. The current ability of the output N-channel
which we propose to design: MOSFETs must be at least more than the peak
switching current IPK. The voltage rating VDS of
the N-channel MOSFETs should be at least 1.25
times the maximum input voltage. Choose the
(2) Inductor Selection low RDS-ON MOSFETs for reducing the conduction
power loss. Choose the low CISS MOSFETs for
reducing the switching loss. But most of time, the
To find the inductor value it is necessary to consider two factors are trade-off. Consider the system
the inductor ripple current. Choose an inductor which requirement and define the MOSFETs rating.
operated in continuous mode down to 10 percent of
the rated output load: b. The MOSFETs must be fast (switch time) and
ΔIL = 2 x 10% x IO must be located close to the FP6321A using
The inductor “L” value for this system is connected to short leads and short printed circuit traces. In
be: case of a large output current, we must layout a
copper to reduce the temperature of these two
(VIN - VDS(sat) – VO) x DMIN MOSFETs.
L ≧
ΔIL x fS
(4) Input Capacitor Selection
If the core loss is a problem, increasing the a. The RMS current rating of the input capacitor can
inductance of L will be helpful. be calculated from the next page formula table.
(3) Output Capacitor Selection b. This capacitor should be located close to the IC
using short leads and the volt age rating should
a. The output capacitor is required to filter the output
be approximately 1.5 times the maximum input
noise and provide regulator loop stability. When
voltage.
selecting an output capacitor, the important
capacitor parameters are; the 100kHz Equivalent
Series Resistance (ESR), the RMS ripples current
rating, the voltage rating, and capacitance value.
For the output capacitor, the ESR value is the
most important parameter.
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Board Layout
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Outline Information
SOP- 8 Package (Unit: mm)
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