You are on page 1of 20

 

                                            NE1101A/B

High Performance Green Mode PWM controller


General Description Features
The NE1101A/B is a current mode controller  Current mode control with Internal slope
which contains advanced features to meet the compensation
stringent worldwide green energy requirements.  High-Voltage Startup current source
Among the advanced energy saving functionalities  Peak current limited Burst mode
include the NE1101A/B include a low leakage high  Internal 2.5mS softstart
voltage startup current source that minimize no  Internal 200nS Leading Edge Blanking
load standby power losses  Cycle-by-Cycle current limit
It has a PFC VCC pin which is capable of
 Latched OCP & OVP functions
delivering 35mA to the front stage PFC controller.
 Frequency Jittering for EMI reduction
This bias will cut off automatically when the IC
enters Green mode under light load. This feature  Over Temperature, over load protections
simplifies the PFC circuit design and reduces  Automatic PFC bias supply output
power losses

y
Under light load, the NE1101A/B enters burst Applications
mode to maintain high efficiency operation

nl
 General 30W-100W flyback SMPS
The NE1101 also features frequency dithering
 AC adaptor for Notebooks, Printers
function that spreads the EMI spectrum and saves
 Off-line battery chargers
the cost on EMI solution.
Other features that incorporated in the NE1101
are latched OVP, OCP, OTP functions, which is
triggered by pulling CS pin above 3.0V and reset
by pulling it to ground. .


O LCD monitors, Set-Top boxes, power tools
Open-frame SMPS
Standby power for TVs, PCs, Home appliances

Package
PL
The switching frequency of NE1101A is internally
fixed at 100KHz. The NE1101B is fixed at 65KHz.
These two versions are available in SO8 and DIP8
packages
SA

Typical Application
r
Fo

July,2010 – Rev 1.1  www.nem.com.tw    Page 1 


                                             NE1101A/B

Functional Block Diagram

y
nl
O
PL
SA

Functional Pin Description


r

Pin Name Pin Function Description


Fo

PFC VCC 1 Provide bias of max 35mA to PFC controller under normal operation condition

Voltage feedback pin. By connecting a photo-coupler to close control loop and


FB 2
achieve the regulation

CS 3 Senses the primary current

GND 4 Ground

GATE 5 Gate drive output to drive the external MOSFET

VCC 6 Power Supply pin

NC 7 No connection

HV 8 High voltage startup pin. Connect this pin to the bulk voltage rail

July,2010 – Rev 1.1  www.nem.com.tw    Page 2 


                                             NE1101A/B
Absolute Maximum Ratings (Note 1)
 Supply Input Voltage, VCC…….….…………21V
 GATE pin…………………………….………...15V
 FB, CS pin……………………….……...........10V
 HV pin…………………………….…………..500V
 PFC VCC pin………………….……………….21V
 ICC…………………………………..…………10mA
 Junction Temperature…………….…………150℃
 Lead Temperature (10sec)…………...........260℃
 Storage Temperature Range………………-60℃to150℃
 ESD Susceptibilty (Note 2)
HBM (Human Body Mode)…………………3KV
MM (Machine Mode)…………….………….200V

y
 Power Dissipation, PD@TA=25℃,
SO8…………………………………..…0.76W

nl
DIP8…………………………………….0.98W
 Package Themal Resistance θJA (Note4)

 
 
SO8….……………………………….…165.5℃/W
DIP8…………………………………….127.0℃/W
O
PL
Recommended Operating Conditions
 Supply Voltage ,VCC………………………7.7V to 18V
 Junction Temperature Range……….… - 40°C to 125°C
 Ambient Temperature Range………….. - 40°C to 85°C
SA

Marking Information:
r
Fo

Ordering Information:
Part Number Freq Package Shipment
NE1101A-S0 100KHz SO8 Tape & Reel/2500ea
NE1101B-S0 65KHz SO8 Tape & Reel/2500ea
NE1101A-S0T 100KHz SO8 Tube/100ea, 100 Tubes/Box(10000ea)
NE1101B-S0T 65KHz SO8 Tube/100ea, 100 Tubes/Box(10000ea)
NE1101A-D0T 100KHz DIP8 Tube/50ea, 60 Tubes/Box(3000ea)
NE1101B-D0T 65KHz DIP8 Tube/50ea, 60 Tubes/box(3000ea)

July,2010 – Rev 1.1  www.nem.com.tw    Page 3 


                                             NE1101A/B
Electrical Characteristics
(Unless otherwise stated, all specifications apply for Tj=25℃,VCC=13V, VHV=30V. Tj=0℃ to 125℃
for min/max values respectively

Specifications
Parameter Symbol Test Conditions Pin Units
Min Typ Max
Supply Voltage Section(VCC pin)
VCC On Threshold Voltage VCC-On VFB=2.0V 6 11.6 12.6 13.6 V
VCC Off Threshold Voltage VCC-Off 6 7.0 7.7 8.4 V
VCC Deep sleep Phase Ends VDeep-Off VFB=3.5V 6 5.0 5.6 6.2 V
VCC Reset Internal Logic VCC-Reset 6 - 4.7 - V

y
VFB=2.5V,
Operating Supply Current 1 ICC1 6 0.4 0.72 1.8 mA
CGATE=open

nl
VFB=2.5V, CGATE=1nF,
6 1.18 1.76 3.0 mA
A Version
Operating Supply Current 2 ICC2

O
VFB=2.5V, CGATE=1nF,
B Version
VCS=3.3V,
6 1.18 1.55 2.5 mA
PL
Operating Supply Current 3 ICC3 6 0.4 0.52 1.0 mA
Latch-Off Mode

Internal Startup Current Source Section (HV Pin)


VCC= VCC-On-0.2V
SA

HV current source , 1.0nF load IHV1 VFB=2.5V 8 0.94 1.77 4.2 mA


VHV=60V
VCC= 0V
HV current source IHV2 8 1.8 3.1 5.6 mA
VHV=60V
r

VCC= VCC-On-0.2V
Fo

Minimum Startup Voltage VHVmin VFB=2.5V 8 - 15 18 V


IHV=0.5mA
VHV=500V,
Startup Leakage IHVLeak 8 1 3.8 20 uA
VCC= VCC-On+0.5V

Gate Drive Section (GATE Pin)


Rising Time TR VCC = 13V, CL = 1nF 5 28 nS
Falling Time TF VCC = 13V, CL = 1nF 5 24 nS
Gate Output Clamping Voltage Vclamp VCC=18V(Note 5) 5 14.3 V
Jitter Percentage Pjit VFB=2.5V(Note 5) 5 ±6.4 %
Jitter Period Tjit VFB=2.5V(Note 5) 5 5 mS

July,2010 – Rev 1.1  www.nem.com.tw    Page 4 


                                             NE1101A/B
 
Specifications
Parameter Symbol Test Conditions Pin Units
Min Typ Max
TJ=25℃, A Version 93 100 107
5 KHz
TJ=0℃~+125℃ 90 - 110
Oscillation Frequency Fosc
TJ=25℃,B Version 60 65 70
5 KHz
TJ=0℃~+125℃ 58 - 72
Maximum Duty Cycle Dmax VCS=0V, VFB=2.5V 5 75 80 85 %

Feedback Section (FB Pin)


Opto Current Source IOPTO VFB=0.75V 2 200 225 290 uA
FB Open Voltage VFB-OP 2 3.3 4.1 4.5 V
Burst Mode Entry Point VBurst 2 600 720 900 mV

y
Burst Mode Leaving Point Vstby-out 2 1.0 1.2 1.5 V

nl
Current-Sense Section(CS Pin)
Input Bias Current IIB Vcs=1V 3 2 8.5 20 uA

Maximum Internal Current Setpoint

Leading Edge Blanking Time


VCSLim

TLEB
TJ=25℃
O
TJ=0℃~+125℃
3

3
1.01
0.976
100
1.057
-
200
1.116
1.168
350
V

nS
PL
VGATE 10V to Low
Propagation Delay Time TPD 3 - 90 180 nS
CGATE=1nF
Soft-Start Period TSS (Note 5) 3 - 2.5 - mS
SA

Latch-Off Level Vlatch 3 2.7 3.0 3.3 V


RFC Controller Source Section (PFC_Vcc Pin)
RDSON between Pin 1 and Pin 6 RPFC RLoad In Pin 1=680Ω 1 6 20 32 Ω
Internal Ramp Compensation
r

Internal Ramp Compensation Resistor RRamp (Note 5) 3 9 18 36 KΩ


Fo

Ramp Compensation Sawtooth


3 - 2.3 - V
Ampitude
Protection
Timeout before Validating Short-circuit TDEL (Note 5) - 100 - mS
Temperature Shutdown TSD (Note 5) 150 165 - ℃
Temperature Shutdown Hysteresis TSDHY (Note 5) - 25 - ℃
Note 1: Stresses beyond ‘Absolute Maximum Ratings’ may cause permanent damage to the device
Note 2: Devices are ESD sensiive.Handling precaution recommended. The human body model is 100pF
capactor discharged through a 1.5KΩ resistor into each pin.
Note 3: The device is not guaranteed to function outside its operating conditions
Note 4: θJA is measured in the natural convection at TA=25℃ on a low effective single layer thermal conductivity
test board of JEDEC 51-3 thermal measurement standard.
Note 5: Guaranteed by design

July,2010 – Rev 1.1  www.nem.com.tw    Page 5 


                                             NE1101A/B

Typical Operating Characteristics

y
nl
 
 

O
PL
SA

 
r

 
Fo

 
 

July,2010 – Rev 1.1  www.nem.com.tw    Page 6 


                                             NE1101A/B
 
Typical Operating characteristics

y
 

nl
 

O
PL
SA

 
 
r
Fo

 
 

July,2010 – Rev 1.1  www.nem.com.tw    Page 7 


                                             NE1101A/B
Typical Operating characteristics

y
nl
O
PL
SA

 
 
r
Fo

 
 
 

July,2010 – Rev 1.1  www.nem.com.tw    Page 8 


                                             NE1101A/B
Typical Operating characteristics

y
nl
O
PL
r SA
Fo

 
 
 
 

July,2010 – Rev 1.1  www.nem.com.tw    Page 9 


                                             NE1101A/B
Typical Operating characteristics

y
 

nl
Operation Description:

HV Startup
The NE1101 contains an extremely low leakage
High Voltage switch inside pin1 for low power
O The HV switch is activated again whenever the
Vcc voltage drops to 5.6V as shown in Fig.2 for short
PL
dissipation startup function. circuit condition. In this situation, the internal logic is
reset and HV switch turned on to charge up the Vcc
capacitor to 12.6V for start up the controller again. See
also the description in Over Current Protection section.
SA

HV
Current
r
Fo

12.6V

Vcc
5.6V

Figure 1
Short
Start-up
circuit

In Figure 1, when a high voltage of 120VDC-


400VDC is applied to HV (pin8), the internal HV switch Figure 2
turns ON and connects a 3.1mA current source to Pin6
(Vcc). The capacitor at Vcc pin is charged up till it SoftStart
reaches 12.6V UVLO(ON) level that the controller
starts operation. The HV switch is then turned Off to Softstart function is internally fixed at 2.5ms.
reduce the power dissipation in the startup circuit. It When Vcc reaches 12.6V level, the controller starts
will remain Off during normal operation. The leakage up and performs a softstart immediately.
current of the HV switch is less than 20uA typically for In Figure 5, the softstart circuit overrides the 1V
minimum power loss. peak current limit and ramp up the current limit from
After the controller is started up, the Vcc zero to 1V in 2.5ms. The softstart is also activated
subsequently draws power from the transformer whenever the controller performs a Vcc recycled or
auxiliary winding to continue the operation. . . re-start operation.

July,2010 – Rev 1.1  www.nem.com.tw    Page 10 


                                             NE1101A/B
PFC_Vcc
The NE1101A/B features a PFC bias output pin
which can provide power source to the external PFC
controller or other circuits.
As shown in Figure 3 is the internal circuitry of pin1.
The PFC_Vcc and Vcc pins are connected internally
by a low impedance PFC switch. This switch is current
limited to 35mA and capable of biasing an external
PFC controller. A 0.1uF decoupling capacitor is
recommended to be placed near to the Vcc pin of the
PFC controller.

Figure 4

y
Current Sense
The CS (pin 3) is used for sensing the switching

nl
current for current mode control. The switching
current information is sensed across the Rs resistor,
which is connected to the source terminal of the

Figure 3
O
Mosfet. (Figure 5). This signal is compared with
1/3*FB voltage for generatng the PWM output. In
addition, the CS pin is internally clampped to 1V level
and thus for maximum power, the value of Rs can be
PL
calculated as 1V/(Ipeak).
The PFC switch is disabled during softstart To prevent sub-harmonic oscillation when the
although the FB feedback voltage is much higher than power supply operates in continuous current mode at
the 1.20V (Vstby-out) level which PFC switch suppose greater than 50% duty cycle, an internal slope
to turn ON normally. The switch will turn ON after the compensation is added by injecting sawthooth
controller completes the softstart and the power supply waveform of 2.3Vpeak to CS pin via an 18K resistor.
SA

output voltage enters regulation. (Figure 4)


The PFC switch is disabled automatically when
the power supply enters burst mode with feedback
voltage (FB pin) is below 0.72V (Vburst) under light load
condition. To prevent momentarily load changes from
causing error operation, a time delay is added such
r

that the PFC switch is disabled after the feedback


Fo

voltage (FB pin) drops below 0.72V for 100ms (TDEL)


When the output load increases, the PFC switch
turns ON as soon as FB voltage rises above 1.20V
(VSTBY-OUT). See Figure 4.     
The PFC_Vcc pin can be left floating if it is 
not used
Figure.5

July,2010 – Rev 1.1  www.nem.com.tw    Page 11 


                                             NE1101A/B
Leading Edge Blanking
The current signal at CS (pin3) consists of large
turn-on current spike due to discharge of stray
capacitances when the Mosfet turns on. If the
amplitude of the spike is higher than the peak
switching current of the Mosfet, it will result in the
controller turns off the PWM output prematurely and
cause unstable operation. In Figure 5, a 200ns
leading edge blanking circuit is added in the CS path
to mask out the initial 200ns spike and allow the
controller to sense the correct peak current information
internally.
Figure 7

Latch protection Feedback Voltage

y
Latch off protection can be implemented by In typical applications, the power supply output
pulling CS (pin3) higher than 3V during the PWM off voltage is sampled and compared with a reference

nl
time. When the latch protection is triggered, the voltage in the secondary side. The error between
controller terminates the PWM output immediately, the these two voltages is sent to the NE1101A/B via an
PFC bias output (pin1) is shutdown and the controller isolation opto coupler connected to the FB (pin2) of the
stops operation as long as Vcc is above 4.7V, the
voltage level at which the controller resets the internal
logic.
Figure 6 shows an example on using the Latch
function for Over Voltage protection. When the Vcc
O
NE1101A/B.
The FB pin is internally pull high by a 20K
resistor to the internal bias. This signal is scaled
down by a factor of three (V-) and sent to the inverting
input of the PWM comparator. (Figure 7). The
PL
rail voltage (or output voltage) is too high, the PNP non-inverting input of the comparator is connected to
transistor turns ON during the PWM off time and the peak current signal. During operation, the V-
applies a >3V voltage to the CS pin to latch off the signal sets the limit for the peak current signal. When
controller. This circuit does not affect the current the peak current reaches V- level, the internal logic
sense operation at CS pin since the PNP is turned turns off the PWM output for the rest of the swithcing
SA

OFF during the PWM On time. cycle. After which, the PWM resets and starts deliver
output in the next switching cycle (Figure 8)
This method can be used for protections that
require Latch off function, such as Over Temperature
protection.
r
Fo

Figure 8

The NE1101A/B relies on the FB voltage level to


determine the loading condition. In Figure 7, the FB
Figure 6 signal is sent to two comparators whose thresholds
are fixed at 0.72V and 1.20V for Burst and Normal
mode operations respectively.

July,2010 – Rev 1.1  www.nem.com.tw    Page 12 


                                             NE1101A/B
Under light load, the FB voltage will decrease in For momentarily transient load which the CS
order to reduce the power deliver to the output. When signal falls below 1V before the 100ms timer expires,
FB voltage fells below 0.72V (VBurst), the controller the controller will reset the timer and resumes normal
enters burst mode to maintain high efficiency swiching operation.
operation. (See figures 7 and 9). When this occurs, an
100ms timer is activated. To prevent uncessary
disruption of PFC bias due to momentarily load Driver output
changes, the PFC_Vcc is turned off only after the timer The NE1101A/B output is capable of delivering
expires. After which, the FB voltage oscillate at gate drive current that reaches rise time of 28ns and
0.72V±5% level as long as the output load is light.. fall time of 24ns measured with a 1nF capacitive load.
When the load increases, the FB voltage will rise Its output voltage is clamped to 14.3V to protect the
up to provide more power to the output. When FB gate terminal of the external Mosfet and improve the
voltge rises above 1.20V, the controller exits burst and reliablity of the power supply.
resume normal operation. The PFC_Vcc begins to
provide bias output immediately.

y
nl
Over current protection
The NE1101A/B uses a timer function to
differentiate Over current and momentarily large
current transient conditions.
When over current occurs, the CS signal hwill rise
to the 1V max limit and trigger a timer circuit. If the CS
signal continues to hit the 1V limit for 100ms, the
controller confirms the over current situation and turns
O
PL
off the PWM output. The Vcc supply to the controller
will start dropping since the switching operation is Figure 10
halted.
When the Vcc decreases to 7.5V UVLO Off
threshold, the controller enters deep sleep mode in Frequency Jittering
SA

which it will shutdown the internal functions further to The build-in frequency jittering function spreads
reduce its operation current down to 520uA (typical). the EMI spectrum and result in lower noise amplitudes.
The Vcc decreases at much slower rate, which helps This features helps power designers meet the EMI
to cut down the auto-retry power dissipation further. requirements easier and at same time reduce the cost
When Vcc drops to 4.7V, the internal logic reset, the on EMI components. As shown in Figure 10 for
controller turns on the HV switch to charge the Cvcc NE1101B (65KHz), the switching frequency is
r

capacitor to 12.5V UVLO On level and performs a modulated by +/-6.4% at interval of 5ms. The
softstart subsequently. If the over current situation jittering function is disabled when the controller enters
Fo

persists and CS signal continues to hit 1V max peak Burst mode under light load condition.
current limit for 100ms timing delay, the above
operation will repeat continusouly.

July,2010 – Rev 1.1  www.nem.com.tw    Page 13 


                                             NE1101A/B

y
nl
O
PL
r SA
Fo

Figure 9 Timing diagram for Softstart, Burst and Overload protection

July,2010 – Rev 1.1  www.nem.com.tw    Page 14 


                                             NE1101A/B

Typical Application: 12V output, 40W design

y
nl
O
PL
SA

This is an application circuit that can deliver 12V, 40W power with all the protections such as OVP (latch), OTP
(latch), OCP. Its AC input voltage is 90-270VAC. The open load standby power is 100mW and average
efficiency is 87.15% with 230VAC input. Please contact NEM for evalaution board.
r
Fo

July,2010 – Rev 1.1  www.nem.com.tw    Page 15 


                                             NE1101A/B

SO8 Package Outline Dimensions

y
nl
O
PL
r SA
Fo

July,2010 – Rev 1.1  www.nem.com.tw    Page 16 


                                             NE1101A/B
Tape and Reel Dimensions for SO8

y
nl
O
PL
r SA
Fo

July,2010 – Rev 1.1  www.nem.com.tw    Page 17 


                                             NE1101A/B

DIP8 Package Outline dimensions

y
nl
O
PL
r SA
Fo

July,2010 – Rev 1.1  www.nem.com.tw    Page 18 


                                             NE1101A/B
Tude Dimensions for DIP8

y
nl
O
PL
r SA
Fo

July,2010 – Rev 1.1  www.nem.com.tw    Page 19 


                                             NE1101A/B

CONTACT INFORMATION

Web : www.nem.com.tw
Email : sales@new.com.tw
Phone : 886-3-5526818
Fax : 886-3-5526819
Address: NeoEnergy Microelectronics, Inc.
6F-01, No.26, Tai Yuen St, Chupei City
Hsinchu County, Taiwan 30288

y
nl
DISCLAIMERS

General
O
Information in this documented is believed to be accurate and reliable. NEM dos not give any representations
or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no
PL
liability for the consequences of use of such information

Right to make changes


NEM reserves the right to make changes in this document at any time without notice. This document
supersedes and replaces all prior information provided. Customers should obtain the latest information from
NEM when placing orders and should verify that such information is current and complete.
SA

Suitablility for use


NEM products are not designed, authorized or warranted to be suitable for use in medical, military, aircrft, space
or life support equipment, nor in applications where failure or malfunction of an NEM products can be expected to
result in personal injury, dealth or severe property or environmental damages. NEM accepts no liability and the
use of NEM products in such applications are at customer’s own risk.
r
Fo

July,2010 – Rev 1.1  www.nem.com.tw    Page 20 

You might also like