A Fresh Look at UVM

and the New UVM Cookbook

Tom Fitzpatrick
Verification Evangelist
IEEE1800.2 Member
info@verificationacademy.com | www.verificationacademy.com
© 2017 Mentor Graphics Corporation
 UVM Has Its Roots in Mentor

e eRM uRM IPCM uVC

Vera RVM VMM VMM1.0 1.0.1 1.1 1.2 1.2.1

UVM 1.0 1.1

OVM 1.0 1.1 2.0 2.1 2.1.1

SV AVM1 AVM2 AVM3

AVM3

© 2017 Mentor Graphics Corporation

 UVM Has Its Roots in Mentor

uRM IPCM uVC

1800.2-2017

VMM1.0 1.0.1 1.1 1.2 1.2.1

1800.2
UVM 1.0 1.1 1.2 Ref Impl

OVM 1.0 1.1 2.0 2.1 2.1.1

AVM1 AVM2 AVM3

AVM3

© 2017 Mentor Graphics Corporation

What's Actually Happening?

© 2017 Mentor Graphics Corporation

Who's in Charge?
Accellera UVM-WG IEEE 1800.2 WG

• Owns UVM Reference • Owns UVM Standard

Implementation • Documents user-facing API
• Reference Guide • Theoretically supports alternate
documents the library implementations
• Vehicle for testing • Proposed enhancements
enhancements prototyped by Accellera

© 2017 Mentor Graphics Corporation

UVM Registers Update
• Flexible register addressing uvm_reg_blk top

• Reg can appear in map > once uvm_reg_map t_m1 uvm_reg_map t_m2

• Map can have >1 parent map 0x0000 0xCA00

• Address defined by injection point

uvm_reg_map m2
and access path uvm_reg_map m1

• Allow remapping of regs 0x008 0xF08 0x002

regA
• unlock_model() uvm_reg_blk blk

• Add access rights to uvm_reg_map

• Add indirect register map
• Add burst_write/read methods to uvm_reg_block
• uvm_reg now factory enabled
© 2017 Mentor Graphics Corporation
Other 1800.2 Changes from 1.2
• Added accessor methods all over the place
• Factory Updates
• Added methods/macros for abstract object/component
factory registration
• Typename aliasing for factory
• Reorganized uvm_printer policy class
• New `uvm_do macro
• Replaces all `uvm_do* variants

© 2017 Mentor Graphics Corporation

 Cleaning up Macros
`uvm_do(SEQ_OR_ITEM)
`uvm_do_pri(SEQ_OR_ITEM, PRIORITY)
`uvm do with(SEQ OR ITEM, CONSTRAINTS)
`uvm_do_pri_with(SEQ_OR_ITEM, PRIORITY,
CONSTRAINTS)
`uvm_do(SEQ_OR_ITEM,
SEQR=get_sequencer(),
`uvm_do_on(SEQ_OR_ITEM, SEQR)
PRIORITY=-1,
`uvm_do_on_pri(SEQ_OR_ITEM, SEQR,
CONSTRAINTS={})
PRIORITY)
`uvm_do_on_with(SEQ_OR_ITEM, SEQR,
CONSTRAINTS)
`uvm_do_on_pri_with(SEQ_OR_ITEM,SEQR,
PRIORITY, CONSTRAINTS)
• Will be preserved by Accellera
• We’ve always told you not to use these

© 2017 Mentor Graphics Corporation

 Review: Sequence/Driver Handshake
my_seq1 driver
start_item(req); get_next_item(req);

finish_item(req);
item_done();

task body();
req = req_t::type_id::create(“req”);
for_int i = 0; i < num; i++) begin
start_item(req, pri, agent.seqr);
if(!req.randomize()) begin
`uvm_error(“body”, “rand failure”)
end
finish_item(req);
`uvm_info(“my_seq1”,req.convert2string());
end
endtask
task run_phase(uvm_phase phase);
forever begin
seq_item_port.get_next_item(req);
drive_item2bus(req);
seq_item_port.item_done();
end
endtask
If driver updates req with
response information
© 2017 Mentor Graphics Corporation
Solving the UVM "Blank Page" Problem
• Accelerate environment development
• Better environments in less time
• Reusable
• Across projects, sites
• Scalable
• Across design size, complexity,
and target technology
• Emulatable
• Same environment and stimulus
© 2017 Mentor Graphics Corporation
UVM Framework Gets You Going
• UVM Jumpstart
• Reduces barrier to entry for UVM at no cost!
• Be immediately productive while learning UVM
• Focus efforts on verifying custom design
• UVM with Questa on Linux or Windows
• UVM Reuse methodology
• Allows team to focus on verifying product features
• Horizontal reuse of components across projects
• Vertical reuse of environments from block to top
• Start in simulation and reuse in emulation
• Automatic Code Generation
• Interface/environment/bench templates

© 2017 Mentor Graphics Corporation

UVM Framework is All About Reuse
• Complete Home
• DUT-specific Bench & Stimulus
• Completed Rooms
• Interface & Env Packages
• Pre-Fabricated Rooms
• UVM Use-Model & Methodology
• Building Supplies
• Common Verification Building
Blocks
• Raw Materials
• Abstract Programming Language
© 2017 Mentor Graphics Corporation
The UVM Framework Contents
• Class library
• Defines reuse methodology
• Component base classes
• Package structure for reuse
• Scripts
• Auto generation of components and test bench
• Makefiles with common tool flow operations
• Examples
• Block and chip level benches
• Technology integrations
• Documentation
• Users Guide

© 2017 Mentor Graphics Corporation

 How Does UVMF Work?
• Generate complete code base for
• Interface package Output
• Environment package Input File Files
• Project bench Configuration Code Generator Package Declaration

Class definitions

Interface definitions

• Generates operational simulation UVM Templates File Lists

• Engineer incrementally adds design
Makefile
specific content to a working simulation

© 2017 Mentor Graphics Corporation

 "Traditional UVM"
Sequencer Driver DUT
sequence
task body();
req = req_t::type_id::create(“req”);
for_int i = 0; i < num; i++) begin
start_item(req);
if(!req.randomize()) begin
`uvm_error(“body”, “rand failure”)
end
finish_item(req); task run_phase(uvm_phase phase);
end forever begin
endtask seq_item_port.get_next_item(req);
interface dut_if;
bus.addr = req.addr;
wire clk;
bus.data = req.data;
logic req;
bus.req = 1'b1;
logic ack;
@(bus.clk iff bus.ack == 1'b1)
logic [31:0] addr;
seq_item_port.item_done();
logic [31:0] data;
end
endinterface
endtask
© 2017 Mentor Graphics Corporation
 UVM Framework Arranged for Efficiency
Sequencer Driver DUT
sequence (Proxy)
task body(); interface dut_bfm(dut_if bus);
req = req_t::type_id::create(“req”); task access(req_t req);
for_int i = 0; i < num; i++) begin
start_item(req);
if(!req.randomize()) begin
`uvm_error(“body”, “rand failure”)
end endtask
finish_item(req); task run_phase(uvm_phase phase);
forever begin endinterface
end
endtask seq_item_port.get_next_item(req);
interface dut_if;
bus.addr = req.addr;
bfm.access(req);
wire clk;
bus.data = req.data;
logic req;
bus.req = 1'b1;
logic ack;
@(bus.clk iff bus.ack == 1'b1)
logic [31:0] addr;
seq_item_port.item_done();
logic [31:0] data;
end
endinterface
endtask
© 2017 Mentor Graphics Corporation
UVM Framework is Emulation-Ready!
Sequencer Driver DUT
sequence (Proxy)

Runs on Simulator Runs on

Emulator
• Automatically partitions design and testbench
• Supports both simulation and emulation

© 2017 Mentor Graphics Corporation

The Need for Speed – Enter Emulation

Faster Bring-up

Users demand the best from both worlds

Rising performance challenges

Simulation More Speed! More
fromFunctionality Emulation
block/IP to sub-system
to full chip/SoC

Testbench Reuse

© 2017 Mentor Graphics Corporation

 UVM Framework is Emulation-Ready!
Scoreboard
Test
Controller
Coverage
Untimed
Monitor Monitor
(Proxy) (Proxy)

Sequencer Slave
Driver DUT Responder
sequence (Proxy) (Proxy) sequence

Emulator Transactions
© 2017 Mentor Graphics Corporation
 UVM Acceleration Flow Summary
• Employ two distinct UVM and HDL top level modules
• UVM (or HVL or TB) top must be untimed; HDL top must be synthesizable for emulation
- DUT, pin interfaces, and clock/reset logic can be largely preserved
- Upper testbench layers should remain (largely) unaffected
• Separate file lists for compilation required too!
• Split UVM agent drivers and monitors into untimed UVM proxies and timed HDL BFMs
• BFMs are modeled as SV interfaces accessing separate SV pin interface
- Implemented using implicit FSMs and other XRTL constructs
- Used for testbench-HDL binding instead of (virtual) pin interfaces
• Proxies encapsulate intra-transactor communication
- Hide BFM tasks and functions which are visible only to the proxy
- Represent interface to upper UVM testbench layers (remains unchanged)
- Are generally light-weight, implementing basic threads to pass generated UVM stimulus to HDL side,
and observed HDL responses back to UVM side
• Transaction objects must be converted to/from synthesizable BFM task and function arguments
- Internal to UVM proxies, e.g. using “to_struct” and “from_struct” methods
• Tune emulation-ready testbench for optimal performance
• Profiling and analysis to minimize s/w overhead and maximize h/w frequency
- Reactive vs. streaming, inbound vs. outbound, one-way vs. two-way, concurrency © 2017 Mentor Graphics Corporation
Common Debug from Simulation to Emulation
Visualizer
Visualizer

• Maximize performance without sacrificing ease-of-use

• Same unified debugger for pure simulation and acceleration
• Questa running testbench and Veloce running HDL domain with DUT
• Emulator savvy, easy, powerful and FAST
© 2017 Mentor Graphics Corporation
UVMF Brings Everything Together
• Verification IP • Verification Run Manager
• Environments with AMBA, • Automated regression
PCIe, USB, Ethernet QVIP management
• Graph-based testing • Vista
• SystemC model of ALU
• Accelerated coverage example
closure
• Visualizer
• inFact testbench import to
• Generates visualizer
create protocol sequences database
• Verification Management • Emulation
• Coverage ranking, merging, • TB structure is emulation
reporting compliant

© 2017 Mentor Graphics Corporation

UVMF Brings Everything Together
• Verification IP • Verification Run Manager

• Graph-based testing • Vista

• Visualizer

• Verification Management • Emulaton

© 2017 Mentor Graphics Corporation

Updating the UVM Cookbook
• 1800.2 Compliant
• Updated examples
• Transition from 1.1d and 1.2
• Emulation-Friendly
• Both “E-F” and “Classic”
use-models discussed
• Updated UVM Video Course
• Targeting early 2018
• 290,000 views and counting!
© 2017 Mentor Graphics Corporation
Mentor & Verification Academy
• Will continue to be your one-stop shop for UVM
and all things Verification
• 44,700 subscribers
• 22,500 replies
• 8,200 questions
• Video courses on UVM and everything else
• Portable Stimulus and Testbench Automation
• Simulation, Emulation, Formal, etc.
• Your Success is Our Goal
© 2017 Mentor Graphics Corporation
 A Fresh Look at UVM
and the New UVM Cookbook
Tom Fitzpatrick
Verification Evangelist
IEEE1800.2 Member
info@verificationacademy.com | www.verificationacademy.com
© 2017 Mentor Graphics Corporation