2b617f4cbf09d03dac573b44463 7ac8e54d 1cd2e0

Application Note, V1.
1, October 2009
EVALPFC2-ICE2PCS01
300W PFC Evaluation Board with CCM PFC
controller ICE2PCS01
Power Management & Supply
N e v e r s t o p t h i n k i n g .
Edition 2009-10-13
Published by Infineon Technologies Asia Pacific,
168 Kallang Way,
349253 Singapore, Singapore
© Infineon Technologies AP 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon
Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of
that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices
or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect
human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
EVALPFC2-ICE2PCS01
Revision History: 2009-10 V1.0

Previous Version:
Page Subjects (major changes since last revision)
9&10 Capacitor CX1 size changed
300W PFC Evaluation Board with CCM PFC controller ICE2PCS01 AN-PS0010
License to Infineon Technologies Asia Pacific Pte Ltd
Liu Jianwei
Luo Junyang
Jeoh Meng Kiat
We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
ap-lab.admin@infineon.com
3
Table of Content
1 Content................................................................................................................. 5
2 Evaluation Board ................................................................................................ 5
3 Technical Specifications .................................................................................... 6
4 Circuit Description.............................................................................................. 6
5 Circuit Operation................................................................................................. 6
6 Circuit Diagram ................................................................................................... 8
7 PCB Layout Top Layer ....................................................................................... 9
8 PCB layout Bottom Layer................................................................................. 10
9 Component List................................................................................................. 11
10 Boost Choke Layout ....................................................................................... 122
11 Test report ......................................................................................................... 12
11.1 Load test (table and figure).............................................................................. 12
11.2 Harmonic test according to EN61000-3-2 Class D requirement .................. 14
11.3 Test Waveforms ................................................................................................ 15
12 References:........................................................................................................ 16
4
1 Content
The evaluation board described here is a 300W power factor correction (PFC) circuit with 85~265VAC
universal input and 393VDC fixed output. Boost converter topology is employed in this board. The
continuous conduction mode (CCM) PFC controller ICE2PCS01 is employed in this board to achieve
the unity power factor. The switching frequency is programmable by external resistor at one pin.
There are various protection features incorporated to ensure safe system operation conditions. The
device has a unique soft-start function which limits the start up inrush current thus reducing the stress
on the boost diode. To improve the efficiency, the third generation CoolMOS™ is used as the power
switch due to its lowest area specific Rdson. High voltage Silicon Carbide (SiC) Schottky diode
thinQ!™ is used as PFC boost diode. Because of its ideal reverse recovery behavior, SiC Schottky
diode is extremely suitable for high frequency CCM PFC application.
2 Evaluation board
5
3 Technical specifications:
Input voltage 85VAC~265VAC
Input frequency 50Hz
Output voltage and current 393VDC, 0.75A
Output power ~ 300W
Efficiency >90% at full load
Switching frequency 62.5kHz (with R8=76K)
4 Circuit Description
Line Input
The AC line input side comprises the input fuse F1 as over-current protection. The high frequency
current ripple is filtered by R1, L1 and CX1. The choke L2, X2-capacitors CX1 and CX2 and Y1-
capacitor CY1 and CY2 are used as radio interference suppressors. RT1 is placed in series to limit
inrush current during each power on.
Power Stage − Boost Type PFC Converter

After the bridge rectifier BR1, there is a boost type PFC converter consisting of L3, Q1, D1 and C2.
The third generation CoolMOS™ is used as the power switch Q1. Due to its low Rdson, the small
heat sink can fulfill the dissipation requirement. SiC Schottky diode thinQ!™ is used for D1. As SiC
Schottky diode does not show a reverse recovery behavior, the stress on the MOSFET will be
reduced due to very low current spike during turn on transient. Simultaneously higher reliability of the
entire system can be achieved. However, due to the poor pulse current capability of SiC Schottky
diode, a standard diode D2 is necessary to bypass the high inrush current during each power on
transient. Output capacitor C2 provides energy buffering to reduce the output voltage ripple (100Hz)
to the acceptable level.
PWM control of Boost Converter

The PWM control is realized by 8-Pin CCM PFC IC ICE2PCS01. Unlike the conventional PFC
controller, ICE2PCS01 does not need direct sine wave reference signal. The switching frequency is
fixed and programmed by R8. There are two control loops in the circuit, voltage loop and current loop.
The output voltage is sensed by the voltage divider of R5A, R5B, R6A and R6B and sent to internal
error amplifier. The output of error amplifier is used to control current in the inner current loop. The
compensation network C4, C5, R7 constitutes the external circuitry of the error amplifier. This circuitry
allows the feedback to be matched to various load conditions, thereby providing stable control. In
order not to make the response for 100Hz ripple, the voltage loop compensation is implemented with
low bandwidth. The inner loop, current control loop, is implemented with average current mode
strategy. The instant current is adjusted to be proportional to both of MOSFET off duty DOFF and the
error amplifier output voltage of voltage loop. The current is sensed by shunt resistors R2, R2A and
R2B and fed into IC through R9. The current sense signal is averaged by an internal operating
amplifier and then processed in the PWM generator which drives the gate drive. The averaging is
realized by charging and discharging an external capacitor C7.
The IC supply is provided by external voltage source and filtered and buffered by C8 and C9. The IC
output gate driver is a fast totem pole gate drive. It has an in-built cross conduction current protection
and a Zener diode to protect the external transistor switch against undesirable over voltages. The
gate drive resistor R4 is selected to limit and gate pulse current and drive MOSFET for fast switching.
5 Circuit Operation
Soft Start
When Vcc pin is higher than turn-on threshold, typical 11V, PFC is going to start. The unique soft start
is integrated. Input current keeps sinusoidal and is increasing gradually until output voltage reaches
6
75% of rating. Because the peak current limit is not activated, the boost diode is not stressed with
large diode duty cycle under high current.
Enhanced Dynamic Response

Due to inherent low bandwidth of PFC dynamic, in case of load jump, regulation circuit can not
response fast enough and it will lead to large output voltage overshoot or drop. To solve this problem
in PFC application, enhance dynamic response is implemented in the IC. Whenever output voltage
exceeds by ±5%, it will bypass the slow compensation operating amplifier and act on the nonlinear
gain block to affect the duty cycle directly. The output voltage can be recovered in a short time.
Protection Features
a. Open loop protection (OLP) / Mains under voltage protection
The open loop protection is available for this IC to safe-guard the output. Whenever VSENSE voltage
falls below 0.6V, or equivalently VOUT falls below 20% of its rated value, it indicates an open loop
condition (i.e. VSENSE pin not connected). In this case, most of the blocks within the IC will be
shutdown. It is implemented using a comparator with a threshold of 0.6V. Insufficient input voltage VIN
will also trigger this protection.
b. Output over-voltage protection
Output over-voltage protection is also available by the same integrated blocks of enhanced dynamic
response. Whenever VOUT exceeds the rated value by 5%, the over-voltage protection OVP is active.
This is implemented by sensing the voltage at pin VSENSE with respect to a reference voltage of 3.15V.
A VSENSE voltage higher than 3.15V will immediately reduce the output duty cycle even down to zero,
bypassing the normal voltage loop control. This results in a lower input power and the output voltage
VOUT is reduced.
c. Soft over current control (SOC) and peak current limit

When the amplitude of current sense voltage reaches 0.68V, Soft Over Current Control (SOC) is
activated. This is a soft control does not directly switch off the gate drive but acts on the internal
blocks to result in a reduced PWM duty cycle.
The IC also provides a cycle by cycle peak current limitation (PCL). It is active when the voltage at
current sense voltage reaches -1.04V. The gate output is immediately off after 300ns blanking time.
d. IC supply under voltage lock out

When VCC voltage is below the under voltage lockout threshold VCCUVLO, typical 11V, IC is off the
gate drive is internally pull low to maintain the off state. The current consumption is down to 200uA
only.
7
6 Circuit Diagram
1 2 3 4
D D2 D
1N5408
R1 L3 D1
BR1
120ohm RT1 SDP04S60
F1 8A, 400V 1.24mH 390V/300W
5A S237/5 Vo
L2
L Q1
L1 SPP20N60C3
40uH CX1 CX2
85~265VAC VAR1 2*3.9mH C2
S10K275 C1
0.47u/275V 0.47u/275V
N 0.1u/630V
R2 R3
CY1
CY2 0.33/1W 10k
2.2nF, Y2, 250V Gnd
2.2nF, Y2, 250V
C Earth R2A C
0.22/1W
R5
R2B 390k, 1%
0.22/1W
R9 R4 R5A
220 3.3 390k, 1%
3
IC?
I-Sense 8
Gate
7
Vcc
ICE2PCS01
B Vsense 6 B
2 I-Comp
V-Comp 5
Freq GND
R7
Vcc C4 C3 R6 R6B
33k
C9 0.1uF 15k,1%
4
C8 10k, 1%
C7 C5 0.1uF
R8
47u/25V 0.1u 76k 1uF
4.7nF
GND
A A
1 2 3 4
8
7 PCB layout top layer
9
8 PCB layout Bottom:
10
9 Component List:
Designator Part Type Description Manufacturer / Part No.

BR1 8A, 400V Bridge Rectifier Vishay / KBU8G
C1 0.1uF/630V Ceramic Cap Epcos / B32652A6104J
C2 220uF/450V Electrolytic Cap Epcos / B43304C5227M
C3 0.1uF/50V Ceramic Cap Murata / RPER71H104K2K1A03B
C5 1uF/50V Ceramic Cap
C7 4.7nF/50V Ceramic Cap
C9 47uF/25V Electrolytic Cap
CX1 0.47uF, X1, 305V Ceramic Cap Epcos / B32922C3474M
CX2 0.47uF, X1, 305V Ceramic Cap Epcos / B32922C3474M
CY1 2.2nF, Y2, 250V Ceramic Cap Epcos / B81123C1222M000
CY2 2.2nF, Y2, 250V Ceramic Cap Epcos / B81123C1222M000
Connector
D1 SDT04S60 Diode
D2 1N5408 Diode Vishay / 1N5408
F1 5A Fuse
Fuse Holder
IC1 ICE2PCS01 Infineon
JP1 12.5mm, Ф0.7mm Jumper
JP2 20mm, Ф0.7mm Jumper
JP3 12mm, Ф1.2mm Jumper
JP4 17.5mm, Ф0.7mm Jumper
L1* Shorted
L2 2*3.9mH CM Choke Epcos / B82725J2602N20
L3 1.24mH Choke
Q1 SPP20N60C3 Power MOSFET Infineon
Heat Sink
TO220 Clip
TO247 Clip
TO220 Isolation Pad
3mm Screw
R2 0.33/1W, 5% Metal Film Resistor
R2A 0.22/1W, 5% Metal Film Resistor
R2B 0.22/1W, 5% Metal Film Resistor
R3 10k/0.25W, 5% Carbon Film Resistor
R4 3.3/0.25W, 5% Carbon Film Resistor
R5A 390k/0.25W, 1% Carbon Film Resistor
R5B 390k/0.25W, 1% Carbon Film Resistor
R6A 10k/0.25W, 1% Carbon Film Resistor
R6B 15k/0.25W, 1% Carbon Film Resistor
R9 220/0.25W, 5% Carbon Film Resistor
RT1 S237/5 NTC Thermistor Epcos / B57237S509M
VAR1 S10K275 Varistor Epcos / B72210S271K101
11
10 Boost Choke Layout
Core: CS468125 toriod Turns: 83
Wire: 1 x Φ1.0mm, AWG19 Inductance: L=1.24mH
11 Test report
11.1 Load test (table and figure):

Vin Pout
(VAC) Pin (W) Iin (A) Vout (V) Iout (A) (W) efficiency PF
320 3.8 393 0.75 294.75 92% 1
211 2.51 393 0.5 196.5 93% 1
165 1.96 393 0.4 157.2 95% 1
124 1.47 393 0.3 117.9 95% 0.99
83 0.99 393 0.2 78.6 95% 0.99
43 0.52 394 0.1 39.4 92% 0.97
31 0.39 394 0.075 29.55 95% 0.95
20.3 0.26 395 0.049 19.355 95% 0.91
12.2 0.17 396 0.029 11.484 94% 0.87
85 4.2 0.07 396 0.01 3.96 94% 0.71
316 2.9 393 0.75 294.75 93% 1
208 1.91 393 0.5 196.5 94% 0.99
163 1.5 393 0.4 157.2 96% 0.99
123 1.13 393 0.3 117.9 96% 0.99
83 0.77 393 0.2 78.6 95% 0.98
42.3 0.4 393 0.1 39.3 93% 0.94
30 0.29 394 0.0718 28.2892 94% 0.89
22 0.22 394 0.0525 20.685 94% 0.86
14.2 0.15 394 0.034 13.396 94% 0.82
110 6.2 0.076 394 0.014 5.516 89% 0.63
307 1.4 394 0.75 295.5 96% 0.99
204 1 394 0.5 197 97% 0.99
161 0.8 394 0.4 157.6 98% 0.97
120 0.63 394 0.3 118.2 99% 0.95
82 0.45 394 0.2 78.8 96% 0.92
41 0.29 394 0.1 39.4 96% 0.83
29.5 0.16 395 0.072 28.44 96% 0.77
21.7 0.133 395 0.053 20.935 96% 0.67
14 0.1 395 0.033 13.035 93% 0.53
220 6 0.093 395 0.014 5.53 92% 0.22
265 305 1.2 394 0.75 295.5 97% 0.99
203 0.79 394 0.5 197 97% 0.98
161 0.63 394 0.4 157.6 98% 0.97
120 0.48 395 0.3 118.5 99% 0.95
81 0.34 395 0.2 79 98% 0.91
41 0.21 395 0.1 39.5 96% 0.73
12
29.5 0.17 395 0.072 28.44 96% 0.64
21.7 0.16 395 0.053 20.935 96% 0.45
13.8 0.15 395 0.033 13.035 94% 0.38
5.83 0.1 395 0.014 5.53 95% 0.15
98.0%
96.0%
300W Load
Efficiency
94.0%
200W Load
150W Load
92.0%
80W Load
90.0%
88.0%
85 110 220 265
Input Voltage (V)
1
0.9
0.8
0.7
0.6 85VAC
110VAC
PF
0.5
230VAC
0.4
265VAC
0.3
0.2
0.1
0
0 50 100 150 200 250 300
Pout (W)
13
11.2 Harmonic test according to EN61000-3-2 Class D requirement
85VAC, full load (300W output)
Iin
85VAC, 9% of full load (28W output)
Iin
265VAC, full load (300W output)
Iin
14
265VAC, 9% of full load (28W output)
Iin
11.3 Waveforms (soft start, load jump, open loop)
Soft start, test at 85VAC, Iout=0.2A
Iin
Vout
Vcc
Vcomp
Load jump test at 85VAC, Iout from 0A to 0.75A Load jump test at 85VAC, Iout from 0.75A to 0A
Vgate
Vgate
Vout
Vout
Iout
Iout
15
Open loop test at 265VAC, Iout=0.1A
Vgate
Iin
Vout
Vsense
12 References:
16
AADesign Guide for ICE2PCSxxApp
Application note, Ver 1.0, May 2008
Design Guide for Boost Type CCM PFC with

ICE2PCSxx
Power Management & Supply
N e v e r s t o p t h i n k i n g .
Edition 2008-08-01
Published by Infineon Technologies Asia Pacific,
168 Kallang Way,
349253 Singapore, Singapore
© Infineon Technologies AP 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee
of characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,
regarding circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types
in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express
written approval of Infineon Technologies, if a failure of such components can reasonably be expected to
cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or
system. Life support devices or systems are intended to be implanted in the human body, or to support
and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
Revision History: 2008-08 V1.0
Previous Version: none
Page Subjects (major changes since last revision)
Design Guide for Boost Type CCM PFC with ICE2PCSxx

License to Infineon Technologies Asia Pacific Pte Ltd AN-PS0029
Liu Jianwei
Luo Junyang
Jeoh Meng Kiat
We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mailto:ap-lab.admin@infineon.com
ICE2PCSxx
Table of Contents Page

1 Introduction ...................................................................................................................................5
2 Boost PFC design with ICE2PCXX ..............................................................................................7
2.1 Target specification .........................................................................................................................7
2.2 Bridge rectifier .................................................................................................................................7
2.3 Power MOSFET and Gate Drive Circuit .........................................................................................7
2.4 Boost Diode.....................................................................................................................................8
2.5 Boost inductor .................................................................................................................................9
2.6 AC line current filter.......................................................................................................................11
2.7 Boost Output Bulk Capacitance ....................................................................................................12
2.8 Current Sense Resistor.................................................................................................................12
2.9 Output voltage sensing divider......................................................................................................13
2.10 Frequency setting (only for ICE2PCS01)......................................................................................13
2.11 AC Brown-out Shutdown (only for ICE2PCS02) ...........................................................................14
2.12 IC supply .......................................................................................................................................15
2.13 PCB layout guide ..........................................................................................................................16
3 Voltage loop and current loop compensation..........................................................................17
3.1 How to achieve PFC function without sinusoidal reference sensing ............................................18
3.2 Current Loop Regulation and Transfer Function...........................................................................19
3.3 Voltage Loop Compensation.........................................................................................................22
3.4 Design Example ............................................................................................................................28
3.5 Vcomp and M1, M2 value at full load condition ............................................................................29
Application Note 4 2008-08-01

Abstract
ICE2PCS01/02 are the 2nd generation of Continuous Conduction Mode (CCM) PFC controllers, which
employ BiCMOS technology. Its control scheme does not need the direct sine-wave sensing reference
signal from the AC mains compared to the conventional PFC solution. Average current control is
implemented to achieve the unity power factor. In this application note, the design process for the boost PFC
with ICE2PCXX is presented and the design details for a 300W output power PFC with the universal input
voltage range of 85~265VAC are included.
1 Introduction
The Pin layout of ICE2PCS01 and ICE2PCS02 is shown in Figure 1.
GND 1 8 GATE GND 1 8 GATE
ICOMP 2 7 VCC ICOMP 2 7 VCC
ISENSE 3 6 VSENSE ISENSE 3 6 VSENSE
FREQ 4 5 VCOMP VINS 4 5 VCOMP
ICE2PCS01 ICE2PCS02
Figure 1 Pin Layout of ICE2PCS01 and ICE2PCS02
From the layout, it can be seen that most of Pins in ICE2PCS02 are the same as ICE2PCS01 except Pin 4.
In ICE2PCS01, Pin 4 is to set the switching frequency. However, for ICE2PCS02, Pin 4 is for AC brown out
detection and the switching frequency is fixed by internal oscillator at 65kHz. The typical application circuits
of ICE2PCS01 and ICE2PCS02 are shown in Figure 2 and Figure 3 respectively.

Rectifier
EMI Filter D1
L1 COUT
R1
T1 VOUT=400VDC
R2
VIN=85V ...265V AC RSENSE
R3
ISENSE GATE GND VSENSE
Auxiliary Supply VCC ICE2PCS01
ICOMP FREQ VCOMP
RFREQ R4
C1 C2 C3
Figure 2 Typical application circuit of ICE2PCS01
Rectifier
EMI Filter D1
L1 COUT
R1
T1 VOUT=400VDC
R2
VIN=85V ...265V AC RSENSE
R3
D2
ISENSE GATE GND VSENSE
R5 ICE2PCS02 VCC Auxiliary Supply
VINS ICOMP VCOMP
R4
R6 C1 C2 C3
C4
Figure 3 Typical application circuit of ICE2PCS02

2 Boost PFC design with ICE2PCXX
2.1 Target specification
The fundamental electrical data of the circuit are the input voltage range Vin, the output power Pout, the
output voltage Vout, the operating switching frequency fSW and the value of the high frequency ripple of the
AC line current Iripple. Table 1 shows the relevant values for the system calculated in this Application Note.
The efficiency at rated output power Pout is estimated to 91 % over the complete input voltage range.
Input voltage 85VAC~265VAC

Input frequency 50Hz
Output voltage and current 390VDC, 0.76A
Output power 300W
Efficiency >90% at full load
Switching Frequency 65kHz
Maximum Ambient temperature around PFC 70ºC
Table 1 Design parameter for the proposed design
2.2 Bridge rectifier
In order to obtain 300W output power at 85 V minimum AC input voltage, the maximum input RMS current is
Pout 300
I in _ RMS = = = 3.92 A (1)
Vin _ min ⋅ η 85 ⋅ 90%
and the sinusoidal peak value of AC current is
I in _ pk = 2 ⋅ I in _ RMS = 2 ⋅ 3.92 = 5.54 A (2)
For these values a bridge rectifier with an average current capability of 6A or higher is a good choice. Please
note here, that due to a power dissipation of approximately
PBR = 2 ⋅ VF ⋅ I in _ RMS = 2 ⋅ 1V ⋅ 3.92 A = 7.84W (3)
the rectifier bridge should be connected to an appropriate heatsink. Assuming a maximum junction
temperature TJmax of 125°C, a maximum ambient temperature TAmax of 70°C, the thermal junction-to-case
RthJC of approximate 2.5 K/W and the thermal case to heatsink RthCHS of approximate 1K/W, the heatsink
must have a maximum thermal resistance of
TJ max − T A max 125 − 70
RthHS _ BR = − RthJC − RthCHS = − 2.5 − 1 = 3.52 K / W (4)
PBR 7.84
2.3 Power MOSFET and Gate Drive Circuit
Due to the switch mode operation, the loss is only valid during the on-time of the MOSFET. The duty cycle of
the transistor in boost converters operating in CCM at minimum AC input RMS voltage is
Vin _ min 85
Don = 1 − = 1− = 0.782 (5)
Vout 390
Since rms-values have the same effect on a system as DC-values, it is possible to calculate a characteristic
duty cycle for the rms-value. Therefore, the on-state loss of the MOSFET in CCM-mode at a junction-
temperature of 125°C is
2
Pcond = I in _ RMS ⋅ Don ⋅ Rdson (125C ) (6)
the MOSFET switching loss can be estimated as
PSW = ( E on + E off ) ⋅ f SW (7)
where, Eon and Eoff are the switch-on and switch-off energy loss which can be found in MOSFET datasheet,
fSW is the switching frequency.
For 300W design, if SPP20N60C3 is used, the conduction loss is

Pcond = 3.92 2 ⋅ 0.782 ⋅ 0.42 = 5.05W
assuming the switching current is about 6A and gate drive resistance Rg=3.6Ω, then the switching loss is
PSW = (0.007mWs + 0.015mWs) * 65kHz = 1.43W
the total loss is

PMOS _ total = Pcond + PSW = 6.48W (8)
the required heatsink for the MOSFET is

RthHS _ MOS = − RthJC _ MOS − RthCHS = − 0.6 − 1 = 6.89 K / W (9)
PMOS _ total 6.48
RthCHS is the Rth of the insulation pad between MOSFET and heatsink.
Gate drive resistance is used to drive MOSFET as fast as possible but also keep dv/dt within EMI
specification. In this 300W example, 3.6Ω gate resistor is chosen for SPP20N60C3 MOSFET.
Beside gate drive resistance, one 10kΩ resistor is also commonly connected between MOSFET gate and
source to discharge gate capacitor.
2.4 Boost Diode

The boost diode D1 has big influence on the system’s performance due to the reverse recovery behaviour.
So the Ultra-fast diode with very low trr and Qrr is necessary to reduce the switching loss. The new diode
technology of silicon carbide (SiC) Schottky shows its outstanding performance with almost no reverse
recovery behaviour. The switching loss due to the boost diode can be ignored with SiC Schottky diode. Only
conduction loss is calculated as below.
Pdiode = VF ⋅ I in _ RMS ⋅ (1 − Don ) = 2V ⋅ 3.92 A ⋅ (1 − 0.782) = 1.71W (10)
To decide the current rating of a SiC diode, there is a rule of thumb - the SiC diode can handle output power
Pout of 100 W to120 W in a CCM-PFC-system per one rated ampere. For example, the SDT04S60 from
Infineon Technologies is rated at a forward current IF = 4 A, so it is capable for a system of Pout = 4*100 W
= 400 W system in minimum. Therefore, this diode should be suitable for the proposed design.
The required heatsink for boost diode is

RthHS _ diode = − RthJC _ diode − RthCHS = − 4.1 − 1 = 27.06 K / W (11)
Pdiode 1.71

The SiC boost diodes often have a poor surge current handling capability. Therefore a so called bypass
diode is necessary such as the diode D3 as Figure 4. For the proposed system, 1N5408 is suitable.
D3
Rectifier
L1 D1 COUT
R1
T1
R2
RSENSE
Figure 4 inrush current bypass diode
2.5 Boost inductor
The peak current that the inductor must carry is the peak line current at the lowest input voltage plus the high
frequency ripple current. The high frequency ripple current peak to peak, IHF, can be related to maximum
input power and minmum input voltage as equation below.
Pin _ max
I HF = k ⋅ 2 ⋅ (12)
Vin _ min
Where, k must be kept reasonably small, and is usually optimized in the range of 15% to 25% for cost
effective design based on the current magnetic component status. If k is too high, the larger AC input filter is
required to filter out this ripple noise. If k is too low, the value of the inductance is too large and leads to big
size of the magnetic core.
For example, we choose k = 22%, then,

Pin _ max
I HF = 22% ⋅ 2 ⋅ = 1 .2 A
Vin _ min
The peak current passing through inductor is
I HF 1 .2
I L _ pk = I in _ peak + = 5.54 + = 6.14 A (13)
2 2
The boost choke inductance must be
D ⋅ (1 − D ) ⋅ Vout
Lboost ≥ (14)
I HF ⋅ f SW
D=0.5 will generate the maximum value for the above equation.
0.5 ⋅ (1 − 0.5) ⋅ 390V
Lboost ≥ = 1.25mH
1.2 A ⋅ 65kHz
The magnetic core of the boost choke can be either magnetic powder or ferrite material.
(1) sendust powder toroid core

The required effective magnetic volume of the core, Ve, is
I L _ pk 6.14 A 2
Ve ≥ µ r µ 0 Lboost ( ) 2 = 125 ⋅ 1.257 e − 6 ⋅ 1.25mH ( ) = 11.6e − 6m 3 = 11.6cm 3 (15)
Bmax 0.8T
where, µ r is the relative permeability of the material. It should be noted that µ r changes with different
DC magnetizing force H, and so does the inductance. As an example, Figure 5 illustrates the relationship
between the Percent Permeability and the DC Magnetizing Force H.
µ 0 in (15) is the magnetic field constant which is equal to 1.257e-6; Bmax is the maximum magnetic flux
density for the selected magnetic material (for sendust, Bmax is up to 0.8T.)
Figure 5 Percent Permeability and DC Magnetizing Force H (from Changsung)

Select a core with similar Ve value from the magnetic core datasheet. For example, the core type
CS468125 from Chang Sung Corporation is selected. The parameters of CS468125 are Ve=15.584cm3,
Ae=1.34cm2, C=11.63cm, µ r =125. The turn number of the boost choke winding is
Lboost ⋅ C
N toroid _ boost = = 83 (16)
µ r µ 0 Ae
where, C is the magnetic path length and Ae is the effective magnetic cross section area.
To check the actual µ r at low line, maximum power, the DC Magnetizing Force H is calculated
NI in _ pk
H= = 50(Oe)
C

Then µr = 125 * 50% = 62.5 according to Figure 5. The actual inductance can be re-calculated as
N 2 µ r µ 0 Ae
Lboost = = 0.625mH . Hence, the corresponding ripple current will be higher than the
C
previously assumed value.
The copper loss of the winding wire can be calculated on Iin_RMS.
2
PL _ boost = I in _ RMS ⋅ RL _ boost (17)
Select the proper wire type to fullfil the loss and thermal requirement for the choke.
(2) ferrite core

To make sure the ferrite core will not go into saturation, the turn number of the boost choke winding with
ferrite core is
I L _ pk ⋅ Lboost
N ferrite _ boost ≥ (18)
Bmax ⋅ Amin
where, Bmax is up to 0.3T according to ferrite material specification; Amin is the minimum magnetic cross
section area.
The winding wire copper loss calculation is the same as in the above section of sendust powder toroid
core.
2.6 AC line current filter

As decribed in section 2.5, there is high frequency ripple current peak to peak IHF passing through boost
choke. This ripple will also go into AC line power network. The current filter is necessary to reduce the
amplitude of high frequency current component. The filtering circuit consists of a capacitor and an inductor
as shown in Figure 6.
Rectifier
IHF_spec Current Filter IHF
Lfilter Cfilter
VIN=85V ...265VAC
Figure 6 AC line current filter
The required Lfilter is

I HF
+1
I HF _ spec
L filter ≥ (19)
(2πf SW ) 2 C filter
normally there is one EMI X2 capacitor which can act as Cfilter. In this example, if we define IHF_spec as 0.2A
peak to peak and asumming X2 capacitance 0.47µF, then
1.2 A
+1
L filter ≥ 0.2 A = 89 µH
(2π ⋅ 65kHz ) 2 ⋅ 0.47 µF
The leakage inductance of EMI common mode choke can be used for current filter. If the leakage inductance
is large enough, no need to add the additional differential mode inductor for filtering. Otherwise, a current
filter choke is necessary. The calculation method for the current filter choke is the same as for boost choke.
2.7 Boost Output Bulk Capacitance

The bulk capacitance has to fullfil two requirements, output double line frequency ripple and holdup time.
(1) output double line frequency ripple limit.
The inherent PFC always presents 2*fL ripple. The amplitude of ripple voltage is dependant on output
current and bulk capacitance as below.
I out
C out ≥ (20)
π ⋅ 2 * f L ⋅ Vout _ ripple _ pp
where, Iout is the PFC output current, Vout_ripple_pp is the output voltage ripple (peak to peak), and fL is the
AC line frequency.
Please note that ICE2PCXX has enhance dynamic block which is active when Vout exceed ±5% of
regulated level. The enchanc dynamic block should be designed to work only during load or line change.
During steady state with constant load, the enhance dynamic block should not be triggered, otherwise
THD will be deteriorated. That means the target Vout_ripple_pp must be lower than 10% of Vout. For this
example, Vout=390VDC, then Vout_ripple_pp must be lower than 39V. if we define Vout_ripple_pp=12V, then
I out
C out ≥ = 220µF (21)
π ⋅ 2 ⋅ f L ⋅ Vout _ ripple _ pp
(2) holdup time requirement
After the PFC stage, there is commonly a PWM stage to provide isolated DC output for end user. Some
applications, especially computing, have the holdup time requirement. It means that PWM stage should
be able to provide the isolated output even if AC input voltage become zero for a short holdup time. The
common specification for this holdup time is 20ms. If minimum input voltage for PWM stage is defined as
250VDC, then the bulk capacitance will be
2 ⋅ Pout ⋅ t holdup 2 ⋅ 300W ⋅ 20ms
C out ≥ = = 134 µF (22)
2
Vout − Vout _ min
2
390 2 − 250 2
the final Cout capacitance should be higher value calculated from the above two requirements.
2.8 Current Sense Resistor
The current sense resistance is calculated based on the IC soft over current control threshold and peak
current carried by boost choke.
When the Isense signal reaches the soft over control threshold, IC will reduce the internal control voltage and
accordingly the duty cycle is reduced in the following cycles. Finally the boost choke current is limited.
According to IC datasheet, soft over current control threshold is -0.68V maximum. So the current sense
resistor should be
0.68V 0.68V
Rsense ≤ = = 0.11Ω (23)
I L _ pk 6.14 A

According to Figure 2 and Figure 3, the transistor current as well as the diode current flows through Rsense.
That means, when AC is powered up, a large negative voltage drop at Rsense will be observed when large
inrush current in the range of about 150 A to 200 A flows through the resistor. It is therefore necessary to
limit the current into Pin 2 (ISENSE) to 1 mA, which is realized with resistor R3. A value of R3 = 220Ω is
sufficient for this resistor.
2.9 Output voltage sensing divider

The output voltage is set with the voltage divider represented by R1 and R2 in Figure 2 and Figure 3. First,
choose the value of the lower resistor R2. Then the value of the upper resistor R1 is
Vout − Vref
R1 = ⋅ R2 (24)
Vref
where, Vref is IC internal reference voltage for voltage sensing, 3V typical.
If R2=6kΩ,
390 − 3
R1 = ⋅ 10kΩ = 774kΩ
3
It is recommended to take resistor values with a tolerance of 1% for R1 and R2. Due to the voltage stress of
R1, it is recommended to split this value into few resistors in series.
2.10 Frequency setting (only for ICE2PCS01)

The frequency of the ICE2PCS01 is adjustable in the range of 50 kHz up to 250 kHz. The external resistor
RFREQ according to Figure 7 programs a current which controls the oscillator.
Figure 7 Resistor-frequency characteristic

2.11 AC Brown-out Shutdown (only for ICE2PCS02)
Brown-out occurs when the input voltage VAC falls below the minimum input voltage of the design (i.e. 85V
for universal input voltage range) and the VCC has not entered into the VCCUVLO level yet. For a system
without input brown out protection (IBOP), the boost converter will increasingly draw a higher current from
the mains at a given output power which may exceed the maximum design values of the input current and
lead to over heat of MOSFET and boost diode. ICE2PCS02 provides a new IBOP feature whereby it senses
directly the input voltage for Input Brown-Out condition via an external resistor/capacitor/diode network as
shown in Figure 8. This network provides a filtered value of VIN which turns the IC on when the voltage at
Pin 4 (VINS) is more than 1.5V. The IC enters into the standby mode and gate is off when VINS goes below
0.7V. The hysteresis prevents the system to oscillate between normal and standby mode.
Figure 8 Block diagram of voltage loop
Because of the high input impedence of comparator of C4 and C5, R5 can be high ohmic resistance to
reduce the loss. From the datasheet, the bias current on VINS Pin is 1µA maximum. In order to have the
design consistence, the current passing through R5 and R6 has to be much higher than this bias current, for
example 6µA. Then R6 is:
0.7V
R6 = = 117 kΩ (25)
6uA
R6 is selected 120KΩ. R5 is selcted by
2 ⋅ V AC _ on − 1.5V
R5 = ⋅ R6 (26)
1.5V
where, VAC_on is the minimum AC input voltage (RMS) to start PFC, for example 70VAC.
2 ⋅ 70V − 1.5V
R5 = ⋅ 120kΩ = 7.8MΩ
1.5V
Due to the voltage stress of R5, it is recommended to split this value into few resistors in series.
C4 is used to modulate the ripple at the VINS pin. The timing diagram of VINS pin when IC enters brown-out
shutdown is shown in Figure 9.

Figure 9 Timing diagram of VINS Pin when IC enters brown-out shutdown
If the bottom level of the ripple voltage touches 0.7V, PFC is in standby mode and gate is off. The ripple
voltage defines PFC brown out off threshold of AC input voltage (RMS), VAC_off. C4 can be obtained from the
R6
following equation. Assuming V INS _ AVE = ⋅ V AC _ off , where, VAC_off is the maximum AC input voltage
R5 + R6
(RMS) to switch off PFC, for example 65VAC.
t disch arg e
R6 −
(2 ⋅ ⋅ V AC _ off − 0.7) ⋅ e R6C4
= 0.7V (27)
R5 + R6
1
assuming tdischarge is equal to half cycle time of line frequency, ie. t disch arg e = , then
2 fL
−1
 R6 
 2⋅ V AC _ off − 0.7V 
 R5 + R6 
C 4 = 2 f L R6 ln
 0.7V 
 
  (28)
−1
 120kΩ 
 2⋅ 65V − 0.7V 

C 4 = 2 ⋅ 50 Hz ⋅ 120kΩ ln 7 .8 M Ω + 120 kΩ  = 140nF
 0.7V 
 
 
2.12 IC supply
The IC supply voltage operating range is 11~26V.
There are two stages during IC turned on. First Vcc capacitor is charged from 0V to 7V, the IC internal
regulator block starts to reset voltage at all external pins. The reset process will take about 10us. And then
when Vcc voltage is charged to Vcc_on threshold, IC starts the soft start with gate switching. In the case of
Vcc decoupling capacitance is too low such as 0.1uF, Vcc voltage may be charged up too fast and the time
interval from Vcc=7V to Vcc_on is less than the reset time. Then the IC will not go through a proper soft start
as the voltages at IC pins are not yet properly reset. To avoid such a problem, the delay circuitry is needed.

Q1
AUX supply
IC Vcc input
Cvcc R1 Cdelay
0.1uF 10k 0.47uF
R2
10k
Power on Q2
control
Figure 10 Vcc supply circuitry
Figure 10 is a typical circuitry to supply PFC controller. Q2 is NPN transistor and controlled by external
“Power on” signal. When “Power on” signal is “high”, Q2 is turned on provides base current for Q1. Q1 is
turned on accordingly to supply auxiliary power to IC Vcc. The reset delay time is adjustable by changing the
RC time constant of R1, R2 and Cdelay. The recommended values are shown in Figure 10 as 10kΩ, 10kΩ and
0.47uF respectively.
The same reset process also happens during IC power down when Vcc is discharged from Vcc_off to 7V.
The reset time for power down is around 200us. Because IC is in power down mode with very low current
consumption, typically 300uA only, the required Vcc capacitance for power down reset can be calculated as:
I power _ down _ max ⋅ t reset 650 µA ⋅ 200 µs
CVCC ≥ = = 38.2nF (29)
Vcc _ off _ min − Vreset 10.4V − 7V
So the common Vcc decoupling capacitance 0.1uF is enough for reset delay requirement.
2.13 PCB layout guide

In order to avoid crosstalk on the board between power and signal path, and to keep the IC GND pin as
“clean” from noise as possible, the PCB layout for GND must be taken care of properly. Below are some
suggestions for GND connection and Figure 11 below illustrates as a good example.
(1) Star connection rule for main power stage GND: the PCB tracks of MOSFET source, output load
GND, IC auxiliary supply GND and shunt resistor are separated and connected together at bulk
capacitor negative Pin.
(2) Star connection rule for small signal IC GND: the IC external components which need to be
connected to the small signal GND bus highlighted in red color. Such GND bus is connected to IC
GND Pin.
(3) Connection between main power stage GND and small signal IC GND: in Figure 11, a single PCB
track in pink color directly connect IC GND pin to power stage star connection point - bulk capacitor
negative. This is to ensure that the voltage between IC Isense Pin and IC GND Pin does not observe
the switching rectangular noise current. The dark green and blue tracks denote for flowing paths of
high frequency rectangular switching current.
(4) Vcc decoupling capacitor Cvcc: the decoupling capacitor need to be placed close to IC Vcc and
GND Pins as much as possible. The GND track of Cvcc (green color in Figure 11) should be
connected at the point on the single PCB track connecting between IC GND Pin and power GND
point so that the large gate charging current will not pass through the small signal GND bus.
(5) Vsense capacitor Cvsense: to reduce noise in Vsense Pin, small capacitor up to 0.1uF can be added
between Vsense Pin and small signal GND bus.

Rectifier
EMI Filter
L1
R1
T1 C OUT VOUT =400VDC
R2
VIN=85V ...265V AC R SENSE
R3
ISENSE GATE GND

VSENSE
Cvsense
VCC ICEXPCS01
Auxiliary Supply Cvcc
ICOMP FREQ VCOMP
RFREQ R4
C1 C2 C3
Figure 11 Good PCB layout illustration
3 Voltage loop and current loop compensation

This section provides a model and a tool for evaluating and improving the control loop characteristics of
ICE2PCS02-based PFC pre-regulators in boost topology. The goal is not only to ensure a narrow bandwidth
in order to achieve a high Power Factor, but also to have enough phase margin so as to make sure the
system is stable over a large range of operating conditions. The design example is demonstrated as well.
Traditional diode rectifiers used in front of the electronic equipment draw pulsed current from the utility line,
which deteriorates the line voltage, produce radiated and conducted electromagnetic interference, leads to
poor utilization of the capacity of the power sources. In compliance with IEC 61000-3-2 harmonic regulation,
active power factor correction (PFC) circuit is getting more and more attention in recent years. For low power
up to 200W, discontinuous conduction mode (DCM) PFC is popular due to its lower cost. Furthermore, there
is only one control loop, i.e. voltage loop, in its transferring control blocks. The design is easy and simple for
DCM operation. However, due to its inherent high current ripple, DCM is seldom to be used for high power
applications. In high power applications, continuous conduction mode (CCM) PFC is more attractive.
V, I
OUT
IL
IIN
DCM operation CCM operation
Figure 12 DCM and CCM PFC principle

3.1 How to achieve PFC function without sinusoidal reference sensing
3.1.1 Boost converter modeling

Figure 13 shows the inductor current waveform for boost converter operating in continuous conduction mode.
iL
diL
I0
ton toff
TSW
Figure 13 inductor current waveform of boost converter operating in CCM mode
assuming Vin is boost converter input DC voltage, Vout is the boost converter output voltage, L is the boost
choke inductance, ton is the on time duration in one switching cycle, toff is the off time duration in one
switching cycle, doff is the off time duty cycle and Tsw is the time duration in one switching cycle.
During “on” interval,

diL Vin
= (30)
dt L
During “off” interval,
diL Vin − Vout
= (31)
dt L
And then the boost inductor current variation after one switching cycle is:
Vin V −V V −V ⋅ d
diL = ⋅ ton + in out ⋅ toff = in out off ⋅ TSW (32)
L L L
The instant boost inductor current after n switching cycle is:
Vin _ n − Vout _ n ⋅ d off _ n
iL _ n = iL _ n −1 + ⋅ TSW (33)
L
3.1.2 PFC IC control principle with boost topology

PFC IC control block is inserted in boost converter as shown in Figure 14.

Vin Boost converter iL
Vin _ n − Vout _ n ⋅ d off _ n
iL _ n = iL _ n−1 + ⋅ TSW
L
doff IC PWM modulation

doff=K*iL
Figure 14 PFC current loop principle
IC senses boost inductor average current, and calculate the off duty cycle to be proportional to inductor
current, and then send such off duty cycle back to boost converter. The negative feedback loop can be seen
from Figure 14. A small disturb increasing on iL will result in a little bit increasing on off duty cycle. The
increasing off duty cycle will lead to decreasing of iL after processing by boost converter. In the stead state,
Vin = Vout ⋅ d off = Vout ⋅ K ⋅ iL (34)
Where, K is the modulation gain defined by IC. It can be seen that boost inductor current shape follows AC
input voltage and it is how PFC function to be achieved.
In the following sections, detail mathematical analysis of current loop and voltage loop will be described and
the transfer function for each block is given in order to design IC external compensation network
components.
3.2 Current Loop Regulation and Transfer Function
The detail block diagram of current loop for ICE2PCS02 is shown in the Figure 15. The boost converter
stage Kboost is elaborated in S-plane.
Vout Vin
PWM + iL
M2 Doff -
Comparator X 1/sL
Kc(S)
Boost Converter Power Stage
Kboost(s)
Vicomp Current Averaging

Kave(S)
M1
Figure 15 Block diagram of current loop
3.2.1 Current Averaging Circuit
IC sense the boost inductor current via shunt resistor Rsense as shown in Figure 2. The sensing signal is
sent to Isense Pin. As the voltage in Isense Pin is negative signal together with switching ripple, IC need to
do signal averaging and convert the polarity to positive for following PWM modulation blocks. The output of
averaging block is Vicomp voltage at Icomp Pin. the block diagram of current averaging block is shown in
Figure 16.

Figure 16 current averaging block diagram
The transfer function of averaging circuit block can be derived as below.

K 1 Rsense
Vicomp M1
K AVE ( s ) = = (35)
iL K 1C icomp
1+ s ⋅
M 1 g OTA 2
where, K1 is a ratio between R501 and R7 which is equal to 4, Cicomp is the capacitor at Icomp Pin, gOTA2 is
the trans-conductance of the error amplifier of OTA2 for current averaging, typical 1.0mS as shown in
Datasheet, M1 is the variable controlled by voltage loop.
The function of the averaging circuit is to filter out the switching current ripple. So the corner frequency of the
averaging circuit fAVE must be lower than the switching frequency fSW. Then,
g OTA2 M 1
C icomp ≥ (36)
K 1 ⋅ 2πf AVE
3.2.2 PWM comparator block

The averaged Vicomp signal is sent to PWM comparator block and compared with internal triangular ramp
signal to derive duty cycle. The timing diagram of this block is shown in Figure 17.

Ramp
Vicomp
PWM
Comparator
To PWM logic and
gate driver block
C1
Vicomp
From protection logic Gate drive
Vramp=M2*Kfq
Oscillator
Tosc
Figure 17 The block diagram and timing sequence of PWM comparator block
The operating principle is explained as following. Gate output is in “low” state in the beginning of the each
cycle. Gate output is turned to “high” at the intersection of the triangular ramp signal and Vicomp signal. Gate
output is turned to “low” by oscillator synchronous signal. Based on the operating principle, the transfer
function of KC(s) is:
d off 1
K C (s) = = (37)
Vicomp K FQ M 2
Where, KFQ is a design constant which is equal to 9.183, M2 is the variable controlled by voltage loop.
3.2.3 Boost converter stage

The transfer function of boost converter stage KBoost(s) can be obtain via State-Space Averaging method.
Combining equation (30) and (31) by state –space averaging,
di L Vin V − Vout Vin − Vout d off
= d on + in d off = (38)
dt L L L
Make Laplace transformation for equation (38) with assuming Vin and Vout are constant for current loop
analysis,
1
i L ( s ) = (Vin − Vout d off ( s )) (39)
sL
The equation (39) has been described in current loop block diagram in Figure 15. Although Vin is not
physically sensed by circuit, the input sinusoidal signal is presented in transfer functions only if
boost topology is applied.
3.2.4 Open loop transfer function gain for current loop

The open loop gain of current regulation loop is:
K 1 RsenseVout
V K FQ M 1 M 2 L
GC ( s ) = K AVE ( s ) K C ( s ) out = (40)
sL K 1Cicomp
s (1 + s ⋅ )
M 1 g OTA2

The selected Cicomp must also meet the requirement that the cross over frequency of the current loop fC is
much lower than the switching frequency fSW.
3.2.5 Steady state solution of IL

Solving the current loop in Figure 15,
1 1
i L ( s ) = (Vin − Vout d off ( s )) = (Vin − Vout K C ( s ) K AVE ( s )i L ( s ))
sL sL
Vin Vin
i L ( s) = sL = sL (41)
Vout K C ( s ) K AVE ( s ) 1 + GC ( s )
1+
sL
For AC line frequency which is much lower than fC, then Gc ( s ) >> 1
Vin Vin K FQ M 1 M 2Vin

sL K 1 RsenseVout
i L ( s) = ≈ sL = (42)
1 + GC ( s ) GC ( s ) K1C icomp
1+ s ⋅
M 1 g OTA2
K 1C icomp
For AC line frequency which is also much lower than fAVE, s ⋅ << 1 , then the steady state IL can
M 1 g OTA 2
be derived as
K FQ M 1 M 2Vin
IL = (43)
K1 RsenseVout
from the above steady state solution of IL, it can be seen that the choke current IL is always following
input voltage Vin. This is how PFC function is achieved.
3.3 Voltage Loop Compensation
The control loop block diagram for ICE2PCS02 based CCM PFC is shown in Figure 18 and Figure 19. There
are four blocks in the loop. IC PWM Modulator G2(s) has been discussed in above Section 3. the rest of them
are Error Amplifier G1(s), nonlinear block GNON(s), boost converter output stage G3(s) and Feedback Sensing
G4(s).
Vin
Vcomp_DC
0V
Vref + Boost converter Vout

Error Amplifier Vcomp Nonlinear block M1M2 PWM Modulator iL
output Stage
G1(s) GNON(s) G2(s)
- G3(s) 400V
Vsense
5V
Feedback
G4(s)
Figure 18 Large signal modeling of voltage loop

PWM modulation G2(s) Output Stage G3(s)
Voltage loop ∆Vcomp Non- ∆ ( M 1M 2 ) I L _ rms ∆I L _ rms ∆I out Output Stage ∆Vout
+ Vinrms
Error Amplifier linear 1
G1(s) GNON(s) M 1M 2 + Vout _ AVE
- sCout
∆Vsense -
I L _ rms
Vout _ AVE
Feedback
Figure 19 Small signal modeling of voltage loop
3.3.1 Boost converter output stage G3(s)
Boost converter output stage is described as influencing of variation on iL to bulk output voltage Vout. The
transfer function of power stage, G3(s), is separated to two stages as:
∆Vout ∆Vout ∆I out

G3 ( s ) = = ⋅ (44)
∆I L _ rms ∆I out ∆I L _ rms
where Vout is the DC output voltage, Iout the DC output current and IL_rms is the boost inductor current.
3.3.1.1 ∆Vout / ∆Iout
Under the above assumption, the power stage can be modeled as illustrated in Figure 20: a controlled
current source (with a shunt resistor Re) that drives the output bulk capacitor Cout and the load resistance
Rout (= Vout / Iout). The zero due to the ESR associated with Cout is far beyond the crossover frequency thus
it is neglected.
Iout Re Cout Rout Vout
Figure 20 Power stage modeling
A few algebraic manipulations would show that the shunt resistor Re always equals the DC load resistance
Rout, thus it changes depending on the power delivered by the system. There are two kinds of load in the
application. Two cases will give a different result in case of resistive load or constant power load. For purely
resistive load, the AC load resistance equals Ro. In case of constant power load like additional isolated PWM
DC/DC converter, the AC load resistance is equal to -Ro (if the DC bus decreases, the current demanded of
the PFC increases. hence the negative sign is shown.). As a result, the parallel combination with Re tends to
infinity and the two resistances cancel. The current source drives only the output capacitor. The result is
summarized as below:

 Rout
Resistive Load
 R C
∆Vout  2(1 + s ⋅ out out )
= 2 (45)
∆I out  1
 sC out
Constant Power Load

In this application note, the calculation is only carried out for constant power load situation
3.3.1.2 ∆Iout / ∆IL_rms
The current source Iout can be characterized with the following considerations as shown in Figure 21. The
low frequency component of the boost diode current is found by averaging the discharge portion of the
inductor current over a given switching cycle. The low frequency current, averaged over a mains half-cycle
yields the DC output current Iout:
IL_PK
iL
idiode
IOUT
Figure 21 The simplification and characterization for Iout / IL_rms
1 π 2Vinrms I L _ rms π Vinrms I L _ rms

π∫ ∫
I out = (1 − Don ) I L _ PK Sinαdα = ( Sinα ) 2 dα = (46)
0 πVout _ AVE 0 Vout _ AVE
So,
∆I out V
= inrms (47)
∆I L _ rms Vout _ AVE
where, Don is the switch duty cycle; α is the instantaneous phase angle of the mains voltage, Vinrms is the
input RMS voltage value, IL_PK is choke current sinewave peak value and Vout_AVE is the averaging bulk DC
output voltage.
In case of constant power load, the transfer function of G3(s) is:

∆Vout ∆Vout ∆I out V 1
G3 ( s ) = = ⋅ = inrms ⋅ (48)
∆I L _ rms ∆I out ∆I L _ rms Vout _ AVE sC out
3.3.2 Small signal transfer function of ∆Vout/∆(M1M2) for voltage loop analysis
There is a internal feedback from Vout to G2(s). this inner loop has to be solved to obtain the transfer
function of ∆Vout/∆(M1M2). Rewrite the equation (43) at input voltage RMS point:
K FQ M 1 M 2Vinrms
I L _ rms = (49)
K1 RsenseVout

making a perturbation on IL_rms, (M1M2), Vout, then
I L _ rms I L _ rms
∆I L _ rms = ∆( M 1 M 2 ) − ∆Vout (50)
M 1M 2 Vout _ AVE
replacing ∆IL_rms by ∆Vout/G3(s) according to voltage loop block diagram,

∆Vout I L _ rms I L _ rms
= ∆( M 1 M 2 ) − ∆Vout (51)
G3 ( s ) M 1 M 2 Vout _ AVE
then the transfer function of dVout/dVcomp is
Vout _ AVE Vout _ AVE
∆Vout M 1M 2 M 1M 2
G23 ( s ) = = = (52)
∆( M 1 M 2 ) Vout _ AVE 2 C out 3
K 1 RsenseVout _ AVE C out
s +1 2
s +1
I L _ rmsVinrms K FQ M 1 M 2Vinrms
1
With f 23 = 3
,
K 1 RsenseVout _ AVE C out
2π 2
K FQ M 1 M 2Vinrms
Vout _ AVE
∆Vout M 1M 2
G23 ( s ) = = (53)
∆( M 1 M 2 ) s
1+
2πf 23
3.3.3 Nonlinear block GNON(s)

The Vcomp voltage is sent to nonlinear gain block. The output of nonlinear is two internal variables, M1 and
M2. The two variables are used to define boost choke current amplitude IL as in equation (43). The
characteristic of nonlinear gain block is shown in Table 2 and Figure 22. The small signal gain between
∆(M1*M2) and ∆Vcomp can be derived as well at different operating point.
Vcomp M1 M2 M1*M2
0.00 4.686E-02 4.964E-04 2.326E-05
0.25 4.685E-02 7.072E-04 3.313E-05
0.50 4.665E-02 1.199E-03 5.595E-05
0.75 4.685E-02 3.292E-03 1.542E-04
1.00 4.823E-02 3.224E-02 1.555E-03
1.25 8.153E-02 1.075E-01 8.766E-03
1.50 1.261E-01 1.921E-01 2.423E-02
1.75 1.901E-01 2.796E-01 5.316E-02
2.00 2.747E-01 3.686E-01 1.013E-01
2.25 3.768E-01 4.590E-01 1.729E-01
2.50 4.884E-01 5.523E-01 2.697E-01
2.75 5.992E-01 6.539E-01 3.918E-01
3.00 6.992E-01 7.794E-01 5.449E-01
3.25 7.816E-01 9.669E-01 7.557E-01
3.50 8.443E-01 1.287E+00 1.087E+00
3.75 8.888E-01 1.802E+00 1.601E+00
4.00 9.184E-01 2.442E+00 2.243E+00
4.25 9.339E-01 2.911E+00 2.719E+00

4.50 9.350E-01 2.911E+00 2.722E+00
4.75 9.351E-01 2.911E+00 2.722E+00
5.00 9.351E-01 2.911E+00 2.722E+00
Table 2 nonlinear block characteristic data
3.5
3.0
2.5
M1 2.0
M2
M1*M2 1.5
1.0
0.5
0.0
0 1 2 3 4 5
Vcomp
Figure 22 The characteristics of nonlinear block
3.3.4 Error Amplifier compensation G1(s)
The circuit of error amplifier compensation circuit is shown in Figure 23. The sensing voltage Vsense is
compared to internal reference voltage 3V typical. The difference between Vsense and internal reference is
sent to transconductance error amplifier and converted to a current source to charge or discharge the RC
components in Vcomp Pin.
Figure 23 Error Amplifier compensation G1(s)
The transfer function is:

∆Vcomp ∆Vcomp ∆I OTA1 1 + sR4 C 2
G1 ( s) = = ⋅ = ⋅ g OTA1 (54)
∆Vsense ∆I OTA1 ∆Vsense R4 C 2 C 3
(C 2 + C 3 ) s(1 + s )
C 2 + C3
where, gOTA1 is the trans-conductance of OTA1, 42uS typically for ICE2PCS02.

1 1
With f CZ = and f CP = ,
2πR4 C 2 R4 C 2 C 3
2π
C 2 + C3
g OTA1 (1 + s )
2πf CZ
G1 ( s ) = (55)
(C 2 + C3 ) s(1 + s )
2πf CP
The pole and zero are to regulate the overall voltage loop with the cross-over frequency below 100Hz and
create the phase margin for the loop stability.
3.3.5 Feedback G4(s)
The Feedback block is a simple voltage divider to monitor the bulk capacitor output voltage. The circuit is
shown in Figure 24.
Vout
∆Vsense R2 R1
G4 ( s ) = = (56)
∆Vout R1 + R2
Vsense
R2
Figure 24 bulk voltage sensing divider
3.3.6 Overall Open Loop Transfer Function GV(s)
With combining all of the blocks above, the overall open loop gain for voltage loop is equal to:
GV ( s ) = G1 ( s )G NON ( s )G23 ( s )G4 ( s ) (57)
Due to PF requirement, inherent PFC dynamic voltage loop compensation is always implemented with low
bandwidth in order not to make the response for 2*fL ripple. For example, for 50Hz AC line input, PFC
voltage loop bandwidth is normally set below 20Hz. The compensation circuit R4, C2 and C3 are used to
optimize the loop gain and phase margin.
3.3.7 Enhance dynamic response

As mentioned in Section 4.6, the inherent low bandwidth of voltage loop in PFC application will lead to slow
response in case of sudden load step and result in large output overshoot or drop. Enhance dynamic
response feature is integrated in ICE2PCS02 to have a fast response in the case of load step. The voltage
loop with including enhance dynamic response block is shown in Figure 25.
Vin
Vcomp_DC
0V
Vref + Boost converter Vout

Error Amplifier Vcomp Nonlinear block M1M2 PWM Modulator iL
output Stage
G1(s) + GNON(s) G2(s)
- G3(s) 400V
+/-
Vsense
5V Enhance dynamic
Feedback
G4(s)
Figure 25 voltage loop block diagram including enhance dynamic response

When Vsense voltage variation is within -5% to +5% of nominal value, there is no function of enhance
dynamic response block. However, when Vsense variation is out of such +/-5% range, enhance block will
add offset voltage on top of Vcomp voltage to influence the current amplitude.
The timing diagram of enhance dynamic response operation is shown in Figure 26 with sudden load jump
situation. It can be seen that during enhance dynamic operation, the high current of boost choke is delivered
for fast response. Within half sinusoidal period, when Vsense operating around the boundary of -5%
threshold, the first part of boost choke current follows high amplitude profile due to enhance mode offset and
the rest of boost choke current come back to low amplitude profile without enhance mode offset. When
Vsense voltage is pulled back within +/-5% range, enhance dynamic offset disappear and boost choke
current waveform will stay as perfect sinusoidal shape.
Normal enhance Normal
Vin
Iin
Vcomp
0
Pin Pin_ave
0
Ichg Ichg_ave
0
Vout Vout_ave nominal

- 5%
Figure 26 timing diagram for enhance dynamic operation
3.4 Design Example
Assuming a 300W application with universal input AC voltage 85~265VAC,
constant power load

efficiency=90%
Vout=400VDC
Cout=220uF/450V
fSW=125kHz
Rsense=0.1ohm
Boost choke inductance L=1.2mH (please note that the inductance may change at different choke current)
Vsense divider: R1=390kohm*2=780kohm, R2=6kohm
3.5 Vcomp and M1, M2 value at full load condition

(1) 85VAC:
RMS AC input current under full load:

Pout 300
I L _ rms _ 85 = = = 3.92 A (58)
η ⋅ Vinrms _ 85 0.9 ⋅ 85
From equation (43), With K FQ = 4.34 and K 1 = 4 from the ICE2PCS02 Datasheet,
I L _ rms _ 85 K1RsenseVout 3.92 ⋅ 4 ⋅ 0.1⋅ 400
M 1M 2 85VAC = = = 1.70 (59)
K FQVinrms _ 85 4.34 ⋅ 85
From table 2 and Figure 22, it can be obtained

Vcomp M1 M2 M1*M2
3.75 8.888E-01 1.802E+00 1.601E+00
4.00 9.184E-01 2.442E+00 2.243E+00
With Linear approximation:

M 1M 2 85VAC − M 1M 2
Vcomp _ 85 = Vcomp _ 1 + Vcomp _ 1
⋅ (Vcomp _ 2 − Vcomp _ 1 )
M 1M 2 Vcomp _ 2 − M 1M 2 Vcomp _ 1 (60)
1.70 − 1.601
Vcomp _ 85 = 3.75 + ⋅ (4 − 3.75) = 3.79V
2.243 − 1.601
M1 _ 2 − M1 _ 1
M 1 85VAC = M 1 _ 1 + ⋅ (Vcomp _ 85 − Vcomp _ 1 )
Vcomp _ 2 − Vcomp _ 1
(61)
0.918 − 0.889
M 1 85VAC = 0.889 + ⋅ (3.79 − 3.75) = 0.894
4 − 3.75
M 2 _ 2 − M 2 _1
(62)
2.442 − 1.802
M 2 85VAC = 1.802 + ⋅ (3.79 − 3.75) = 1.91
4 − 3.75
The small signal gain of nonlinear block is
M 1 M 2 Vcomp _ 2 − M 1 M 2 Vcomp _ 1 2.243 − 1.601
G NON ( s ) 85VAC = = = 2.568 (63)
Vcomp _ 2 − Vcomp _ 1 4 − 3.75
The inherent pole of f23 is

1
f 23 85VAC
= 3
= 1.54 Hz (64)
K1 RsenseVout _ AVE C out
2π 2
K FQ ⋅ ( M 1 M 2 ) 85VAC ⋅ Vinrms _ 85
(2) 265VAC
RMS AC input current under full load:

Pout 300
I L _ rms _ 265 = = = 1.257 A (65)
η ⋅ Vinrms _ 265 0.9 ⋅ 265
From equation (43),
I L _ rms _ 265 K1RsenseVout 1.257 ⋅ 4 ⋅ 0.1 ⋅ 400
M 1M 2 265VAC = = = 0.175 (66)
K FQVinrms _ 265 4.34 ⋅ 265
From table 2 and Figure 22, it can be obtained

Vcomp M1 M2 M1*M2
2.25 3.768E-01 4.590E-01 1.729E-01
2.50 4.884E-01 5.523E-01 2.697E-01
With Linear approximation:

M 1M 2 265VAC − M 1M 2
Vcomp _ 265 = Vcomp _ 1 + Vcomp _ 1
⋅ (Vcomp _ 2 − Vcomp _ 1 )
M 1M 2 Vcomp _ 2 − M 1M 2 Vcomp _ 1 (67)
0.175 − 0.1729
Vcomp _ 265 = 2.25 + ⋅ (2.5 − 2.25) = 2.255V
0.2697 − 0.1729
M1 _ 2 − M1 _ 1
(68)
0.4884 − 0.3768
M 1 265VAC = 0.3768 + ⋅ (2.266 − 2.25) = 0.386
2.5 − 2.25
M 2 _ 2 − M 2 _1
(69)
0.5523 − 0.459
M 2 265VAC = 0.459 + ⋅ (2.255 − 2.25) = 0.461
2.5 − 2.25
The small signal gain of nonlinear block is
M 1 M 2 Vcomp _ 2 − M 1 M 2 Vcomp _ 1 0.2697 − 0.1729
G NON ( s ) 265VAC = = = 0.3872 (70)
Vcomp _ 2 − Vcomp _ 1 2.5 − 2.25
The inherent pole of f23 is

1
f 23 265VAC
= 3
= 1.54 Hz (71)
K1 RsenseVout _ AVE C out
2π 2
K FQ ⋅ ( M 1 M 2 ) 265VAC ⋅ Vinrms _ 265

3.5.1 Current Averaging Circuit
With gOTA2=1.0mS from Datasheet, M1@85VAC, and assuming fAVE=13kHz which is 10 times less than
switching frequency 125kHz, then
g OTA2 M 1 85VAC 1.0 E − 3 ⋅ 0.895

C icomp ≥ = = 3nF (72)
K 1 ⋅ 2πf AVE 4 ⋅ 2π ⋅ 24 E 3
Select Cicomp=3.3nF
3.5.2 Current Loop Regulation
Insert M1 and M2 value in equation (40). The amplitude and phase angle of GC(s) is shown in Figure 27 to
verify the stability of current loop and the requirement of fC less than switching frequency.
100
85VAC full load
265VAC full load
50
0
Gain(db)
-50
-100
-150
0 1 2 3 4 5 6 7
10 10 10 10 10 10 10 10
f(HZ)

-90
85VAC full load
265VAC full load
-100
-110
-120
-130
Phase Angle
-140
-150
-160
-170
-180
0 1 2 3 4 5 6 7
10 10 10 10 10 10 10 10
f(HZ)
Figure 27 The bode plot and phase angle for current loop
The cross over frequency and phase margin are 3kHz and 75º for 85VAC, and 10kHz and 25º for 265VAC.

3.5.3 Voltage Loop Regulation
From the above sections, it can be obtained:
∆Vcomp g OTA1 (1 + s )
2πf CZ
G1 ( s ) = = (73)
∆Vsense (C 2 + C 3 ) s (1 + s )
2πf CP
∆( M 1 M 2 )
G NON ( s ) = (74)
∆Vcomp
Vout _ AVE
∆Vout M 1M 2
G23 ( s ) = = (75)
∆( M 1 M 2 ) s
1+
2πf 23
∆Vsense R2 6.2
G4 ( s ) = = = . = 0.0077 (76)
∆Vout R1 + R2 806.2
The open loop gain for voltage loop is to times all above factors together as:
GV ( s ) = G1 ( s )G NON ( s )G23 ( s )G4 ( s )
G1(s) is used to provide enough phase margin and also limit the bandwidth below 20HZ. R4, C2 and C3 can
be chosen as required. fCZ normally select to be compensate the pole in G23(s). fCP normally select to be
40~70Hz in order to fast put down the gain amplitude and reject the high frequency interference. In this
example f23 is around 1.54Hz at 85VAC/ 265VAC and full load. So the initial target is: fCZ is chosen to be
close to 1.5Hz, and fCP is chosen to be 50Hz.
C2 and C3 is calculated to obtain Gv(s) cross over frequency around 10Hz. The gain amplitude of
GNON*G23*G4 in 85VAC and full load is shown in Figure 28. It can be seen that at f=10Hz, the gain is about -
4.52dB. So G1 should provide the gain +4.52dB at f=10Hz. Considering that C2>>C3 due to fcz<fcp and
10Hz>>1Hz=fCZ, then
g OTA1 10 Hz
G1 (10 Hz ) = 1Hz = +4.52dB
C2 ⋅ 2π ⋅ 10 Hz
10 Hz (77)
39 ⋅ 10− 6 ⋅
C2 = 4.52 1Hz = 3.69µF
10 20 ⋅ 2π ⋅ 10 Hz
3.97uF is not common for ceramic type capacitor. So select C2=1uF, then fCZ is recalculated as:

gOTA1 1 + (10 Hz )2
f CZ
G1 (10 Hz ) = = +4.52dB
C2 ⋅ 2π ⋅ 10 Hz
10 Hz (78)
f CZ = = 4.30 Hz
2
 1µF ⋅ 104.52 20 ⋅ 2π ⋅ 10 Hz 
  −1
 39 ⋅ 10 − 6 
 
1
according to f CZ = = 4.30 Hz then
2πR4C2
1
R4 = = 37 kΩ (79)
2π ⋅ 4.30 Hz ⋅ C2
1 1
select R4=33kΩ, and f CP = ≈ = 50 Hz
R4 C 2 C 3 2πR4 C 3
2π
C 2 + C3
1
C3 = = 96.5nF (80)
2π ⋅ 50 Hz ⋅ R4
select C3=100nF
The gain amplitude and phase angle of overall voltage loop GV(s) at 85VAC and 265VAC in full load
condition is shown in Figure 28 and Figure 29. At 85VAC, the cross over frequency fV is around 9.5Hz and
the phase margin is about 63º. At 265VAC, the cross over frequency fV is around 14Hz and the phase
margin is about 62º.

60
Gv=G1*Gnon*G23*G4
40 Gnon*G23*G4
20
-20
Gain(db)
-40
-60
-80
-100
-120
-1 0 1 2 3 4
10 10 10 10 10 10
f(HZ)
-90
Gv
-100
-110
-120
Phase Angle
-130
-140
-150
-160
-170
-180
-1 0 1 2 3 4
10 10 10 10 10 10
f(HZ)
Figure 28 the bode plot and phase angle for voltage loop at 85VAC and full load

60
40
20
-20
Gain(db)
-40
-60
-80
-100
-120
-1 0 1 2 3 4
10 10 10 10 10 10
f(HZ)
-90
-100
-110
-120
-130
Phase Angle
-140
-150
-160
-170
-180
-1 0 1 2 3 4
10 10 10 10 10 10
f(HZ)
Figure 29 The bode plot and phase angle for voltage loop at 265VAC and full load

References
[1] Infineon Technologies: ICE2PCS01 - Standalone Power Factor Correction Controller in Continuous
Conduction Mode; Preliminary datasheet; Infineon Technologies; Munich; Germany; Sept. 2007.
[2] Infineon Technologies: ICE2PCS02 - Standalone Power Factor Correction (PFC) Controller in
Continuous Conduction Mode (CCM) at Fixed Frequency, Preliminary datasheet; Infineon Technologies;
Munich; Germany; Sept. 2007.
[3] Luo Junyang, Liu Jianwei, Jeoh Meng Kiat, 300W CCM PFC Evaluation Board with ICE2PCS02,
CoolMOS™ and SiC Diode thinQ!™, Application note, Infineon Technologies, Munich, Germany, Feb. 2007.
[4] Luo Junyang, Liu Jianwei, Jeoh Meng Kiat, ICE2PCSxx, New generation of BiCMOS technology,
Application note, Infineon Technologies, Munich, Germany, Feb, 2007
[5] Luo Junyang, Liu Jianwei, Jeoh Meng Kiat, ICE1PCS01 Based Boost Type CCM PFC Design Guide
- Control Loop Modeling, Application note, Infineon Technologies, Munich, Germany, May, 2007.
[6] Luo Junyang, Liu Jianwei, Jeoh Meng Kiat, ICE1PCS01/02 Boost Type CCM PFC Design with
ICE1PCS01. Application note, Infineon Technologies, Munich, Germany, Apr. 2007.

www.fairchildsemi.com
Application Note AN4134

Design Guidelines for Off-line Forward Converters
Using Fairchild Power Switch (FPSTM)
Abstract
helps the engineers to design a SMPS easily. In order to
This paper presents practical design guidelines for off-line make the design process more efficient, a software design
forward converter employing FPS (Fairchild Power Switch). tool, FPS design assistant, that contains all the equations
Switched mode power supply (SMPS) design is inherently a described in this paper, is also provided.
time consuming job requiring many trade-offs and iteration
with a large number of design variables.
The step-by-step design procedure described in this paper
DR2 L2 Lp2
+
Bridge 2CDC Np NS2 VO2
Reset Circuit
rectifier Non-doubled CO2 Cp2
diode DF2
VDC
Doubled
FPS Lp1
2CDC DR1
Drain
L1
- Ra Da NS1
Vcc VO1
CL2 DF1 CO1 Cp1
FB GND
Ca Na
Line Filter Rd Rbias
CL1 CB 817A R1
RL1 RF CF
NTC Fuse KA431
R2
AC line
Figure 1. Basic Off-line Forward Converter Using FPS
1. Introduction transformer
Due to circuit simplicity, the forward converter has been design, reset circuit design, output filter design, component
widely used for low to medium power conversion selection and closing the feedback loop. The design
applications. Figure 1 shows the schematic of the basic off- procedure described herein is general enough to be applied
line forward converter using FPS, which also serves as the to various applications. The design procedure presented in
reference circuit for the design procedure described in this this paper is also implemented in a software design tool (FPS
paper. Because the MOSFET and PWM controller together design assistant) to enable the engineer to finish SMPS
with various additional circuits are integrated into a single design in a short time. In the appendix, a step-by-step design
package, the design of SMPS is much easier than the discrete example using the software tool is provided.
MOSFET and PWM controller solution.
This paper provides step-by-step design procedure for an
FPS based off-line forward converter, which includes
Rev. 1.0.0
©2003 Fairchild Semiconductor Corporation
AN4134 APPLICATION NOTE
2. Step-by-step Design Procedure

In this section, design procedure is presented using the DC link voltage ripple
schematic of the figure 1 as a reference. In general, most FPS DC link voltage
has the same pin configuration from pin 1 to pin 4, as shown
in figure 1.
(1) STEP-1 : Determine the system specifications T1

Dch = T1 / T2
- Line voltage range (Vlinemin and Vlinemax) :
Usually, voltage = 0.2 - 0.25
T2
doubler circuit as shown in figure 1 is used for a forward
converter with universal input. Then, the minimum line Figure 2.DC Link Voltage Waveform
voltage is twice the actual minimum line voltage.
- Line frequency (fL).
(3) STEP-3 : Determine the transformer reset method and
- Maximum output power (Po). the maximum duty ratio (Dmax)
- Estimated efficiency (Eff) : It is required to estimate the One inherent limitation of the forward converter is that the
power conversion efficiency to calculate the maximum input transformer must be reset during the MOSFET off period.
power. If no reference data is available, set Eff = 0.7~0.75 for Thus, additional reset schemes should be employed. Two
low voltage output applications and Eff = 0.8~0.85 for high most commonly used reset schemes are auxiliary winding
voltage output applications. reset and RCD reset. According to the reset schemes, the
design procedure is changed a little bit.
With the estimated efficiency, the maximum input power is
given by
(a) Auxiliary winding reset : Figure 3 shows the basic
circuit diagram of forward converter with auxiliary winding
P
P in = ------o- (1) reset. This scheme is advantageous in respect of efficiency
E ff since the energy stored in the magnetizing inductor goes
Considering the maximum input power, choose the proper back to the input. However, the extra reset winding makes
FPS. Since the voltage stress on the MOSFET is about twice the construction of the transformer more complicated.
the input voltage in the case of the forward converter, an FPS
with 800V rated MOSFET is recommended for universal
L Vo
input voltage. The FPS lineup with proper power rating is
also included in the software design tool.
Nr Np Ns
Lm
(2) STEP-2 : Determine DC link capacitor (CDC) and the VDC IM

DC link voltage range. Dreset
+
The maximum DC link voltage ripple is obtained as Ir Vds
Vgs
-
max P in ⋅ ( 1 – D ch )
∆ V DC = ------------------------------------------------------------ (2)
min
2V line ⋅ 2f L ⋅ C DC
Vgs
ON ON
where Dch is the DC link capacitor charging duty ratio
defined as shown in figure 2, which is typically about 0.2. Vds
It is typical to set ∆VDC max min
as 10~15% of 2V line For
voltage doubler circuit, two capacitors are used in series, VDC
each of which has capacitance twice of the capacitance that VinNp/Nr
is determined by equation (2).
With the resulting maximum voltage ripple, the minimum V DC Np
IM
and maximum DC link voltages are given as IM+
Lm / C oss N r
IM-
min min max
V DC = 2V line – ∆ V DC (3)
Ir
max max
VDC = 2V line (4)
T0 T1 T2 T3 T4 T5
Figure 3. Auxiliary Winding Reset Forward Converter

2
APPLICATION NOTE AN4134
The maximum voltage on MOSFET and the maximum duty The maximum voltage stress and the nominal snubber capac-
ratio are given by itor voltage are given by
max max  N p
V ds = V DC  1 + ------
N
- (5)
V ds
max
= V DC
max
+ V sn (7)
r
Np min
D max ≤ -------------------- (6) V DC ⋅ D max
Np + Nr V sn > ---------------------------------------- (8)
( 1 – D max )
where Np and Nr are the number of turns for the primary

Since the snubber capacitor voltage is fixed and almost
winding and reset winding, respectively.
independent of the input voltage, the MOSFET voltage
stress can be reduced compared to the reset winding
As can be seen in equations (5) and (6), the maximum
approach when the converter is operated with a wide input
voltage on the MOSFET can be reduced by decreasing Dmax.
voltage range. Another advantage of RCD reset method is
However, decreasing Dmax results in increased voltage stress
that it is possible to set the maximum duty ratio larger than
on the secondary side. Therefore, it is proper to set
50% with relatively low voltage stress on the MOSFET
Dmax=0.45 and Np=Nr for universal input. For auxiliary
compared to auxiliary winding reset method, which results
winding reset, FPS, of which duty ratio is internally limited
in reduced voltage stress on the secondary side.
below 50%, is recommended to prevent core saturation
during transient.
(4) STEP-4 : Determine the ripple factor of the output
(b) RCD reset : Figure 4 shows the basic circuit diagram of inductor current.
the forward converter with RCD reset. One disadvantage of Figure 5 shows the current of the output inductor. The ripple
this scheme is that the energy stored in the magnetizing factor is defined as
inductor is dissipated in the RCD snubber, unlike in the reset
winding method. However, due to its simplicity, this scheme
∆ I-
K RF = ------- (9)
is widely used for many cost-sensitive SMPS.
2I o
where Io is the maximum output current. For most practical
Np Ns L Vo
design, it is reasonable to set KRF=0.1~ 0.2.
-
Rsn Vsn
+ Lm
IM ∆I Io
VDC Dreset Isn
+ ∆I
K RF =
Vds 2 Io
Vgs
- Ts
DTs
Vgs
ON ON Figure 5. Output Inductor Current and Ripple Factor
Vds Once the ripple factor is determined, the peak current and
Vsn rms current of MOSFET are obtained as
VDC
peak
I ds = I EDC ( 1 + KRF ) (10)
rms 2 D max
IM Vsn I ds = I EDC ( 3 + K RF ) -------------
- (11)
IM+ Lm / Coss 3
P in
where I EDC = -------------------------------------
- (12)
min
IM-
V DC ⋅ D max
Isn
Check if the MOSFET maximum peak current (Idspeak) is
T0 T1 T2 T3 T4 T5
below the pulse-by-pulse current limit level of the FPS (Ilim).
Figure 4. RCD Reset Forward Converter

3
(5) STEP-5 : Determine the proper core and the minimum

primary turns for the transformer to prevent core
min
saturation. N V DC ⋅ D max
n = -------p- = -------------------------------------
- (15)
Actually, the initial selection of the core is bound to be crude N sI V o1 + VF1
since there are too many variables. One way to select the
where Np and Ns1 are the number of turns for primary side
proper core is to refer to the manufacture's core selection
and reference output, respectively. Vo1 is the output voltage
guide. If there is no proper reference, use the following
and VF1 is the diode forward voltage drop of the reference
equation as a starting point.
output.
Then, determine the proper integer numbers for Ns1 so that
Ap = Aw Ae
the resulting Np is larger than Npmin obtained from equation
11.1 × P in 1.31
4 4 (14). The magnetizing inductance of the primary side is
= ------------------------------------- × 10 ( mm ) ( 13 )
0.141 ⋅ ∆B ⋅ f s given by
where Aw is the window area and Ae is the cross sectional
2 –9
area of the core in mm2 as shown in figure 6. fs is the L m = A L × N p × 10 (H) (16)
switching frequency and ∆B is the maximum flux density
swing in tesla for normal operation. ∆B is typically 0.2-0.3 T where AL is the AL-value with no gap in nH/turns2.
for most power ferrite cores in the case of a forward
converter. Notice that the maximum flux density swing is The numer of turns for the n-th output is determined as
small compared to flyback converter due to the remnant flux
density. Vo (n ) + VF (n )
N s ( n ) = ---------------------------------- ⋅ N s1 (turns) (17)
V o1 + V F1
where Vo(n) is the output voltage and VF(n) is the diode

forward voltage drop of the n-th output.
The next step is to determine the number of turns for Vcc
Aw winding. The number of turns for Vcc winding is determined
differently according to the reset method.
(a) Auxiliary winding reset : For auxiliary winding reset,
the number of turns of the Vcc winding is obtained as
V cc * + V Fa
- ⋅ N r (turns)
N a = --------------------------- (18)
min
V DC
where Vcc* is the nominal voltage for Vcc and VFa is the
diode forward voltage drop. Since Vcc is proportional to the
input voltage when auxiliary winding reset is used, it is
proper to set Vcc* as the Vcc start voltage to avoid the over
Ae voltage protection during the normal operation.
(b) RCD reset : For RCD reset, the number of turns of the
Vcc winding is obtained as
Figure 6. Window Area and Cross Sectional Area
Vcc * + V Fa
With a determined core, the minimum number of turns for N a = ---------------------------- ⋅ N p (turns) (19)
V sn
the transformer primary side to avoid saturation is given by
where Vcc* is the nominal voltage for Vcc. Since Vcc is
min almost constant for RCD reset in normal operation, it is
min V DC ⋅ D max 6 proper to set Vcc* to be 2-3 V higher than Vcc start voltage.
Np = -------------------------------------- × 10 ( turns ) ( 14 )
Ae ⋅ fs ⋅ ∆ B
(7) STEP-7 : Determine the wire diameter for each
transformer winding based on the rms current.
The rms current of the n-th winding is obtained as
(6) STEP-6 : Determine the number of turns for each
inding of the transformer
rms 2 D max
First, determine the turns ratio between the primary side and I sec ( n ) = Io ( n ) ( 3 + K RF ) -------------
- (20)
3
the feedback controlled secondary side as a reference.
where Io(n) is the maximum current of n-th output.

4
When the auxiliary winding reset is employed, the rms cur- Then, calculate the inductance of the reference output
rent of the reset winding is as follows. inductor as
V DC
min
D max D max V o1 ( Vo1 + V F1 )
I Reset
rms
= ---------------------------------------- -------------- (21) - ( 1 – D min )
L 1 = ---------------------------------------- (24)
Lm f s 3 2 ⋅ f s ⋅ KRF ⋅ P o
min
V DC
The current density is typically 5A/mm when the wire is 2 where D min = D max ⋅ --------------------
max
- (25)
VDC
long (>1m). When the wire is short with small number of
turns, current density of 6-10 A/mm2 is also acceptable.
Avoid using wire with a diameter larger than 1 mm to avoid The minimum number of turns for L1 to avoid saturation is
severe eddy current losses and to make winding easier. For given by
high current output, it is better to use parallel winding with
multiple strands of thinner wire to minimize skin effect.
min L 1 P O ( 1 + K RF ) 6
Check if the winding window area of the core is enough to N L1 = ---------------------------------------- × 10 ( turns ) ( 26 )
VO1 B sat A e
accommodate the wires. The required window area is given
by where Ilim is the FPS current limit level, Ae is the cross
sectional area of the core in mm2 and Bsat is the saturation
Aw = A c ⁄ K F (22) flux density in tesla. If there is no reference data, use Bsat
=0.35-0.4 T. Once NL1 is determined, NL(n) is determined by
where Ac is the actual conductor area and KF is the fill factor.
equation (23).
Typically the fill factor is 0.2-0.3 when a bobbin is used.
(8) STEP-8 : Determine the proper core and the number

(9) STEP-9 : Determine the wire diameter for each
of turns for output inductor
inductor winding based on the rms current.
When the forward converter has more than one output as
shown in figure 7, coupled inductors are usually employed to The rms current of the n-th inductor winding is obtained as
improve the cross regulation, which are implemented by
winding their separate coils on a single, common core.
2
rms ( 3 + K RF )
IL( n) = I o ( n ) ---------------------------
- (27)
3
DR2 L2
The current density is typically 5A/mm2 when the wire is
NL2
Np NS2
long (>1m). When the wire is short with small number of
VO2
turns, a current density of 6-10 A/mm2 is also acceptable.
DF2 CO2
Avoid using wire with diameter larger than 1 mm to avoid
severe eddy current losses and to make winding easier. For
high current output, it is better to use parallel winding with
NL1 multiple strands of thinner wire to minimize skin effect.
DR1
L1 (10) STEP-10 : Determine the diode in the secondary side

NS1 based on the voltage and current ratings.
DF1 CO1 VO1
The maximum voltage and the rms current of the rectifier
diode of the n-th output are obtained as
max N s ( n )
Figure 7. Coupled Output Inductors V D ( n ) = VDC ------------- (28)
NP
rms 2 D max
First, determine the turns ratio of the n-th winding to the ID ( n) = I o ( n ) ( 3 + K RF ) -------------
- (29)
3
reference winding (the first winding) of the coupled
inductor. The turns ratio should be the same with the
transformer turns ratio of the two outputs as follows.
(11) STEP-11 : Determine the output capacitor
Ns ( n ) NL (n ) considering the voltage and current ripple.
------------- = ------------- (23)
N s1 N L1 The ripple current of the n-th output capacitor is obtained as

5
the ouput capacitance of the MOSFET. Based on the power

loss, the snubber resistor with proper rated wattage should be
rms K RF Io ( n )
IC ( n) = ---------------------
- (30) chosen.
3
The ripple of the snubber capacitor voltage in normal
The ripple current should be equal to or smaller than the operation is obtained as
ripple current specification of the capacitor.
The voltage ripple on the n-th output is given by V D
∆ V sn = -----------------------
sn max
- (37)
C sn R sn f s
Io ( n ) ⋅ K RF
∆ V o ( n ) = -------------------------
- + 2KRF I o ( n ) R c ( n ) (31) In general, 5-10% ripple is practically reasonable.
4C o ( n ) fs
Vds
where Co(n) is the capacitance and Rc(n) is the effective series
resistance (ESR) of the n-th output capacitor. V sn
V DC
Sometimes it is impossible to meet the ripple specification
with a single output capacitor due to the high ESR of the
electrolytic capacitor. Then, additional LC filter (post filter)
can be used. When using additional LC filter, be careful not
to place the corner frequency too low. If the corner Vsn
frequency is too low, it may make the system unstable or
limit the control bandwidth. It is proper to set the corner ∆ Vsn
frequency of the filter to be around 1/10 to 1/5 of the
switching frequency.
T0 T1 T2 T3 T4
(12) STEP-12 : Design the Reset circuit.
Figure 8. Snubber Capacitor Voltage
(a) Auxiliary winding reset : For auxiliary winding reset,
the maximum voltage and rms current of the reset diode are
given by (13) STEP-13 : Design the feed back loop.
Since FPS employs current mode control as shown in figure
9, the feedback loop can be simply implemented with a one
max  Nr 
V Dreset = V DC pole and one zero compensation circuit.
 1 + ------
N 
- (32)
p
min
rms V DC Dmax D max FPS vo1' vo1
IDreset = ---------------------------------
- -------------- ( 33 )
Lm f s 3
vFB RD
Lp1
ibias
(b) RCD reset : For RCD reset, the maximum voltage and Rbias
iD
rms current of the reset diode are given by CB
1:1
B R1
CF RF
max
V DR = V DC + V sn (34)
431
min
rms V DC D max D max
I DR = ---------------------------------
- -------------- (35)
L m fs 3 R2
The power loss of the snubber network in normal operation

is obtained as Ipk
MOSFET
2 2 current
V sn 1 ( nV o1 ) 2nVo1 V sn
Loss sn = -----------
- = --- --------------------
- – ---------------------------
- ( 36 ) Figure 9. Control Block Diagram
R sn 2 L m fs L ⁄C m oss
For continuous conduction mode (CCM) operation, the
control-to-output transfer function of forward converter
where Vsn is the snubber capacitor voltage in normal using FPS is given by
operation, Rsn is the snubber resistor, n is Np/Ns1 and Coss is

6
(c) Place compensator zero (fzc) around fc/3.

ˆ (d) Place compensator pole (fpc) above 3fc .
ν o1 N p 1 + s ⁄ wz
- = K ⋅ R L ⋅ --------- ⋅ ------------------------
G vc = -------- ( 38 )
s1 1 + s ⁄ w p
ν ˆ N
FB
fp Light load
40 dB
1 1
where w z = -------------------- , w p = -----------------
Rc1 C o1 R L C o1
20 dB fp
and RL is the effective total load resistance of the controlled
output defined as Vo12/Po.When the converter has more than
0 dB Heavy load
one output, the DC and low frequency control-to-output
transfer function are proportional to the parallel combination fz
of all load resistance, adjusted by the square of the turns -20 dB
ratio. Therefore, the effective total load resistance is used in
equation (38) instead of the actual load resistance of Vo1. -40 dB
The voltage-to-current conversion ratio of FPS, K is defined 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
as
Figure 10. CCM Forward Converter Control-to-output
Transfer Function variation According to the Load
I pk I lim
K = ---------
- = -------
- (39)
V FB 3 Loog gain T
40 dB
where Ipk is the peak drain current and VFB is the feedback
voltage for a given operating condition.
20 dB fzc fpc
Figure 10 shows the variation of control-to-output transfer Compensator
function for a CCM forward converter according to the load. fp wi/wzc
Since a CCM forward converter has inherent good line 0 dB
fc
regulation, the transfer function is independent of input Control to output
voltage variation. While the system pole together with the -20 dB
DC gain changes according to the load condition.
fz
The feedback compensation network transfer function of -40 dB
figure 9 is obtained as 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
Figure 11. Compensator Design

ν̂ FB wi 1 + s ⁄ wzc
--------- = - ----- ⋅ --------------------------- (40)
ν̂o1 s 1 + 1 ⁄ w pc
When determining the feedback circuit component, there are
RB 1 1 some restrictions as follows.
where wi = -------------------------
-,w = ---------------------------------,w = ---------------
R 1 R D CF s zc ( RF + R 1 )C F pc R B C B
(a) The capacitor connected to feedback pin (CB) is related to
the shutdown delay time in an overload situation as
As can be seen in figure 10, the worst case in designing the
feedback loop for a CCM forward converter is the full load
condition. Therefore, by designing the feedback loop with T delay = ( VSD – 3 ) ⋅ C B ⁄ I delay (41)
proper phase and gain margin in low line and full load where VSD is the shutdown feedback voltage and Idelay is the
condition, the stability all over the operation ranges can be shutdown delay current. These values are given in the data
guaranteed. sheet. In general, 10~100 ms delay time is proper for most
The procedure to design the feedback loop is as follows: practical applications. In some cases, the bandwidth may be
limited due to the required delay time in over load
(a) Determine the crossover frequency (fc). When an protection.
additional LC filter (post filter) is employed, the crossover
frequency should be placed below 1/3 of the corner (b) The resistor Rbias and RD used together with opto-coupler
frequency of the post filter, since it introduces -180 degrees and the KA431 should be designed to provide proper operat-
phase drop. Never place the crossover frequency beyond the ing current for the KA431 and to guarantee the full swing of
corner frequency of the post filter. If the crossover frequency the feedback voltage of the FPS. In general, the minimum
is too close to the corner frequency, the controller should be cathode voltage and current for KA431 is 2.5V and 1mA,
designed to have enough phase margin more than about 90 respectively. Therefore, Rbias and RD should be designed to
degrees when ignoring the effect of the post filter. satisfy the following conditions.
(b) Determine the DC gain of the compensator (wi/wzc) to
cancel the control-to-output gain at fc.

7
V o – V OP – 2.5
-------------------------------------- > I FB (42)
RD
V OP
-------------
- > 1mA (43)
R bias
where VOP is opto-diode forward voltage drop, which is

typically 1V and IFB is the feedback current of FPS, which
is typically 1mA. For example, Rbias<1kΩ and RD <1.5kΩ
for Vo1=5V.

8
- Summary of symbols -
Aw : Window area of the core in mm2

Ae : Cross sectional area of the core in mm2
Bsat : Saturation flux density in tesla.
∆B : Maximum flux density swing in tesla in normal operation
Co : Capacitance of the output capacitor.
Dmax : Maximum duty cycle ratio
Eff : Estimated efficiency
fL : Line frequency
fs : Switching frequency
Idspeak : Maximum peak current of MOSFET
Idsrms : RMS current of MOSFET
Ilim : FPS current limit level.
Isec(n)rms : RMS current of the n-th secondary winding
ID(n)rms : Maximum rms current of the rectifier diode for the n-th output
Ic(n)rms : RMS Ripple current of the n-th output capacitor
IO : Output load current
KL(n) : Load occupying factor for n-th output
KRF : Current ripple factor
Lm : Transformer primary side inductance
Losssn : Power loss of the snubber network in normal operation
Npmin : The minimum number of turns for the transformer primary side to avoid saturation
Np : Number of turns for primary side
Nr : Number of turns for reset winding
Ns1 : Number of turns for the reference output
Po : Maximum output power
Pin : Maximum input power
Rc : Effective series resistance (ESR) of the output capacitor.
Rsn : Snubber resistor
RL : Output load resistor
Vlinemin : Minimum line voltage
Vlinemax : Maximum line voltage
VDCmin : Minimum DC link voltage
VDCmax : Maximum DC line voltage
Vdsnom : Maximum nominal MOSFET voltage
Vo1 : Output voltage of the reference output.
VF1* : Diode forward voltage drop of the reference output.
Vcc* : Nominal voltage for Vcc
VFa : Diode forward voltage drop of Vcc winding
∆VDCmax : Maximum DC link voltage ripple
VD(n) : Maximum voltage of the rectifier diode for the n-th output
∆Vo(n) : Output voltage ripple of the n-th output
Vsn : Snubber capacitor voltage in normal operation
∆Vsn : Snubber capacitor voltage ripple
Vsnmax : Maximum snubber capacitor voltage during transient or over load situation
Vdsmax : Maximum voltage stress of MOSFET

9
Appendix. Design Example using FPS design Assistant

Target System : PC Power Supply
- Input : universal input (90V-265Vrms) with voltage doubler
- Output : 5V/15A, 3.3V/10A, 12V/6A
FPS Design Assistant ver.1.0 By Choi

For forward converter with reset winding
Blue cell is the input parameters

Red cell is the output parameters
1. Defin e specifications of the SMPS

Minimum Line voltage (V_line.min) 180 V.rms
Maximum Line voltage (V_line.max) 265 V.rms
Line frequency (fL) 60 Hz
Vo Io Po KL
1st output for feedback 5 V 15 A 75 W 42 %
2nd output 3.3 V 10 A 33 W 18 %
3rd output 12 V 6 A 72 W 40 %
4th output 0 V 0 A 0 W 0 %
Maximum output power (Po) = 180.0 W
Estimated efficiency (Eff) 70 %
Maximum input power (Pin) = 257.1 W
2. Determin e DC link capacitor and the DC voltage range

DC link capacitor 235 uF
DC link voltage ripple = 29 V
Minimum DC link voltage = 226 V
Maximum DC link voltage = 375 V
3. Determin e the maximum duty ratio (Dmax)

Maximum duty ratio 0.4
Turns ratio (Np/Nr) 1 > 0.67
Maximum nominal MOSFET voltage = 750 V
4. Determin e the ripple factor of the output inductor current

Output Inductor current ripple factor 0.15
Maximum peak drain c urren t = 3.27 A
RMS drain current = 1.81 A
Current limit of FPS 4 A
∆I Io
∆I
KRF =
2I o
Ts
DT s
5. Determin e proper core and minimum primary turns for transformer

Switching frequency of FPS (kHz) 67 kHz
Maximum flux density swing 0.32 T --> EER2834
4
Estimated AP value of core = 9275 mm AP=12470
2
Cross sectional area of core (Ae) 86 mm Ae=86
Minimum primary turns = 49.0 T Aw=145

10
6. Determine the numner of turns for each outputs
Vo VF # of turns
Vcc (Use Vcc start voltage) 15 V 1.2 V 3.6 => 4 T
1st output for feedback 5 V 0.4 V 3 => 3 T
2nd output 3.3 V 0.4 V 2.06 => 2 T
3rd output 12 V 0.5 V 6.94 => 7 T
4th output 0 V 0 V 0 => 0 T
VF : Forward voltage drop of rectifier diode Reset winding = 50 T
Primary turns = 50 T
->enough turns
AL value (no gap) 2490 nH/T2
Transformer magnetizing inductance = 6.27499 mH --> EER2834
7. Determine the wire diameter for each transformer winding
Diameter Parallel Irms (A/mm 2)

Primary winding (Np) 0.68 mm 1 T 1.81 A 4.98
Reset windin g (Nr) 0.31 mm 1 T 0.08 A 1.04
Vcc winding 0.31 mm 1 T 0.10 A 1.33
1st output winding 0.68 mm 4 T 9.5 A 6.56
2nd output winding 0.68 mm 3 T 6.3 A 5.83
3rd output winding 0.68 mm 2 T 3.8 A 5.25
4th output winding 0 mm 0 T 0.0 A #DIV/0!
2
Copper area = 33.9262 mm
Fill factor 0.25
2
Required window area 135.705 mm --> EER2834 (Aw=145)
8. Determine proper core and number of turns for inductor (coupled inductor)
Cross sectional area of Inductor core (A 86 mm2 --> EER2834
Saturation flux density 0.42 T
Inductance of 1st output (L1) = 5.7 uH
Minimum turns of L1 = 6.5 T
Actual number of turns for L1 6 => 6 T
Number of turns for L2 = 4 => 4 T
9. Determine the wire diameter for each inductor winding
2
Diameter Parallel Irms (A/mm )
Winding for L1 0.68 mm 5 T 15.1 A 8.30
Winding for L4 0 mm 0 T 0.0 A #DIV/0!
Copper area = 25.4089 mm2
Fill factor 0.25
Required window area 101.636 mm2 --> EER2834(Aw=145)
10. Determine the rectifier diodes in the secondary side
Reverse voltage Rms Current

Vcc diode 55 V 0.10 A -->UF4003
1st output diode 22 V 9.5 A -->MBR3060PT
2nd output diode 15 V 6.3 A -->MBR3045PT
3rd output diode 52 V 3.81 A -->MBR20H100CT
4th output diode 0 V 0.00 A

11
11. Determine the output capacitor
ESR Current Voltage

Capacitance
ripple Ripple
1st output capacitor 4400 uF 20 mΩ 1.3 V 0.09 V
2nd output capacitor 4400 uF 20 mΩ 0.9 V 0.06 V
3rd output capacitor 2000 uF 60 mΩ 0.5 V 0.11 V
4th output capacitor 0 uF 0 mΩ 0.0 V #### V
12. Design the Reset Circuit

Reset diode rms current 0.08 A
Maximum voltage of reset diode 750 V -->UF4007
13. Design Feedback control loop
Contr ol-to-output DC gain = 3

Contr ol-to-output zero = 1,809 Hz
Contr ol-to-output pole = 261 Hz FPS vo ' vo
vFB RD
ibias
Voltage divider resistor (R1) 5 ㏀ R bia s
iD
Voltage divider resistor (R2) 5 ㏀ CB
1: 1
Opto coupler diode resistor (RD ) 1 ㏀ B
CF RF R1
431 Bias resistor (Rbias) 1.2 ㏀ 431
Feeback pin capacitor (CB) = 10 nF R2

Feedback Capacitor (CF) = 100 nF
Feedback resistor (RF) = 1 ㏀
Feedback integrator gain (fi) = 955 Hz

Feedback zero (fz) = 265.393 Hz
Feedback pole (fp) = 5307.86 Hz
60
16 9.80783 36 45 16 # -86.7 #
Contorl-to-output
25 9.78487 32 Compensator
41 25 # -84.9 #
40 40 9.7248 28 T37 40 # -81.9 #
63 9.58236 24 33 63 # -77.3 #
20 100 9.24037 20 29 100 # -70.4 #
Gain (dB)
160 8.46816 17 25 160 # -60.6 #

0 250 7.07174 14 21 250 # -49.4 #
10 100 400 4.77208 13 10000
1000 17 400 # 100000
-37.8 #
-20 630 1.96652 12 14 630 # -29.6 #
1000 -0.9856 11 10 1000 # -25.5 #
1600 -3.5451 11 7.3 1600 # -26.2 #
-40
2500 -5.2263 10 5.1 2500 # -31.3 #
4000 -6.2187 9.2 3 4000 # -40.8 #
0 6300 -6.6721 7.3 0.6 6300 # -52.3 #
10 100 1000
10000 -6.8719 4.5 10000
-2 #### # 100000
-63.5 #
16000 -6.9549 1.1 -6 #### # -72.6 #
-30
25000 -6.9867 -3 -10 #### # -78.6 #
Phase (degree)
40000 -7.0002 -6 -13 #### # -82.8 #

-60 63000 -7.0054 -10 -17 #### # -85.4 #
100000 -7.0075 -14 -21 #### # -87.1 #
-90
-120

12
Design Summary
• For the FPS, FS7M0880 is chosen. This device has a fixed switching frequency of 67kHz.
• To limit the current, a 10 ohm resistor (Ra) is used in series with the Vcc diode.
• The control bandwidth is 6kHz. Since the crossover frequency is too close the corner frequency of the post filter (additional
LC filter), the controller is designed to have enough phase margin of 120 degrees when ignoring the effect of the post filter.
Figure 12 shows the final schematic of the forward converter designed by FPS Design Assistant
MBR120H100CT
L3
UF4007 DR3
DReset NS2
V O3 12V
CO3
DF3
1000uF ×2
Nr
MBR3045PT L2
L p2 1.2uH
470uF + DR2
2CDC Np NS2 VO2
DF2 C p2
GBU606 N on-doubled Rstart CO2 1000uF 3.3V
V DC 560k 2200uF× 2
Doubled FS7M0880
2CDC MBR3060PT Lp1 1.2uH
470uF Drain L1
- R a 10 D D
a NS1 R1 V O1
S/S Vcc DF1 C p1
CL2 100nF CO1 5V
UF4003 470uF
FB GND 2200uF ×2
Ca Na
Css 22uF
1uF 1k
Line Filter Rbias
Rd
1.2k
5k
CL1 100nF CB 817A R1
10nF
1k 100nF
R L1
RF CF
1M
NTC Fuse KA431
5k
R2
AC line
Figure 12. The final schematic of the forward converter
KA1M0280RB,KA1M0380RB,KA1L0380RB,KA1H0680B,KA1M0680B,KA1H0680RFB,KA1M0680RB,KA1M0880B,KA1M0
880BF,KA1M0880D,KA5H0280R,KA5M0280R,KA5H0380R,KA5M0380R,KA5L0380R,KA5P0680C,FS7M0680,FS7M0880

13
by Hang-Seok Choi / Ph. D
FPS Application Group / Fairchild Semiconductor

Phone : +82-32-680-1383 Facsimile : +82-32-680-1317
E-mail : hschoi@fairchildsemi.co.kr
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPROATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
3/24/04 0.0m 002

 2003 Fairchild Semiconductor Corporation
Application Note AN-4105

Design Considerations for Switched-Mode Power Supplies
Using a Fairchild Power Switch (FPS) in a Flyback
Converter
Introduction MOSFET (SenseFET) and pulse width modulation (PWM)-
based control IC in one package. Moreover, they provide
Flyback, switched-mode power supplies (SMPS) are among enhanced IC functionality, thereby minimizing the number
the most frequently used power circuits in household and of additional components needed in an SMPS. Fairchild
consumer electronics. The basic function of an SMPS is to Power Switch (FPS) ICs are widely used in the power
supply regulated power to the load on the secondary, or out- circuits of a variety of equipment, such as color TVs,
put, side. An SMPS typically incorporates a power trans- printers, PCs, monitors, battery chargers, and AC adapters.
former, secondary-side rectifier diodes, a switching They typically incorporate a variety of enhanced protection
semiconductor device with control IC, and peripheral cir- functions and they greatly reduce power consumption in
cuitry. If the level of integration of the switching and control standby modes.
circuitry is not high enough, then additional, separate circuits
are required to accommodate all functions. Such additional This application note considers the three major functional
components raise the overall SMPS cost and sometimes blocks of an SMPS: Fairchild Power Switch (FPS), flyback
reduce reliability. converter, and transformer. It discusses a variety of issues
important to their design and use in the overall SMPS.
Fairchild power switches are highly integrated ICs for power
supply applications. They combine a high-voltage power
Vcc
3
32V Voltage
6.3V Sync. UVLO Ref.
Vck
2μA 1mA
OSC.
1 Drain
Feedback 4
2.5R S
Soft-Start
5 Q
& Sync.
R
R Source
LEB 2
Voffset Sense GND
5V
Rsense
Reset
SenseFET
S
7.5V Q
Reset Thermal R
Protection
OVP
Control IC
Figure1. Internal block diagram of a Fairchild Power Switch (FPS)
REV. 1.0.4 • 5/19/06

AN-4105 APPLICATION NOTE
1. Block Diagram and Basic Operation

of a Fairchild Power Switch (FPS)
1.1 Block Diagram (Figure 2) charges to 15V. Because only a small current
Figure 1 presents a block diagram of a Fairchild Power (<1mA) is allowed to flow in through the resistor during
Switch (FPS). It can be divided into several large, functional normal operation, this technique reduces the current dissi-
sections: under-voltage lockout circuitry (UVLO); reference pation in the SMPS start-up resistor.
voltage; oscillator (OSC); pulse width modulation (PWM) DC
block; protection circuits; and gate driving circuits. LINK Rg +
Ccc
1.2 Under-Voltage Lockout (UVLO) Vcc
3
A Fairchild Power Switch (FPS) under-voltage lockout Internal Bias
(UVLO) circuitry (Figure 2) guarantees stable operation of Power On
the IC’s control circuit by stopping and starting it as a Reset 5V
15V/10V Vref
function of the value of VCC (Figure 3). The turn off and turn Latch
UVLO
Comparator
on voltage thresholds are fixed internally at 10V and 15V, Vz
Good Logic
6V
respectively; therefore, the UVLO circuitry turns off the Fairchild Power
control circuit when VCC is lower than 10V and starts it Switch (FPS)
when VCC is higher than 15V. Once the control circuit starts
Figure 2. Detail of the under-voltage lockout (UVLO)
operating, VCC must drop below the 10V level for the circuitry in a Fairchild Power Switch. The gate
UVLO to stop the circuit again. Before switching starts, the operating circuit holds in a low state during UVLO,
IC current is less than 300µA. IC operation starts when CCC thereby maintaining the SenseFET at turn-off
Icc
[mA]
20
Power On
Reset Range
0.3
Vc
6V 10V 15V Vz [V]
Figure 3. Fairchild Power Switch (FPS) control circuit status vs. Vcc
1.3 Feedback Control Circuit

The Fairchild Power Switch (FPS) control IC uses a current comparator operates to turn it off again when the MOSFET
mode PWM and operates such that MOSFET current is current reaches a set value proportional to Vfb. The
proportional to the feedback voltage Vfb. This limits the MOSFET turn-off operation is as follows: (1) the internal
MOSFET current at every cycle. It also offers other (R+2.5R) voltage divider sets the voltage fed back to one
advantages, such as a well-regulated SMPS output voltage input of the feedback comparator at Vfb /3.5; (2) a current
with input voltage changes. This method of control also proportional to the drain current flows to the MOSFET sense
works successfully in SMPSs used for monitors, which may terminal, making Vsense proportional to the drain current;
have a broad range of synchronizing frequencies to and, (3) when Vsense becomes greater than Vfb, the output of
accommodate. As shown in Figure 4, the Fairchild Power the feedback comparator goes high, turning off the
Switch (FPS) oscillator turns on the MOSFET. The feedback MOSFET. Figure 4 also shows that the circuit is designed to
REV. 1.0.4 • 5/19/06 2

use an opto isolator in the feedback loop. This is appropriate functions as those provided by the circuit of Figure 4; fine
for an off-line design where input to output isolation is control of the output voltage through Vfb. Similarly, other
required. Cfb improves the noise characteristics. If the appropriate devices are Fairchild’s LM431/TL431/KA431
control IC incorporates an error amp as in Fairchild’s series of three terminal shunt regulators. These have a very
KA3842B/3B/4B/5B current mode PWM controller ICs for sharp turn-on characteristic much like a Zener diode and are
SMPSs, a resistor and capacitor are required to provide the widely used in SMPS secondary-side error amplifiers.
feedback to the error amp. This would provide the same
Precision SPS(FPS)
Fairchild Power Switch
Current Source
Vck Idrain
2uA 1mA
Vfb OSC.
#4 #1
5V S
2.5R On
Cfb
Vfb* Q #2
R Sense
R
Vss Off Ioffset
#5
Css Vsense
Reset Rsense Isense
Figure 4. Fairchild Power Switch (FPS) feedback circuit appropriate for off-line SMPS use (current mode PWM)
1.4 Example Fairchild Power Switch (FPS)

Control Circuit
Figure 5 shows two approaches to control feedback with a
Fairchild Power Switch (FPS). The design in Figure 5a uses
the LM431 regulator and that of Figure 5b uses a Zener diode.
Even though the Zener diode approach is cost effective, the
output regulation is relatively poor.
In Figure 5a, C1, together with R1, produces a high-frequency
pole formed by the internal 3.5kΩ resistor and Cfb in the
compensation network. R4 limits the maximum current of the
photodiode to 2.3mA [(12V - 2.5V - 2V) /3.3KΩ, where 2.5V
is the LM431's saturation voltage and 2 V is the photodiode's
voltage drop]. Cfb should be determined by considering the
shutdown delay time (see Section 2.1). In Figure 5b, R3 sets a
fixed current to the Zener diode to stabilize its voltage.
Fairchild Power Switch(FPS)

Vck SPS
2uA 1mA
Vo, 80V 12V PC817 Vfb OSC.
#4
R3 S
Cfb 2k 2R
C1 1k
33n
R1 33n
Vfb* Q
33k R4 R R
1k
3.3k
Ioffset
10n
R2 KA431 Sense
C2 Rsense
1k LM431
(a) Control
ControlCircuit
circuitusing
thatKA431(LM431)
used KA431(LM431)
Control IC
Fairchild Power Switch(FPS)

Vck SPS
2uA 1mA
Vo, 80V 12V PC817 Vfb OSC.
#4
R1 Cfb S
R3 2k 2R
33k
1k 33n Vfb* Q
R
1k R
2.2k
C1 Ioffset
0.1u
Sense
Rsense
R2
Vz
(b) Control
ControlCircuit
circuitusing
thata used
Zener the
Diode Control
zener IC
diode
Figure 5. Fairchild Power Switch (FPS) feedback control circuit
1.5 Soft-Start Operation diode DS turns off. No more current flows to it from the
Normally, the SMPS output voltage increases from start up 1mA current source. Cs then continues to charge to 5V
with a fixed time constant. This is due to the capacitive through the 50kΩ resistor.
component of the load. At start up, therefore, the feedback
signal applied to the PWM comparator's inverting input
reaches its maximum value (1V) because the feedback loop
is effectively open. Also at this time, the drain current is at
its peak value (Ipeak) and maximum allowable power is being
delivered to the secondary load. When the SMPS pushes
maximum power to the secondary side for this initial fixed
time, the entire circuit is seriously stressed. Use of a soft-
start function avoids such stresses. Figure 6 shows how to
implement a soft-start for a Fairchild Power Switch (FPS).
At turn on, the soft-start capacitor CS on pin 5 of the
Fairchild Power Switch (FPS) starts to charge through the
1mA current source. When the voltage across CS reaches 3V,
REV. 1.0.4 • 5/19/06 4

absence of an external sync signal, the voltage across Ct oscil-
1 0V Fa ircPower
Fairchild hild Switch
Pow e(FPS)
r lates at the basic frequency of 20kHz. In the presence of a
Sw itc h (SPS) sync signal, however, the Set signal goes high because VCt
2㎂ 1㎃
charges to the high threshold following the external sync
signal and, ultimately, the Set signal, which determines the
PW M switching frequency, synchronizes to the external sync signal.
5V Co mp a ra to r
Ds
It is necessary to limit the Set signal's high duration to 5% or
－
50k less of the full cycle. As the Set signal drops low, the gate
＋ turns on. If the device is not synchronized to the horizontal
scan of the monitor, noise appears on the screen. When the Set
#4 #5 signal goes high, the sync is synchronized with the horizontal
KA5XX Series scan flyback. Because the high duration is 5% (maximum) of
Cs
E xte rn a l
the full cycle, the start of the horizontal scan (as the Set signal
A
S yn c In put goes low) turns-on the switch. The switch turn-on noise,
Rs KKA2SXX
A 5S X X therefore, is hidden in the horizontal blanking period at the far
KKA3SXX
A 5Q X X
B S eries left of the monitor display.
Figure 6. Soft-start circuit

When the voltage across CS exceeds 3V, the voltage at the Fairchild Power Switch(FPS)
SPS
comparator’s inverting terminal no longer follows the voltage 1㎃
across CS. Instead, it follows the output voltage feedback
signal. In shutdown or protection circuit operation, capacitor
PWM
CS is discharged, to enable it to charge from 0V at restart. 5V comparator
－
1.6 Synchronization
V CS #5 ＋
In an SMPS intended for use with monitors, synchronization
is handled differently from a general purpose SMPS. For External Cs
Sync
monitor use, it is necessary to prevent noise from appearing on Input
VRS V COMP
the monitor display. To accomplish this, it is necessary to －
OSC.
synchronize the SMPS switching frequency with the Rs
6.3V ＋
Dsync
monitor’s horizontal sync frequency. The monitor’s horizontal
Sync
scan flyback signal is commonly used as the external sync comparator
signal for the SMPS. By synchronizing the switching with the
horizontal scan’s flyback, the switching noise is positioned at Figure 7. Synchronization circuit
the far left of the monitor display where it cannot be seen.
Figure 7 shows how to implement the external circuit for 2V
V RS
synchronization. The external sync signal, applied across 0V
resistor Rs, cannot drop below 0.6V because of diode Dsync.

V CS
After the conclusion of the initial soft start, the voltage across 5V
Cs remains at 5V until the external sync signal is applied, at 0V

which point, it looks like VRs of Figure 8. The sync
V C OMP
comparator compares VCs against a 6.3V level and produces
0V
the comparator output waveform, Vcomp of Figure 8.
V ThH
A Fairchild Power Switch (FPS) has an internal timing V CT
V ThL
capacitor, Ct. Figure 8 shows that when the voltage on Ct, VCt, 0V
reaches an upper threshold, it begins to discharge; then, when V ck

it reaches a lower threshold, it again starts to charge. This
0V
operation is controlled by the internal oscillator. The oscillator
Figure 8. Synchronization circuit operation
output signal, VCk in Figure 8, which goes low when Ct
recharges and high when it discharges, is applied to the
Fairchild Power Switch (FPS) S/R Latch Set terminal. In the
2. Fairchild Power Switch (FPS) waits for a specified time. If the overload is still present after
Built-In Protection Circuits this, it is considered a true overload and the device shuts
down.
Since a Fairchild Power Switch’s built-in protection circuits
do not require additional external components, reliability is The Fairchild Power Switch (FPS) has a current control that
increased without increasing cost. Note that the protective prohibits current flow above a set maximum, which means
circuitry can completely stop the SMPS operation (latch the maximum input power is limited at any given voltage.
mode protection) until the power is turned off and on again. Therefore, if the output load tries to draw more than this
It can force the control voltage to restart above the ULVO level, Vo (Figure 9) drops below the set voltage and LM431
level should the latch be released below ULVO (Auto can draw only a given minimum current. As a result, the opto
Restart Mode protection). coupler secondary current drops to almost zero. Almost the
entire current flow at the node is from the Fairchild Power
2.1 Output Overload Protection Switch (FPS) 1mA current source. Hence, the internal 3kΩ
An overload is any load greater than the load defined as resistor (2.5R + R = 3KΩ) moves Vfb to 3V. From this point
normal for operation. This is not a short circuit. The on, however, the 5µA current source starts to charge Cfb and,
Fairchild Power Switch (FPS) overload protection because the opto coupler secondary current is almost zero,
determines whether the overload is true or merely transient. Vfb continues to increase. When Vfb reaches 7.5V, the
Only a true overload triggers the overload protection. When Fairchild Power Switch (FPS) shuts down.
the Fairchild Power Switch (FPS) senses an overload, it
Fairchild Power Switch

SPS(FPS)
Vck
2uA 1mA
Vo Vfb OSC.
#4
D1 D2 2.5R S
Cfb 2R
Vfb*
Q
R
R
Ioffset
LM431
KA431 Sense
Rsense
7.5V Reset R
R
Q
Q Shutdown
Thermal S
S
Shutdown
Figure 9. Fairchild Power Switch (FPS) overload protection circuit
The shutdown delay interval is therefore determined by Cfb. Cd extends the delay time to the desired shutdown point.
When Cfb is 10nF, the shutdown delay t2 (see Figure 10b) is Where transients are insignificant and good dynamic
about 9mS. With Cfb at 0.1µF, t2 is about 90ms. Such delay response is not required, eliminate Cd and the Zener, thereby
intervals do not allow the typical transients observed to shut eliminating the added costs.
down the Fairchild Power Switch (FPS). If a longer delay is
needed, Cfb cannot be made arbitrarily large because it is
important in determining the dynamic response of the
SMPS.
When a large value of Cfb is necessary, a series-connected
capacitor and Zener diode can be connected across Cfb, as
shown in Figure 10a. In this combination, when Vfb is below
3V, the low-valued Cfb allows the SMPS to have a good
dynamic response. When Vfb is above 3.9V, the high-valued
REV. 1.0.4 • 5/19/06 6

Fairchild Power Switch(FPS) V
SPS
2uA 1mA 7.5V
Vfb
Vo
#
D1 D2
Cf b 4 3.9V
Cd 3V
b Vfb*
Vz=3.9V 0
t
LM431
KA431 t1 t2 t3
7.5V
Shutdown
Tim e Constant 2uA = Cfb*0.9V/t2
= 3.5R*Cfb 2uA = Cd*3.6V/t3
(a) < SPS
<Fairchild Powerlong Delayed
Switch Shutdown >
(FPS) Long-Delayed Shutdown>
(b)
Figure 10. Long delay shutdown
2.2 Output Short Circuit Protection

When the SMPS’s output terminal is short circuited, the the maximum transformer current. For this case, if the output
input current is at maximum. The output power however, is short circuits, Vcc increases and, after a specified delay, the
not a maximum because there can be no load voltage since protection circuit operates, entering the latch mode.
the load is a short circuit. Under such conditions, the output However, when Rsd is made sufficiently large, Vcc can
short-circuit protection operates as follows: become smaller than n'Vo. Therefore, if the output short
circuits, Vcc drops; but, if Ccc (see Figure 11a) is sufficiently
When the output load short circuits a relatively large
large, Vcc stays at a level higher than the UVLO's lower
transformer winding in the SMPS, the Fairchild Power
threshold voltage (10V) until Vfb reaches 7.5V (Figure 11c-
Switch’s MOSFET current becomes much greater than Ipeak
2) and latch mode protection starts. In contrast, if Ccc is
because the inductor’s magnetic core is unable to reset. This
small enough, Vcc approaches the UVLO's low threshold
is due to low transformer coil voltage at turn off. This occurs
before Vfb reaches 7.5V (Figure 11c-3), and the UVLO
because the current remaining in the inductor during the
operates instead of the protection circuit, stopping the device
Fairchild Power Switch’s minimum turn-on time cannot
switching. In such a case, if Vcc exceeds the ULVO's upper
decrease by that amount during the remaining turn off time.
threshold voltage (15V), auto restart operates again. Rsd,
Even though it is a large current, it does not unduly stress the
Ccc, and Cfb have effects even at start up and power down, so
MOSFET, but does greatly stress the transformer’s
their values must be decided carefully. Experiments have
secondary coils and the secondary-side rectifiers.
indicated that 10-20W is most appropriate for Rsd.
In most flyback or forward converters, the controller gets its
power from a small secondary bias winding in the
transformer. Furthermore, this controller voltage is propor-
tional to the output voltage (see circuit of Figure 11a). This is
fairly straightforward because, for a flyback converter, the
coil voltage, when the switch turns off, is proportional to the
output voltage.
For a forward converter, the transformer average voltage at
turn off is proportional to the output voltage. For a flyback
converter SMPS, the output short-circuit protection circuit
can be operated in either latch mode or auto restart mode.
The change in Vcc as a function of Rsd is shown in Figure
11b. Rsd is shown in Figure 11a. When Rsd is zero, Vcc
reaches the maximum value of Vtx (see lower primary
winding, Figure 11a), i.e., n'Vsn/n, which is proportional to
n :1 Vo
Vin
V in V sn
Fairchild
S P S Power Switch (FPS) 1
LM431
C o n t ro l
5 IC K A 4 31
2
4 3
V fb V cc
Rsd
n *: 1
C fb Ccc V tx
(a ) F ly b a c k c o n v e rt e r
No Rsd
n *V s n / n
V tx n *V o
L o w Rsd
L a rg e R s d
0
n * V in / n
(b ) The
F lavoltage
y b a c k Vtx
c owaveform
n v e rt e r of
c oNnBtand
ro lleVrCCv(the
o lt arectified
g e a n dVNB
R),s depending
d depend one n t V cc
Rsd
(1 ) S h u t do w n
V cc
(2 )
(3 ) UVLO
1 0V S h u t do w n
7 . 5V
3V
V fb
Cvcc
0V t
O u t p ut s h o rt UVLO S h u t do w n
,
(c)) V c c a n d V f b w a v e f o rm s d e p e n d in g o n t h e re la t iv e s iz e o f C v c c a t o u t p u t s h o rt
(C
Figure 11. Operation of the SMPS flyback converter’s output short-circuit protection (latch mode)
REV. 1.0.4 • 5/19/06 8

2.3 Fast Protection Without Delay operate sufficiently fast. In such a case, when the transistor is
As mentioned above, that the Fairchild Power Switch (FPS) turned off, the protection shifts to auto restart mode for
shutdown capability is associated with a delay to allow normal operation. It is also possible to use this circuit as an
normal transients to occur without shutting down the system. output-enable circuit. Fast latch-mode protection can be
In effect, this restricts the protection range. If fast protection implemented by adding a photocoupler. Thus, when the
is required, additional circuitry is necessary. As shown in output terminal latch-mode transistor turns on, a large
Figure 12, a transistor is used to force the feedback current flows through the photodiode PC2. A large current
photodiode current to increase, causing the primary side Vfb therefore flows through the primary phototransistor, which
to be forced below 0.3V. Therefore, the Fairchild Power increases Vfb rapidly. This executes fast latch-mode
Switch (FPS) stops switching. Depending on the magnitude protection with no time delay.
of the photodiode current, the protection can be made to
n:1 Vo
Vin
V in V sn
PC1
Fairchild Power Switch (FPS)

SPS 1
5 Con trol
IC Vo
2 KA 431
LM431 Bu rst Mo d e
P C2 Shutdown
Sh u t Down
4 3
Vcc
Vfb
Rsd
n *:1
Ccc Vtx
P C2 La tch Mo d e
P C1 Cfb Shutdown
Sh u t Down
Figure 12. A fast protection circuit without a shutdown delay
2.4 Over-voltage Protection (FPS) over-voltage protection circuit operates. Since VCC is
The Fairchild Power Switch (FPS) has a self-protection proportional to the output, in an over-voltage situation it also
feature that operates even when faults exist in the feedback increases. In the Fairchild Power Switch (FPS), the
path. These could include an open or short circuit. On the protection circuit operates when Vcc exceeds 25V; therefore,
primary side, if the feedback terminal is short circuited, the in normal operation, Vcc must be set below 25V.
voltage on it is zero and the Fairchild Power Switch (FPS) is
unable to start switching.
If the feedback path open circuits, the protection circuit
operates as though a secondary overload is present. Further,
if the feedback terminal looks open due to some fault in the
primary feedback circuit, the primary side could switch at
the set maximum current level until the protection circuit
operates. This causes the secondary voltage to become much
greater than the rated voltage. In such a case, if there were no
protection circuit, the fuse could blow or, more serious, a fire
could start. It is possible that, without a regulator, devices
directly connected to the secondary output could be
destroyed. Instead, however, the Fairchild Power Switch
3. Noise Considerations at Switch Turn On

3.1 SMPS Current Sensing 1. Reverse recovery current is generated when the SMPS
Whether an SMPS is current-mode or voltage-mode operates in continuous-conduction mode (CCM; see Section
controlled, or uses some form of non-linear control, it 4.1). If the MOSFET is turned on while the rectifier diode is
requires the protection afforded by current-sensing conducting, the diode, during its reverse recovery time, acts
capabilities. Even though most current sensing uses a like a short circuit; therefore, a large current spike flows in
sensing resistor or a current transformer, there are instances the MOSFET. There are three ways to reduce the magnitude
where a MOSFET is used by the SMPS to further reduce of this (reverse recovery) current: use a fast recovery diode;
current sensing losses. The Fairchild Power Switch (FPS) reduce the MOSFET’s gate-operating current at turn on; or,
switching element is a SenseFET. This minimizes any power increase the transformer leakage inductance.
losses in the sense resistor, which is integrated onto the 2. The total capacitance on the MOSFET’s drain side
controller chip. includes the parasitic capacitor Cds between the drain and the
source terminals, the junction capacitance of the snubber
3.2 Current Sensing Waveform Noise After diode, and the capacitance of the transformer windings. At
Turn On turn on, the total equivalent capacitor discharges through the
A leading edge spike is present on the current sense line MOSFET.
when the SMPS switching device turns on. It arises from 3. As shown in Figure 13, the MOSFET gate-operating
three causes, as shown in Figure 13: (1) reverse recovery current also flows through the current-sensing resistor.
current; (2) charge/discharge current of the MOSFET shunt
capacitance; and (3) MOSFET gate-operating current.
Vin Vo Vin Vo Vin Vo
Rg Rg Rg
Control Control Control

IC Rf IC Rf IC Rf
Rs R Rs
Cf Cf Cf
s
Charge/Discharge Current MOSFET Gate Operating Current

Reverse Recovery
Reverse Recovery Current
Current Charge/Discharge Currentof of
the Equivalent Capacitor
MOSFET Gate Operating
the equvalent capacitor
Current
Figure 13. Current sensing waveform noise after turn on
REV. 1.0.4 • 5/19/06 10

3.3 Dealing With Leading Edge Noise 3.3.1 Burst-Mode Operation
Among the measures taken to reduce leading edge noise, the The aforementioned method can be viewed as an example of
most commonly used technique is the RC filter. As shown in burst mode operation. Burst-mode operation, by reducing the
Figure 14a, the RC filter is effective against the noise, but its switching frequency, is one of the most useful ways to
disadvantage is that it distorts the current sensing signal so improve SMPS efficiency at light loads and to reduce the
that accurate current sensing becomes difficult. standby input power of household appliances. Note that
burst-mode operation is not a burst oscillation (as in ringing
Furthermore, a large RC value may be difficult to implement choke conversion circuits), which can bring about reliability
on an IC and may even require a bigger chip. The technique problems. There are mainly two types of true burst-mode
of leading edge blanking (LEB), as presented in Figure 14b operation: one type lowers the switching frequency equally;
and 14c, overcomes the distortion disadvantage of the RC the other switches at normal frequency for a fixed time and
technique. Since the problem noise arises just after turn on, if stops the control IC operation for a large number of cycles.
a circuit is inserted that ignores the current sensing line for a Even though, in the first method, the control IC continues to
fixed time just after turn on, operation can continue normally consume power, the output voltage ripple is minimized.
regardless of the noise. Whatever the details of the location
and type of circuit used, the basic idea is to maintain a The second method can be a useful way to reduce the
minimum turn-on time; to use the shortest turn-on time that minimum input power at standby (since the standby power is
cannot be terminated once turn-on starts. Duty ratio control greatly reduced when the IC is stopped). Indeed, it is often
with a minimum turn-on time is implemented through a non- used in cell phones to reduce the DC/DC converter’s power
linear control method with a very wide control range relative consumption in standby mode. However, it has the
to a linear control. The non-linear control operates such that disadvantage of a larger output voltage ripple. Currently,
if load conditions require a turn-on time of 400ns when the Europe restricts household appliance standby input power to
minimum turn-on time is set at 500ns, one switching cycle less than 5W and, in time, it will be required to be less than
turns on at 800ns. The next cycle is missed, ensuring that the 3W. For such needs, burst mode operation is a powerful
average turn-on time is 400ns. In this case, every other cycle method to satisfy the requirement for reduced standby input
is missed. This is pulse skipping. In this case, the switching power.
frequency will be half that of a linearly controlled system,
thereby improving SMPS efficiency at light loads. The input
power is therefore minimized. The Fairchild KA34063 DC/
DC converter is an example of a non-linear control IC.
Rg MO S FE T
PW M
IC
Rf
C u rre n t
S e n s in g
Cf Rs
(a)
< N oise elim ination using R C filter >
V ck Vi Vo
OSC
LEB
Ifb S Vq
V fb Va Q
R
C fb Ifb
Vb
F e e d ba c k
V is C ir c u it
(b)
< Internal block diagram for noise elim ination using LE B >
V ck
Va
0
V fb
V is
0
Vb
0
Vq
0
(c) Noise elimination and waveforms in LEB

< N oise elim ination and w aneform s in LE B >
Figure 14. Leading edge blanking
REV. 1.0.4 • 5/19/06 12

4. Flyback Converter Operation
4.1 Operation In Continuous Conduction Mode V i T ON = nV O T OFF (3)
(CCM)
Figure 15 shows a typical flyback converter. When the current nVO T ON D (4)
through the converter’s inductor is always greater than zero ------------ = --------------
- = -------------
Vi T OFF 1–D
within a switching cycle, the converter is said to be operating
in the continuous conduction mode (CCM). Figure 16 shows the input and output currents become:
the waveforms of CCM operation, which operates as follows. I i = DI Lm, AVG (5)
4.1.1 For t0 ~ t1 = TON I O = n ( 1 – D )I Lm, AVG (6)

At t0, the MOSFET turns on. Immediately before t0, the
hence the input and output powers are equal. An ideal
inductor current is flowing through diode D, but when the
waveform is shown here because the effect of leakage
MOSFET turns on, D turns off, thereby isolating the output
inductance has been ignored. In reality, leakage inductance
terminal from the input terminal. At MOSFET turn on, its
causes ringing.
VDS goes to zero and VD becomes (Vo + Vi/n). During the
ID D IO
interval after MOSFET turn on (i.e., from t0 on), Vi is
applied to Lm, so ILm increases linearly with a slope, as IL m IC
shown by the following equation: VD RO
VL m Lm CO VO
V
Slope = -------i- (1)
Lm Vin ID S n:1
When the energy flow is examined, it appears that the input VD S

power source supplies energy to Lm while the MOSFET is on.
However, since the energy in Lm continues to increase while
the output terminal is isolated from the input terminal, it is Co
Figure 15. A typical flyback converter
that has to supply the output current during this interval.
V GS
ON OFF
4.1.2 For t1 ~ t2 = TOFF 0
TON T OFF
At t1, the MOSFET turns off. At the instant of turn off, the VDS
V i+ n V O
inductor current that flows through the MOSFET starts to
0
flow through diode D. When D turns on, VDS becomes
(Vi+nVo). During this interval, the voltage nVo is applied to V Lm A Vi
0
Lm so that ILm decreases in a straight line with the following B nV 0
slope:
VD
nV O V 0 + V i/ n
Slope = -----------
- (2)
Lm 0
S lo p e =V i/ L m S lp o e = n V O /L m
When the energy flow during this interval is examined, it
ILm
appears that the inductor energy is delivered to the output.
The energy in Lm is reduced by the amount of energy it 0
delivers to the output. When the MOSFET turns on again, at ID S
t2, one switching cycle ends.

0
4.1.3 Relationship Between Input and Output ID

IC
0
As shown in Figure 16, the colored areas A and B of the 0
IO
t0 t1 t2 t3
waveform VLm (the voltage applied to the inductor) must be
equal because the average voltage of the inductor or Figure 16. Flyback converter operating waveforms in
continuous current mode (CCM)
transformer in steady state is always zero. Therefore:
4.2 Discontinuous Conduction Mode (DCM) .

V i T ON = nV O T* OFF (8)
The appearance of an interval in which the inductor current
becomes zero during a switching cycle marks flyback con- VO T ON D*
-------- = -----------------
- = ---------------- (9)
verter operation as discontinuous conduction mode (DCM). Vi T* OFF 1 – D*
As shown in Figure 17, the voltage waveform applied to the
inductor, VLm, becomes more complex in DCM. To avoid Deriving the above equation again, using Io and the fact that
difficulties in computation, TOFF is not used. Instead, three the input and output powers are equal, Vo is obtained as:
input and output relationships of a converter are derived 2
( V i T ON )
using TOFF* the time when the output rectifier diode is actu- V O = ---------------------------------------------------------------------- (10)
IO
ally conducting. 2 ----- -L (T + T OFF ) + V i
n m ON
V GS
ON OFF
0 The following equation represents the input power:
1 2
(11)
VD S P IN = --- L m I Lm,(peak) fsw
V i+nV O
2
Vi
0
where fsw is the switching frequency.
VL m
A Vi V i+nV O
0
B nV 0 4.3 Flyback Converter Design
4.3.1 Turns Ratio Considerations

VD
V O +V i/n
VO The turns ratio of an SMPS’s flyback converter transformer
0
TOFF * is an important variable. It affects the voltage and current
TON T OFF
levels associated with the primary-side switching device and
ILm
Slope
Slpoe=V i/Lm Slope=nV O /L m the secondary-side rectifier, as well as the number of turns
on the transformer and the current through it. A frequently
0
discussed design concept suggests operating at maximum
duty ratio when the input voltage is a minimum. For
ID S simplified calculations, assume that operating conditions
change as listed below:
0
- Vac input: 85 ~ 265Vac
ID
IC
- Vdc (rectified voltage): 100 ~ 400Vdc
0
0
IO - Output voltage: 50Vdc
t0 t1 t2 t3
- Inductor current: Continuous conduction mode (CCM)
Figure 17. Flyback converter operating waveforms in operation assumed.
discontinuous current mode (DCM)
The input power taken by the DC source is the product of the
The boundary condition between DCM and CCM is: DC voltage and average input current. Using a wide duty
Vi cycle to deliver equal average current reduces efficiency. A
I i + I O = ----------
-T (7) narrow duty cycle increases the effective current on the pri-
2L m ON
mary side, increasing the operating temperature of the pri-
The following input-output relationship in DCM is derived mary winding and the MOSFET. It is best to decide on a
using the fact that the colored areas A and B of VLm in Fig- turns ratio, n, based on the device used. If the voltage on the
ure 17 must always be equal because, in steady state, the primary side MOSFET is relatively low (e.g., 600V), make n
average inductor (or transformer) voltage is always zero. small; if it is on the high side (e.g., 800V), make n large. As
the value of n increases, the primary side switching device
current and the secondary-side rectifier diode voltage
decreases. Hence, with high output voltage and multiple
secondary side outputs, it is advantageous to increase n.
REV. 1.0.4 • 5/19/06 14

4.3.2 Deciding the Operating Current Mode side current. The gain is at the low-frequency end where core
loss is not a problem since only a minimum number of turns
As discussed in Sections 4.1 and 4.2, there are two different need be wound. Also, turn-on loss is not a serious problem
operating current modes possible in a flyback converter: the due to the low input current. Other losses; such as eddy
continuous conduction mode (CCM), and the discontinuous current, skin effect, proximity effect, etc., are not significant.
conduction mode (DCM). The advantages and disadvantages A more clearly defined advantage of DCM operation is that
of each are reviewed below to help the designer make the it permits the use of a slow, low-cost secondary rectifier
best choice. diode. In contrast to the continuous conduction mode, in the
discontinuous conduction mode, the effective current is
4.3.2.1 Characteristics of the Discontinuous higher, requiring the use of heavier wire and thicker coils.
Conduction Mode Therefore, DCM does not bring an advantage insofar as
In a flyback converter design, if discontinuous conduction transformer construction is concerned. Moreover, DCM
occurs just at minimum input voltage and maximum output causes the MOSFET operating temperature to increase
power, discontinuous conduction must be considered to be because of the large effective primary-side current, as
the case for all input conditions. The flyback converter’s described in Section 4.3.1.
input power in discontinuous conduction mode can be
expressed as: 4.3.2.2 Characteristics of the Continuous
Conduction Mode
1 2
(12)
P I = --- L m I P fsw Since the coils’ effective current is decreased, CCM brings
2
the advantage of lighter wire. The smaller effective current
Regardless of any changes in input voltage, the power also reduces MOSFET heating. This is a definite advantage
equation indicates that the input current is limited by the for average input current. On the other hand, CCM operation
peak value of the current flowing through the MOSFET in requires consideration of the rectifier diode’s reverse
the transformer primary. A Fairchild Power Switch (FPS) recovery current. Depending on the diode’s reverse recovery
has an integrated over-current protection feature (see Section time (trr), the reverse recovery current may stress the diode
2.1, above). This feature does not require external and increase the loss at its end terminals. It is therefore
components and operates across the range of input current. necessary to use a diode with the minimum trr possible
However, the fixed-operating current of DCM, tends within the allowable cost range.
somewhat to offset the effect of the larger effective primary-
n Vi = 100V Vi = 400V Merits & demerits

1 Voltage applied to switch device is low
VDS
VDS
nVO = 67V
nVO = 67V Effective current in switching device and
Vi = 100V primary winding is low
0
Vi = 400V Voltage applied to rectifier diode is high
Output voltage ripple is small
0 Control must be done through short turn-on
VD
VD time
Vi/n = 75V Vi/n = 267V
VO = 50V
0
VDS = 167V 0 VO = 50V
VD = 125V
VDS = 467V
VD = 317V
VDS VDS nVO = 100V

nVO = 100V
Vi = 100V VLm VD
0 Vi = 400V
Vi
VD 0 n:1
Vi/n = 50V VD VDS
VO = 50V Vi/n = 200V

0
VDS = 200V
VD = 100V
0 VO = 50V Intermediate Design Method

VDS = 500V
VD = 250V
VDS
Voltage applied to switch device is high
VDS
nVO = 150V
nVO = 150V Effective current in switching device and
Vi = 100V primary winding is high
0
Voltage applied to rectifier diode is low
Vi = 400V Output voltage ripple is large
Control must be done through long turn-on
0
VD
VD
time
Vi/n = 33V
VO = 50V
0 Vi/n = 133V
VDS = 250V
VD = 83V VO = 50V
0
VDS = 550V
VD = 183V
Figure 18. The current and voltage ratings required on the primary-side switching device and the secondary-side
rectifier diode depend on the turns ratio (n) selected
4.3.2.3 Designer’s Choice on loss could be a major problem, a CCM design would be
As is clear from the above discussion, DCM operation can more advantageous. In conclusion, the system designer must
be advantageous in cost and efficiency, if the input is small decide between the two modes to best fit the characteristics
and it is required to precisely control the input power of the system being designed.
through the primary side switch (MOSFET) current.
On the other hand, for large inputs and where switching turn
REV. 1.0.4 • 5/19/06 16

5. The Transformer
5.1 Why a Transformer is Needed using a transformer to lower the voltage to 10V would allow
There are three reasons for needing a transformer in a power an on time of about 10µs. This is strategy lowers cost and
conversion circuit. The first reason is safety. A transformer raises efficiency. The third reason to use a transformer has to
affords electrical isolation between the primary and do with high voltages and voltage fluctuations. For example,
secondary sides, as shown in Figure 19a. In addition, a true even though all control for a 1000V supply is handled by the
ground on the output side helps prevent electric shock. The 5V power source on the GND side, a transformer is
second reason is for voltage conversion. For example, if a necessary if power is needed for current sensing at the
DC/DC converter (such as the buck converter shown in 1000V output terminal or for other control. If the isolation
Figure 19b) switching at 50kHz is used to obtain 5V from voltage between the transformer windings is sufficient, a
100V, the duty cycle would only be 5%. Using a 50kHz 1000V potential difference can be safely maintained
switching frequency, the control circuit may have only about between the primary and secondary windings and power can
1µs to act, which is not an easy task. Even if this were be delivered. Further, a transformer is also required when the
possible, the internal voltage and current for each element power GND has a sudden potential fluctuation, as in a half-
would be very large, reducing efficiency. The problem is bridge converter, gate drive power source.
aggravated at high output current. In the above example,
AC220V DC GND
& Rectifier Output Vin=100V Vo=5V
100V ----> Duty 5% ----> 5V

Electric Shock
short when touched Safe to touch 50kHz --> Ton=1uS
safety
(a) For safty
5V
Vo=5V
Vin=100V
10:1
1000V
5V 100V --> 10V --> Duty 50% --> 5V

50kHz -> Ton=10uS
(b) For voltage change

(c) For potential fluctuation
Figure 19. Why a transformer is needed
5.2 The Ideal Transformer conditions:

The transformer is a device that uses inductive coupling 1.The coupling coefficient between the windings is unity
between its windings to deliver power or signals from one (i.e., the leakage flux is zero).
winding to the another. This is usually from the primary
winding to the secondary winding. The voltages across the 2.The coil loss is zero (the device has no losses).
windings can be raised or lowered with respect to each other 3.The inductance of each coil is infinite.
and, if necessary, the primary and secondary sides can be
isolated from each other. Figure 20 shows an ideal
transformer, a simplistic model useful in describing the
transformer concept. An ideal transformer which is actually
a fictional concept that must satisfy the following three
IP IS
+ Ideal Transformer
+
IP IP *
VP VS IS
+ +
_ _
VP Lm VS
NP : NS
_ _
VP : VS = NP : NS
NP : NS
IP : IS = NP : NS
VP : VS = NP : NS
Figure 20. Ideal transformer IP* : IS = NP : NS
The input-to-output voltage ratio of an ideal transformer is

directly proportional to the turns ratio. This is the ratio of the Figure 21. A model of an actual transformer showing the
number of turns on the primary winding to the number of magnetizing inductance Lm, which accounts for energy storage
turns on the secondary. The polarity is represented schemati-
cally by the placement of a dot on each winding. Since n=
Vp/Vs, and an ideal transformer has no loss, the current ratio
is inversely proportional to the turns ratio. The current direc-
tion is such that it enters on one side and leaves on another.
Thus the sum of all the nI that flow into the dot is zero. The
dot, indicating the winding polarity, is placed to make the Llp Lls
Rp Ideal Transformer Rs
flux direction in the transformer core uniform when current
flows into the dot. Furthermore, in the case of an ideal trans-
former, if the path on the secondary side windings is opened, Rm Lm
there is no secondary current flow and the current on the pri-
mary side also goes to zero.
-. Rp: Primary side winding resistance
5.3 The Real Transformer -. Rs: Secondary side winding resistance
-. Llp: Primary side leakage inductance
Significant differences exist between an ideal transformer
-. Lls: Secondary side leakage inductance
and a real one. In a real transformer: -. Lm: Magnetizing inductance
1. The coupling coefficient between each coil is finite and, -. Rm: Transformer core loss resistance
when a gap is placed in the core as is done in many power
transformers, the coupling coefficient becomes still small- Figure 22. A more complete equivalent circuit of an actual
er (i.e., there is leakage flux); transformer, showing inductances and loss resistances
2. There are losses, such as iron (hysteresis) loss, eddy current
loss, coil resistance loss, etc.; and,
3. The inductance of each coil is finite. When a gap is placed
in the core, the inductance becomes still smaller.
In a real transformer, should the secondary side be opened
current continues to flow in the primary. While energy
cannot be stored in the ideal transformer, it is stored in a real
transformer. The so-called magnetizing inductance accounts
for this energy storage phenomenon. The circuit of Figure 21
is a simplistic view of an actual transformer and shows the
magnetizing inductance. Figure 22 presents a more complete
equivalent circuit of a real transformer, showing inductances
and loss resistances.
REV. 1.0.4 • 5/19/06 18

6. Transformer Design
6.1 Core Selection
⎛ LΔI I 4 1.58
10 ⎞ 0.66
The maximum power that a transformer core can deliver and AP = ⎜ ------------------------------------------⎟
m RMS
(K f + K ( f )2 )
2
[ cm ] (15)
the maximum energy a transformer inductor can store ⎜ 130K ⎟ H SW E sw
⎝ ⎠
depends on the shape and size of the core. In general, as the
effective cross sectional area (Ae) increases, more power can L = Inductance of Transformer
be delivered. Also, as the window area (Aw) on which the Ip = Operating peak current
coils are wound increases, more and thicker windings can be Irms = RMS current
used, allowing a further increase in the power that can be
delivered. The product of Aw and Ae is called the area prod-
uct, AP, and the maximum power a transformer can deliver is In equation (15), KH is the hysteresis coefficient (typically 4 x
proportional to an exponential power of AP. Recent trans- 10-5 for ferrite cores) and KE is the eddy current coefficient
former theory shows designs depending almost entirely on (typically 4 x 10-10 for ferrite cores).
AP. In the broader view, a flyback converter transformer can The current density relationship, represented by the equation
be viewed as a coupled inductor, so it's common to design a for J30 assumes a hot spot temperature of 15°C above ambient,
flyback transformer using inductor design methods. The two with the iron loss adding on an additional 15°C (a total of
equations below, (13) and (15), represent two ways to calcu- 30°C above ambient).
late AP. Equation (13) based on whether or not the core is – 0.24 2
saturated, is appropriate at low operating frequencies. Equa- J 30 = 297AP [ A ⁄ cm ] (16)
tion (15), limited by core loss, is appropriate at high frequen-
cies. For any given design, it is necessary to calculate AP The parameter K in equation (13) is the product of the win-
using both equations. The equation that gives the higher dow utilization factor KU with the primary area factor KP
value is the one that must be considered correct. Equation (see Table 1). KU is the ratio of the cross sectional area of the
(13) assumes that all losses are wire losses and ignores the winding’s copper to the entire window area, and it is signifi-
core (iron) loss. cant in setting the isolation between the primary and second-
ary sides. Because it is related to the transformer shape and
4 1.31
⎛ LI P I RMS 10 ⎞ 2 winding method, the designer should know the value of KU
AP = ⎜ ---------------------------------⎟ [ cm ] (13)
⎝ 420KB MAX ⎠ for the transformer usually used.
L = Inductance of Transformer
The value of KU can vary greatly, depending particularly on
Ip = Operating peak current how closely the isolation safety standards (re isolation) are
Bmax = Maximum operating flux density followed; the KU of Table 1 assumes a general bobbin is
Irms = RMS current used. KP is the ratio of the area of the primary winding to
that of the total winding. In Table 1, it is unity for the induc-
L and BMAX are in Henries and Tesla units, respectively, and tors because a buck boost inductor has no secondary wind-
K is listed in Table 1, below. From the above equation, the ings. For the flyback transformer coupled inductor, KP is
current density (J) per unit area of wire is obtained from the usually 0.5, as Table 1 shows. Such an inductor has the high-
current by the relationship below, which assumes that the est efficiency when the primary and secondary winding areas
temperature of the inductor’s “hot spot” is 30°C above are equal. When there are more secondary windings, how-
ambient. ever, the KP for a flyback transformer coupled inductor can
be lower more than 0.5. Note that the ease and speed of
– 0.24 2
J 30 = 420 AP [ A ⁄ cm ] (14) obtaining an accurate AP from equations (13) and (15)
depends on the designer's experience. A reasonably good
At any operating frequency high enough for the core losses knowledge of the probable values of the three parameters
to become large, the following equation (15) should be used. KU, KP, and J for the flyback transformer being designed
Specifically, it assumes that the total transformer losses are reduces the number of trial and error attempts necessary.
split equally (50/50) between the wire and the core.
Table 1. KU, KP, and K
KU KP K = K U KP
CCM Buck, Boost Inductor 0.7 1.0 0.7
DCM Buck, Boost Inductor 0.7 1.0 0.7
CCM Flyback Transformer 0.4 0.5 0.2
DCM Flyback Transformer 0.4 0.5 0.2
6.2 Determining the Number of Turns 6.4 Determining the Gap

Although the equation for the minimum number of flyback It is not easy to precisely calculate the required gap; how-
transformer turns can be determined using applied voltage ever, the gap can be calculated from the following equation.
and maximum turn-on time, the equations used here are It is based on the fringing effect of the surrounding flux.
derived from the relationship between L and IP. Note that the calculated value of L is usually larger than
For an AP determined from equation (13), above, calculate required;
NMIN using the following equation: 2
u O u r N A C –2
LI P 4 - 10 [ cm ]
I g = ---------------------------- (19)
N MIN = ------------------------
- 10 (17) L
B MAX A C
UO = Permeability of free space
Ur = Relative permeability
L = Inductance of Transformer
Ip = Operating peak current
BMAX = Maximum operating flux density
Ae = Effective cross-sectional area of core therefore, the gap must be changed to obtain the required
value of L.
For an AP determined from equation (15), above, calculate
NMIN using the following equations: References
L Δ Im 4
N MIN = --------------------
- 10 (18) 1. Transformer and Inductor Design Handbook. 2nd ed.
Δ Bm AC Col. Wm. T. McLyman. Marcel Dekker, Inc., 1988.
L = Inductance of Transformer 2. Switch Mode Power Supply Handbook. Keith H.
Ip = Operating peak current Billings. McGraw-Hill, Inc., 1989.
BMAX = Maximum operating flux density
Ae = Effective cross-sectional area of core
KA1H0280RB, KA1M0280RB, KA1H0380RB, KA1M0380RB,
KA1L0380RB, KA1L0380B, KA1H0680B, KA1M0680B,
6.3 The Windings KA1H0680RFB, KA1M0680RB, KA1M0880B, KA1L0880B,
The cross-sectional area of the winding must be obtained KA1M0880BF, KA1M0880D, KA2S0680B, KA2S0880B,
KA3S0680RB, KA3S0680RFB, KA3S0880RB, KA3S0880RFB,
from the calculated effective current and the current density KA1H0165RN, KA1H0165R, KA1H0265R, KA1M0265R,
(from the appropriate equation above), factoring in the num- KA1H0365R, KA1M0365R, KA1L0365R, KA1H0565R,
ber of turns (as determined from a calculation of NMIN). If KA1M0565R, KA1M0765RC, KA1M0765R, KA1M0965R,
KA2S0765, KA2S0965, KA2S09655, KA2S1265, KA3S0765R,
eddy current loss is not a serious problem, divide the effec- KA3S0765RF, KA3S0965R, KA3S0965RF, KA3S1265R,
tive current by the current density, thereby determining the KA3S1265RF, KA5H0280R, KA5M0280R, KA5H0380R,
coil cross-sectional area. Be aware, however, that as the coil KA5M0380R, KA5L0380R, KA5P0680C, KA5H0165R,
KA5M0165R, KA5L0165R, KA5H0165RV, KA5M0165RV,
becomes thicker, the problem of eddy current loss arises. KA5L0165RV, KA5M0165RI, KA5L0165RI, KA5H0165RN,
Using twisted thin coil strands (Litz wire), instead of a single KA5M0165RN, KA5L0165RN, KA5H0165RVN,
heavy wire, can reduce the eddy current loss, but KU KA5M0165RVN, KA5L0165RVN, KA5H02659RN,
KA5M02659RN, KA5H0265RC, KA5M0265R, KA5L0265R,
becomes smaller. KA5M0365RN, KA5L0365RN, KA5H0365R, KA5M0365R,
KA5L0365R, KA5M0765RQC, KA5M0965Q, KA5S0765C,
KA5S09654QT, KA5S0965, KA5S12656, KA5S1265,
KA5Q0740RT, KA5Q0945RT, KA5Q0765RT, KA5Q12656RT,
KA5Q1265RF, KA5Q1565RF, FSDH0165, FSDH565,
REV. 1.0.4 • 5/19/06 20

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
© 2006 Fairchild Semiconductor Corporation • www.fairchildsemi.com REV. 1.0.4 5/19/06

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Application Note, V1.

Power Management & Supply

Revision History: 2009-10 V1.0

We Listen to Your Comments

Power Stage − Boost Type PFC Converter

PWM control of Boost Converter

Enhanced Dynamic Response

b. Output over-voltage protection

c. Soft over current control (SOC) and peak current limit

d. IC supply under voltage lock out

Designator Part Type Description Manufacturer / Part No.

11.1 Load test (table and figure):

85VAC, 9% of full load (28W output)

265VAC, full load (300W output)

11.3 Waveforms (soft start, load jump, open loop)

Soft start, test at 85VAC, Iout=0.2A

Design Guide for Boost Type CCM PFC with

Power Management & Supply

Design Guide for Boost Type CCM PFC with ICE2PCSxx

We Listen to Your Comments

Table of Contents Page

Application Note 4 2008-08-01

The Pin layout of ICE2PCS01 and ICE2PCS02 is shown in Figure 1.

GND 1 8 GATE GND 1 8 GATE

ICOMP 2 7 VCC ICOMP 2 7 VCC

ISENSE 3 6 VSENSE ISENSE 3 6 VSENSE

FREQ 4 5 VCOMP VINS 4 5 VCOMP

Figure 1 Pin Layout of ICE2PCS01 and ICE2PCS02

Application Note 5 2008-08-01

ISENSE GATE GND VSENSE

Auxiliary Supply VCC ICE2PCS01

ICOMP FREQ VCOMP

Figure 2 Typical application circuit of ICE2PCS01

R5 ICE2PCS02 VCC Auxiliary Supply

VINS ICOMP VCOMP

Figure 3 Typical application circuit of ICE2PCS02

Application Note 6 2008-08-01

2.1 Target specification

Input voltage 85VAC~265VAC

Table 1 Design parameter for the proposed design

2.2 Bridge rectifier

2.3 Power MOSFET and Gate Drive Circuit

For 300W design, if SPP20N60C3 is used, the conduction loss is

the total loss is

the required heatsink for the MOSFET is

2.4 Boost Diode

Pdiode = VF ⋅ I in _ RMS ⋅ (1 − Don ) = 2V ⋅ 3.92 A ⋅ (1 − 0.782) = 1.71W (10)

The required heatsink for boost diode is

TJ max − T A max 125 − 70

Application Note 8 2008-08-01

Figure 4 inrush current bypass diode

2.5 Boost inductor

For example, we choose k = 22%, then,

(1) sendust powder toroid core

Figure 5 Percent Permeability and DC Magnetizing Force H (from Changsung)

Application Note 10 2008-08-01

The copper loss of the winding wire can be calculated on Iin_RMS.

(2) ferrite core

2.6 AC line current filter

IHF_spec Current Filter IHF

The required Lfilter is

2.7 Boost Output Bulk Capacitance

(1) output double line frequency ripple limit.