LTC1704/LTC1704B

550kHz Synchronous
Switching Regulator Controller
Plus Linear Regulator Controller
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FEATURES DESCRIPTIO
■ Dual Regulated Outputs: One Switching Regulator The LTC®1704/LTC1704B include a high power synchro-
and One Linear Regulator nous switching regulator controller plus a linear regulator
■ Excellent DC Accuracy: ±1.5% for Switcher controller. The switching regulator controller is designed
and ±2% for Linear Regulator to drive a pair of N-channel MOSFETs in a voltage mode,
■ External N-Channel MOSFET Architecture synchronous buck configuration to provide the main sup-
■ No External Current Sense Resistor Required ply. The constant frequency, true PWM architecture
■ Burst Mode® Operation at Light Load (LTC1704) switches at 550kHz, minimizing external component size,
■ Continuous Switching at Light Load (LTC1704B) cost and optimizing load transient performance. The
■ Linear Regulator with Programmable Current Limit LTC1704 features automatic transition to power saving
■ Linear Regulator with Programmable Start-Up Delay Burst Mode operation at light loads. The LTC1704B does
■ Low Shutdown Current: <150µA not shift into Burst Mode operation at light loads, eliminat-
■ High Efficiency Over Wide Load Current Range ing low frequency output ripple at the expense of light load
■ PGOOD Flag Monitors Both Outputs efficiency. The linear regulator controller is designed to
■ Small 16-Pin Narrow SSOP Package drive an external NPN power transistor to provide up to 2A
U of current to an auxiliary load.
APPLICATIO S The LTC1704/LTC1704B deliver better than ±1.5% DC
■ Multiple Logic Supply Generator accuracy at the switcher outputs and ±2% at the linear
■ Distributed Power Applications regulator outputs. High performance feedback loops allow
■ High Efficiency Power Conversion the circuit to keep total output regulation within ±5%
under all transient conditions. An open-drain PGOOD
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation. output indicates when both outputs are within ±10% of
their regulated values.

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TYPICAL APPLICATIO
5V to 1.8V/15A and 1.5V/2A Application
10Ω
VIN
5V
CIN + MBR0520LT1 + Switcher Efficiency
330µF 1µF
+ 5k 470k 10µF
10V 10µF
×3
16 15 11 100
CCP
1µF BOOST PVCC VCC
L1 QTA QTB 1 12
TG PGOOD 90
0.68µH
2 10
SW REGILM
EFFICIENCY (%)

COUTSW 1000pF
VOUTSW
180µF
+ 14 4 80
1.8V QBB QBA BG RUN/SS
15A 4V 0.1µF
×6 13.7k 3
LTC1704
8 70
IMAX GND
VOUTSW
13 7 VIN = 5V
10k 1.8k ON SEMI 60
1800pF PGND REGDR VOUTSW = 1.8V
D44H11 TA = 25°C
6
FB QT = QB = 2xFDS6670A
1800pF 330pF 698Ω 50
8.06k 11k 5 9 + 100µF
VOUTREG 0 3 6 9 12 15
COMP REGFB 1.5V ILOAD (A)
TANT
806Ω 2A
CIN: KEMET T510X337K010AS 1704 G04

COUTSW: PANASONIC EEFUE0G181R

1704 TA01
L: SUMIDA CEP125-4712-T007
QTA, QTB, QBA, QBB: FAIRCHILD FDS6670A
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LTC1704/LTC1704B
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ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage ORDER PART
TOP VIEW
VCC, PVCC .............................................................. 6V NUMBER
TG 1 16 BOOST
BOOST ................................................................. 12V
BOOST – SW ......................................................... 6V
SW 2 15 PVCC LTC1704EGN
Input Voltage
IMAX 3 14 BG LTC1704BEGN
RUN/SS 4 13 PGND
SW ............................................................. –1V to 6V COMP 5 12 PGOOD
FB, REGFB, REGILM, FB 6 11 VCC
RUN/SS, IMAX .......................... – 0.3V to (VCC + 0.3V) REGDR 7 10 REGILM GN PART MARKING
Peak Output Current <10µs GND 8 9 REGFB
1704
TG, BG (Note 7) ..................................................... 5A GN PACKAGE 1704B
Operating Temperature Range (Note 2) .. – 40°C to 85°C 16-LEAD PLASTIC SSOP

Storage Temperature Range ................. – 65°C to 150°C TJMAX = 125°C, θJA = 130°C/W

Lead Temperature (Soldering, 10 sec).................. 300°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = PVCC = BOOST = 5V, unless otherwise specified. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC VCC Supply Voltage ● 3.15 5 5.5 V
PVCC PVCC Supply Voltage (Note 4) ● 3.15 5 5.5 V
BVCC BOOST Pin Voltage VBOOST – VSW (Note 4) ● 3.15 5 5.5 V
IVCC VCC Supply Current Test Circuit ● 4.5 8 mA
VRUN/SS = 0V, VREGILM = 0V ● 75 150 µA
IPVCC PVCC Supply Current Test Circuit, No Load at Drivers ● 3 6 mA
VRUN/SS = 0V (Notes 5, 6) ● 50 µA
IBOOST BOOST Pin Current Test Circuit ● 2 6 mA
VRUN/SS = 0V (Notes 5, 6) ● 50 µA
VSHDN RUN/SS Shutdown Threshold VRUN/SS ↑ ● 0.2 0.5 V
ISS RUN/SS Source Current VRUN/SS = 0V –3 µA
Switcher Control Loop
VFB Feedback Voltage ● 0.788 0.800 0.812 V
IFB Feedback Input Current ● ±1 µA
dVFB Feedback Voltage Line Regulation VCC = 3.3V to 5.5V ● ±0.01 ±0.1 %/V
Output Voltage Load Regulation (Note 7) ● – 0.2 – 0.1 %
AFB Feedback Amplifier DC Gain ● 74 85 dB
GBW Feedback Amplifier Gain Bandwidth Product f = 100kHz (Note 7) 20 MHz
ICOMP Feedback Amplifier Output Sink/Source Current ● ±3 ±10 mA
VPGOOD Negative Power Good Threshold ● –15 –10 –6 %
Positive Power Good Threshold ● 6 10 15 %
IIMAX IMAX Source Current VIMAX = 0V ● –11.5 –10 – 8.5 µA

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 LTC1704/LTC1704B
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = PVCC = BOOST = 5V, unless otherwise specified. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Switcher Switching Characteristics
fOSC Oscillator Frequency Test Circuit ● 460 550 650 kHz
DCMAX Maximum Duty Cycle ● 87 90 93 %
tNOV Driver Nonoverlap Test Circuit (Note 8) ● 10 25 120 ns
tr, tf Driver Rise/Fall Time Test Circuit (Note 8) ● 15 100 ns
Linear Regulator Controller
VREGFB Feedback Voltage Test Circuit, RREGILM = 680k 0.784 0.800 0.816 V
● 0.780 0.800 0.820 V
IREGFB REGFB Input Current ● ±1 µA
dVREGFB Feedback Voltage Line Regulation Test Circuit, VCC = 4.5V to 5.5V ● ±0.05 ±0.2 %/V
Feedback Voltage Load Regulation Test Circuit, IREGDR = 0mA to 30mA ● –0.2 –0.05 %
IREGDR Driver Output Current Test Circuit ● 30 mA
RREGILM = 680k, VREGFB = 0.76V, VREGDR = 3.3V 20 mA
RREGILM = 680k, VREGFB = 0V, VREGDR = 1V 6 mA
VDROPOUT Driver Dropout Voltage Test Circuit, IREGDR = 30mA, VREGDR = 3.3V, ● 0.65 1.1 V
dVREGFB = –1% (Note 9)
VREGILM REGILM Threshold Test Circuit, RREGILM = 680k 0.8 V
IREGILMINT REGILM Internal Pull-Up Current VREGILM = 0V –1.9 µA
VPGOOD Negative REGFB Power Good Threshold ● –15 –10 –6 %
Positive REGFB Power Good Threshold ● 6 10 15 %
PGOOD
IPGOOD VPGOOD Sink Current Power Good ● 10 µA
Power Bad ● 10 mA
VOLPG VPGOOD Output Low Voltage IPGOOD = 1mA ● 0.03 0.1 V
tPGOOD VPGOOD Falling Edge Delay (Note 8) ● 0.5 1 4 µs
VPGOOD Rising Edge Delay (Note 8) ● 10 20 40 µs

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC1704E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: PVCC and BVCC (VBOOST – VSW) must be greater than VGS(ON) of
the external MOSFETs to ensure proper operation.
Note 5: Supply current in normal operation is dominated by the current
needed to charge and discharge the external MOSFET gates. This current
will vary with supply voltage and the external MOSFETs used.
Note 6: Supply current in shutdown is dominated by external MOSFET
leakage and may be significantly higher than the quiescent current drawn
by the LTC1704, especially at elevated temperature.
Note 7: Guaranteed by design, not subject to test.
Note 8: Rise and fall times are measured using 10% and 90% levels. Delay
and nonoverlap times are measured using 50% levels.
Note 9: Dropout voltage is the minimum VCC to VREGDR voltage differential
required to maintain regulation at the specified driver output current.

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TYPICAL PERFOR A CE CHARACTERISTICS
VFB vs Temperature VFB Line Regulation
0.812 0.80 0.10
VCC = 5V TA = 25°C
0.64 0.08
0.808
0.48 0.06
0.32 0.04
0.804
0.16 0.02

∆VFB (mV)

∆VFB (%)
VFB (V)

0.800 0 0
–0.16 –0.02
0.796
–0.32 –0.04
–0.48 –0.06
0.792
–0.64 –0.08
0.788 –0.80 –0.10
–50 –25 0 25 50 75 100 125 3 3.5 4 4.5 5 5.5 6
TEMPERATURE (°C) VCC (V)
1704 G01 1704 G02

Switcher Current Limit Threshold

VOUTSW Load Regulation vs Temperature
0.6 0.03 24
TA = 25°C VIN = 5V
VOUTSW = 1.8V VOUTSW = 1.8V
0 0 22
∆VOUTSW = –1%
CURRENT LIMIT THRESHOLD (A)

RIMAX = 13.7k
–0.6 – 0.03 20 QT = QB = 2xFDS6670A
∆VOUTSW (mV)

∆VOUTSW (%)

–1.2 –0.07 18

–1.8 –0.10 16

–2.4 –0.13 14

–3.0 –0.17 12

–3.6 –0.20 10
0 3 6 9 12 15 –50 –25 0 25 50 75 100 125
ILOAD (A) TEMPERATURE (°C)
1704 G03 1704 G08

VOUTSW 0.5A to 5.5A Load Step VOUTSW Burst Mode Operation

(Burst Mode Operation) VOUTSW 5A to 10A Load Step at 1A Load

100µs/DIV 1704 G05 50µs/DIV 1704 G06 20µs/DIV 1704 G07

CH1: VOUTSW = 1.8V, AC 50mV/DIV CH1: VOUTSW = 1.8V, AC 50mV/DIV CH1: VOUTSW = 1.8V, AC 20mV/DIV
CH2: 0.5A to 5.5A LOAD, 5A DIV CH2: 5A to 10A LOAD, 5A DIV CH2: VTG, 5V DIV

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TYPICAL PERFOR A CE CHARACTERISTICS
VOUTSW vs Load Current IIMAX vs Temperature IIMAX vs VCC
2.0 –8.5 –8.5
VCC = 5V TA = 25°C

–9.0 –9.0
1.5
–9.5 –9.5
VOUTSW (V)

IIMAX (µA)
IIMAX (µA)
1.0 –10.0 –10.0

–10.5 –10.5
VIN = 5V
0.5 VOUTSW = 1.8V
TA = 25°C –11.0 –11.0
RIMAX = 13.7k
QT = QB = 2xFDS6670A
0 –11.5 –11.5
0 4 8 12 16 20 –50 –25 0 25 50 75 100 125 3 3.5 4 4.5 5 5.5 6
LOAD CURRENT (A) TEMPERATURE (°C) VCC (V)
1704 G09 1704 G10 1704 G11

Maximum TG Duty Cycle

fOSC vs Temperature fOSC vs VCC vs Temperature
640 650 93
VCC = 5V TA = 25°C VCC = 5V
620 TG, BG FLOAT
92
600 610

580 91

DCMAX (%)
fOSC (kHz)

570
fOSC (kHz)

560
90
540
530
520 89
500
490 88
480

460 450 87
–50 –25 0 25 50 75 100 125 3 3.5 4 4.5 5 5.5 6 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) VCC (V) TEMPERATURE (°C)
1704 G12 1704 G13 1704 G10

Drivers Rise and Fall Time

vs Load VREGFB vs Temperature VREGFB Line Regulation
100 0.820 1.6 0.20
TA = 25°C VREGDR = 3.3V TA = 25°C
90 PVCC = BOOST = 5V 0.815 1.2 VREGDR = 0.8V 0.15
80
0.810 0.8 0.10
70
∆VREGFB (mV)

0.4 0.05
∆VREGFB (%)

60 0.805
VREGFB (V)
tr, tf (ns)

50 0.800 0 0
40 0.795 –0.4 –0.05
30
0.790 –0.8 –0.10
20
0.785 –1.2 –0.15
10
0 0.780 –1.6 –0.20
0 2000 4000 6000 8000 10000 – 50 – 25 0 25 50 75 100 125 3 3.5 4 4.5 5 5.5 6
TG, BG LOAD (pF) TEMPERATURE (°C) VCC (V)
1704 G15 LTXXX • TPCXX 1704 G17

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TYPICAL PERFOR A CE CHARACTERISTICS
Linear Regulator Dropout Voltage
VOUTREG Load Regulation vs Temperature VOUTREG 0.1A to 2.1A Load Step
0.5 0.03 1.1
IREGDR = –30mA
0 1.0 VREGDR = 3.3V
0
VOUT
0.9
–0.5 – 0.03
∆VOUTREG (mV)

∆VOUTREG (%)

VDROPOUT (V)
0.8
–1.0 –0.07
0.7
ILOAD
–1.5 –0.10
0.6
–2.0 –0.13
TA = 25°C 0.5
–2.5 VOUTREG = 1.5V –0.17 0.4 50µs/DIV 1704 G20
IREGILM = 9µA
QEXT = D44H11 CH1: VOUTREG = 1.5V, AC 50mV/DIV
–3.0 –0.20 0.3 CH2: 0.1A to 2.1A LOAD, 1A DIV
0 0.4 0.8 1.2 1.6 2 – 50 – 25 0 25 50 75 100 125
IOUTREG (A) TEMPERATURE (°C)
1704 G18 1704 G19

Linear Regulator Start-Up Time

Minimum VCC vs VOUTREG vs CDELAY IREGDR vs IREGILM
5.5 1100 35
IREGILM = 9µA TA = 25°C
IOUTREG = 2A 1000 VOUTREG = 1.5V
∆VOUTREG = –1% 900 30
5.0 QEXT = D44H11
800 25
START-UP TIME (µs)
MINIMUM VCC (V)

700
4.5 IREGILM = 6.2µA IREGDR (mA)
600 20
500
IREGILM = 9µA 15
4.0 400
TA = –40°C
300 10
3.5 200
TA = 25°C 5
100
3.0 0 0
0.9 1.3 1.7 2.1 2.5 2.9 3.3 0 2000 4000 6000 8000 10000 0 2 4 6 8 10 12
VOUTREG (V) CDELAY (pF) IREGILM (µA)
1704 G21 1704 G22 1704 G23

Linear Regulator Current Limit

IREGDR vs VREGFB Threshold vs Temperature VOUTREG vs Load Current
30 3.0 2.0
TA = 25°C
VREGDR = 0V
CURRENT LIMIT THRESHOLD (A)

25
2.5 1.5
20
IREGDR (mA)

VOUTREG (V)

IREGILM = 9µA
15 2.0 1.0

10
IREGILM = 6.2µA TA = 25°C
1.5 VINREG = 1.8V 0.5 VINREG = 1.8V
5 VOUTREG = 1.5V VOUTREG = 1.5V
IREGILM = 9µA IREGILM = 9µA
QEXT = D44H11 QEXT = D44H11
0 1.0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 –50 –25 0 25 50 75 100 125 0 0.5 1 1.5 2 2.5 3
VREGFB (V) TEMPERATURE (°C) IOUTREG (A)
1704 G28 1704 G24 1704 G25

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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Temperature IPVCC, IBOOST vs Driver Load
6.0 35
VCC = PVCC = BOOST = 5V TA = 25°C
TG, BG FLOAT PVCC = BOOST = 5V
30
IVCC
4.5
SUPPLY CURRENT (mA)

25

IPVCC, IBOOST (mA)

IPVCC 20
3.0
IBOOST 15

1.5 10

0 0
–50 –25 0 25 50 75 100 125 0 2000 4000 6000 8000 10000
TEMPERATURE (°C) TG, BG LOAD (pF)
1704 G26 1704 G27

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PI FU CTIO S
TG (Pin 1): Switcher Controller Top Gate Drive. The TG pin
drives the gate of the top N-channel MOSFET, QT. The TG
driver draws power from the BOOST pin and returns it to
the SW pin, providing true floating drive to QT. TG is de-
signed to typically drive up to 10,000pF of gate capacitance.
SW (Pin 2): Switcher Controller Switching Node. Connect
SW to the switching node of the main converter. The TG
driver ground returns to SW, providing floating gate drive
to the top N-channel MOSFET, QT. The voltage at SW is
compared to IMAX by the current limit comparator while
the bottom MOSFET, QB is on. The Burst comparator
(BURST, see Block Diagram) monitors the potential at SW
and switches to Burst Mode operation under light load
conditions.
IMAX (Pin 3): Switcher Controller Current Limit Set. The
IMAX pin sets the current limit comparator threshold for
the switcher controller. If the voltage drop across the
bottom MOSFET, QB, exceeds the magnitude of the volt-
age at IMAX, the switcher controller enters current limit.
The IMAX pin has an internal 10µA current source pull-up,
allowing the current threshold to be set with a single
external resistor to PGND. Kelvin connect this current
setting resistor to the source of QB. Refer to the Current
Limit Programming section for more information on choos-
ing RIMAX.
RUN/SS (Pin 4): Switcher Controller Soft-Start. A capaci-
tor from RUN/SS to GND controls the turn-on time and
rate of rise of the switcher output voltage at power up. An
internal 3µA current source pull-up at RUN/SS sets the
turn-on time at approximately 300ms/µF. If both RUN/SS
and REGILM are pulled low, the LTC1704 enters shutdown
mode.
COMP (Pin 5): Switcher Controller Loop Compensation.
The COMP pin is connected directly to the output of the
switcher controller’s error amplifier and the input to the
PWM comparator. Use an RC network between the COMP
pin and the FB pin to compensate the feedback loop for
optimum transient response.
FB (Pin 6): Switcher Controller Feedback Input. FB should
be connected through a resistor divider network to VOUTSW
to set the switcher output voltage. Also, connect the
switcher loop compensation network to FB.
REGDR (Pin 7): Linear Regulator Controller Driver Output.
Connect REGDR to the base of the external NPN Pass
transistor. The REGILM pin input current controls the
linear regulator controller maximum driving capability.
GND (Pin 8): Signal Ground. All internal low power cir-
cuitry returns to the GND pin. Connect to a low impedance
ground, separated from the PGND node. All feedback,

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LTC1704/LTC1704B
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PI FU CTIO S
compensation and soft-start connections should return to
GND. GND and PGND should connect only at a single
point, near the PGND pin and the negative plate of the VIN
bypass capacitor.
REGFB (Pin 9): Linear Regulator Controller Feedback
Input. REGFB should be connected through a resistor
divider network to VOUTREG to set the output voltage of the
linear regulator.
REGILM (Pin 10): Linear Regulator Controller Current
Limit Setting cum ON/OFF Control. This pin is internally
servoed to 0.8V. An external resistor RREGILM between VCC
and REGILM programs the REGILM pin input current. This
current determines the maximum pass transistor base
current and directly controls the linear regulator current
sourcing capabilitiy. An external capacitor, CDELAY is added
to this pin to control the turn-on time of the linear regula-
tor, the minimum value for this capacitor is 100pF. Refer
to the Linear Regulator Current Limit Programming sec-
tion for more information on choosing RREGILM and CDELAY.
Pulling REGILM to GND turns off the linear regulator. If
both RUN/SS and REGILM are pulled low, the LTC1704
enters shutdown mode.
VCC (Pin 11): Power Supply Input. All internal circuits
except the switcher output drivers are powered from this
pin. VCC should be connected to a low noise 5V supply, and
should be bypassed to GND with at least a 10µF capacitor
in close proximity to the LTC1704.
PGOOD (Pin 12): Power Good. PGOOD is an open-drain
logic output. PGOOD pulls low if any of the two supply
outputs are outside ±10% of their nominal levels. An
external pull-up resistor is required at PGOOD to allow it
to swing positive.
PGND (Pin 13): Power Ground. The BG driver returns to
this pin. Connect PGND to a high current ground node in
close proximity to the sources of external MOSFET QB,
and the VIN and VOUTSW bypass capacitors.
BG (Pin 14): Switcher Controller Bottom Gate Drive. The
BG pin drives the gate of the bottom N-channel synchro-
nous switch MOSFET, QB. BG is designed to typically drive
up to 10,000pF of gate capacitance.
PVCC (Pin 15): Switcher Controller Bottom Gate Driver Sup-
ply. PVCC provides power to the BG output driver. PVCC
must be connected to a voltage high enough to fully turn
on the external MOSFET, QB. PVCC should generally be con-
nected directly to VIN, the main system 5V supply. PVCC
requires at least a 10µF bypass capacitor directly to PGND.
BOOST (Pin 16): Switcher Controller Top Gate Driver
Supply. The BOOST pin supplies power to the floating TG
driver. Bypass BOOST to SW with a 1µF capacitor. An
external Schottky diode from VIN to BOOST creates a
complete floating charge-pumped supply at BOOST. No
other external supplies are required.

TEST CIRCUIT
5V
IBOOST IPVCC IVCC +
1 16 10µF
fOSC TG BOOST
2000pF 2 15
SW PVCC
3 14
IMAX LTC1704 BG RREGILM
4 13 2000pF 100k
RUN/SS PGND
2k 5 12
COMP PGOOD
6 11
VFB FB VCC
7 10
REGDR REGILM
8 9 80k
100Ω GND REGFB 100pF

1µF 1704 TC
250k

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 PVCC RUN/SS PGOOD VCC
15 4 12 11
10µA 3µA
BLOCK DIAGRA

IMAX 3
SSCMP
W

ILM
0.5V

BOOST 16 SHUTDOWN
SWITCHER DRIVER
TG 1
SW 2 BURST
AND POWER
DRIVER PWM VB = 2V TYP DOWN
PVCC LOGIC
VA = 1V TYP
BG 14 OSC
550kHz
BURST

MAX MIN
MPG
SOFT- PWRGD
0.840V 0.760V START DELAY
0.8V
COMP 5 PWRBAD PWRBAD MREG
SWITCHER REG NPGREG REGFB 7 REGDR
0.800V 0.720V 0.720V
FB NPG 2mA
REG
ILM
PPGREG
FB 6 9 REGFB
PPG
0.880V 0.880V
1.9µA
0.8V
BANDGAP 10 REGILM
REFERENCE
AMP MREGILM
13 8 0.8V
PGND GND
POWER-UP LINEAR REGULATOR
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LTC1704/LTC1704B
LTC1704/LTC1704B
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APPLICATIO S I FOR ATIO
OVERVIEW
The LTC1704 includes a step-down (buck), voltage mode
feedback switching regulator controller and a linear regu-
lator controller. The switching regulator controller em-
ploys a synchronous switching architecture with two
external N-channel MOSFETs. The chip operates from a
low voltage input supply (6V maximum) and provides high
power, high efficiency, precisely regulated output voltage.
The switcher output regulation is extremely tight, with
initial accuracy and DC line and load regulation and better
than 1.5%. Total regulation, including transient response,
is inside of 3.5% with a properly designed circuit. The
550kHz switching frequency allows the use of physically
small, low value external components without compro-
mising performance.
The LTC1704’s internal feedback amplifier is a 20MHz gain
bandwidth op amp, allowing the use of complex multipole/
zero compensation networks. This allows the feedback
loop to maintain acceptable phase margin at higher fre-
quencies than traditional switching regulator controllers,
improving stability and maximizing transient response.
The 800mV internal reference allows regulated output
voltages as low as 800mV without external level shifting
amplifiers. The LTC1704’s synchronous switching logic
transitions automatically into Burst Mode operation, maxi-
mizing efficiency with light loads.
The linear regulator controller drives an external NPN pass
transistor to provide a programmable output voltage up to
2A of current. An external pull-up resistor programs the
current limit threshold for the linear regulator. Under
short-circuit condition, the foldback current limit circuitry
prevents excessive pass transistor heating. The switcher
and the linear regulator can be individually disabled. When
both controllers are disabled, the LTC1704 enters shut-
down mode and the supply current reduces to 75µA. An
onboard power good (PGOOD) flag goes high when both
outputs are regulating.
Small Footprint
The LTC1704 switcher supply operates at a 550kHz switch-
ing frequency, allowing it to use low value inductors
without generating excessive ripple currents. Because the
inductor stores less energy per cycle, the physical size of
10
the inductor can be reduced without risking core satura-
tion, saving PCB board space. The high operating fre-
quency also means less energy is stored in the output
capacitors between cycles, minimizing their required value
and size. The remaining components, including the
LTC1704, are tiny, allowing an entire power convertor to
be constructed in 1.5in2 of PCB space.
Fast Transient Response
The LTC1704 switcher supply uses a fast 20MHz GBW op
amp as an error amplifier. This allows the compensation
network to be designed with several poles and zeros in a
more flexible configuration than with a typical gm feedback
amplifier. The high bandwidth of the amplifier, coupled
with the high switching frequency and the low values of the
external inductor and output capacitor, allow very high
loop crossover frequencies. The low inductor value is the
other half of the equation—with a typical value on the
order of 1µH, the inductor allows very fast di/dt slew rates.
The result is superior transient response compared with
conventional solutions.
High Efficiency
The LTC1704 switcher supply uses a synchronous step-
down (buck) architecture, with two external N-channel
MOSFETs. A floating topside driver and a simple external
charge pump provide full gate drive to the upper MOSFET.
The voltage mode feedback loop and MOSFET VDS current
limit sensing remove the need for an external current
sense resistor, eliminating an external component and a
source of power loss in the high current path. Properly
designed circuits using low gate charge MOSFETs are
capable of efficiencies exceeding 90% over a wide range
of output voltages.
Linear Regulator Controller
The LTC1704 linear regulator controller drives an exter-
nal NPN pass transistor in emitter-follower configuration
to provide an externally adjustable output voltage. The con-
troller senses the output voltage via the REGFB pin, drives
the base of the NPN through the REGDR pin to regulate
the REGFB pin to 0.8V. REGDR is capable of sourcing more
than 30mA of base current to the external NPN.
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Overcurrent protection is achieved by limiting the drive
current. The input current at the REGILM pin programs the
current limit threshold. Refer to the Linear Regulator
Supply Current Limit Programming section for more
information on choosing RREGILM. The linear regulator
controller employs a foldback current limit scheme for
overcurrent protection. Under a short-circuit condition,
the external NPN transistor is subjected to the full input
voltage across its collector-emitter terminal. This increases
the power dissipation of the NPN and may eventually
cause damage to the transistor. LTC1704 overcomes this
problem by using a foldback current limit scheme whereby
the available drive current is reduced as the output voltage
at REGFB pin drops. This limits the power dissipation and
prevents catastrophic damage to the external NPN.
ARCHITECTURE DETAILS
Switcher Supply Architecture
The LTC1704 switcher supply is designed to operate as a
synchronous buck converter (Figure 1). The controller
includes two high power MOSFET gate drivers to control
the external N-channel MOSFETs QT and QB. The drivers
have 0.5Ω output impedances and can carry over an amp
of continuous current with peak currents up to 5A to slew
large MOSFET gates quickly. The drain of QT is connected
to the input supply and the source of QT connected to the
switching node SW. QB is the synchronous rectifier with
its drain at SW and its source at PGND. SW is connected
to one end of the inductor, with the other end connected
to VOUTSW. The output capacitor is connected from VOUTSW
to PGND.
VIN
+ TG
CIN
TG QT
SW L VOUTSW
LTC1704 VOUTSW
BG QB + COUTSW
COUTSW
PGND
1704 F01
Figure 1. Synchronous Buck Architecture
LTC1704/LTC1704B
When a switching cycle begins, QB is turned off and QT is
turned on. SW rises almost immediately to VIN and the
inductor current begins to increase. When the PWM pulse
completes, QT turns off and one nonoverlap interval later,
QB turns on. Now SW drops to PGND and the inductor
current decreases. The cycle repeats with the next tick of
the master clock. The percentage of time spent in each
mode is controlled by the duty cycle of the PWM signal,
which in turn is controlled by the feedback amplifier. The
master clock runs at a 550kHz rate and turns QT once
every 1.8µs. In a typical application with a 5V input and a
1.5V output, the duty cycle will be set at 1.5/5 • 100% or
30% by the feedback loop. This will give roughly a 540ns
on-time for QT and a 1.26µs on-time for QB.
This constant frequency operation brings with it a couple
of benefits. Inductor and capacitor values can be chosen
with a precise operating frequency in mind and the feed-
back loop components can be similarly tightly specified.
Noise generated by the circuit will always be in a known
frequency band with the 550kHz frequency designed to
leave the 455kHz IF band free of interference. Subharmonic
oscillation and slope compensation, common headaches
with constant frequency current mode switchers, are
absent in voltage mode designs like the LTC1704. During
the time that QT is on, its source (the SW pin) is at VIN. VIN
is also the power supply for the LTC1704. However, QT
requires VIN + VGS(ON) at its gate to achieve minimum RON.
The LTC1704, needs to generate a gate drive signal at TG
higher than its highest supply voltage. To accomplish this,
the TG driver runs from floating supplies, with its negative
supply attached to SW and its power supply at BOOST.
This allows it to slew up and down with the source of QT.
VIN
DCP
+
LTC1704 PVCC CIN
BOOST
CCP
QT
SW
L
BG +
QB
PGND
1704 F02
Figure 2. Floating TG Driver Supply
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In combination with a simple external charge pump (Fig-
ure 2), this allows the LTC1704 to completely enhance the
gate of QT without requiring an additional, higher supply
voltage.
Switcher Supply Feedback Amplifier
The LTC1704 senses the switcher output voltage at VOUTSW
with an internal feedback op amp (see Block Diagram).
This is a real op amp with a low impedance output, 85dB
open-loop gain and 20MHz gain bandwidth product. The
positive input is connected internally to an 800mV refer-
ence, while the negative input is connected to the FB pin.
The output is connected to COMP, which is in turn con-
nected to the soft-start circuitry and from there to the
PWM generator. The switching regulator output voltage
can be obtained using the following equation:
 R1
VOUTSW = 0.8 V •  1 + 
 R2 
Unlike many regulators that use a resistor divider con-
nected to a high impedance feedback input, the LTC1704
switcher supply is designed to use an inverting summing
amplifier topology with the FB pin configured as a virtual
ground. This allows flexibility in choosing pole and zero
locations not available with simple gm configurations. In
particular, it allows the use of “Type 3” compensation,
which provides a phase boost at the LC pole frequency
and significantly improves loop phase margin (refer to
Figure␣ 3).
R3
+ 0.8V
COMP
FB
FB
– VOUTSW
LTC1704
C2
R4
C1
1704 F03
Figure 3. "Type 3" Feedback Loop
12
Switcher Supply MIN/MAX Comparators
Two additional feedback loops in the switcher supply keep
an eye on the primary feedback amplifier and step in if the
feedback node moves ±5% from its nominal 800mV value.
The MAX comparator (see Block Diagram) activates when-
ever FB rises more than 5% above 800mV. It immediately
turns the top MOSFET (QT) off and the bottom MOSFET
(QB) on and keeps them that way until FB falls back within
5% of its nominal value. This pulls the output down as fast
as possible, preventing damage to the (often expensive)
load. If FB rises because the output is shorted to a higher
supply, QB will stay on until the short goes away, the
higher supply current limits or QB dies trying to save the
load. This behavior provides maximum protection against
overvoltage faults at the output, while allowing the circuit
to resume normal operation when the fault is removed.
The MIN comparator (see Block Diagram) trips whenever
FB is more than 5% below 800mV and immediately forces
the switch duty cycle to 90% to bring the output voltage
back into range. It releases when FB is within the 5%
window. MIN is disabled when the soft-start or current
limit circuits are active—the only two times that the output
should legitimately be below its regulated value.
Notice that the FB pin is the virtual ground node of the
feedback amplifier. A typical compensation network does
not include local DC feedback around the amplifier, so that
the DC level at FB will be an accurate replica of the output
voltage, divided down by R1 and R2 (Figure 3). However,
the compensation capacitors will tend to attenuate AC
signals at FB, especially with low bandwidth Type 1 feed-
C3
back loops. This creates a situation where the MIN and
MAX comparators do not respond immediately to shifts in
R1
the output voltage, since they monitor the output at FB.
R2 PGOOD Flag
The LTC1704 comes with a power good pin (PGOOD).
PGOOD is an open-drain output, and requires an external
pull-up resistor. If both the regulators are within ±10%
from their nominal value, the transistor MPG shuts off (see
Block Diagram), and PGOOD is pulled high by the external
pull-up resistor. If any of the two outputs is more than 10%
outside the nominal value for more than 1µs, PGOOD pulls
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low, indicating that the output is out of regulation. For
PGOOD to go high, both the outputs must be in regulation
for more than 20µs. PGOOD remains active during soft-
start and current limit. Upon power-up, PGOOD is forced
low. As soon as the RUN/SS and REGILM pins rise above
the shutdown thresholds, the two pairs of power good
comparators take over and control the transistor MPG
directly. The 1µs and 20µs delay ensures that short output
transient glitches that are successfully “caught” by the
power good comparators don’t cause momentary glitches
at the PGOOD pin.
Shutdown/Soft-Start
The RUN/SS pin performs two functions: when pulled to
ground, it shuts down the switcher drivers, and acts as a
conventional soft-start pin, enforcing a maximum duty
cycle limit proportional to the voltage at RUN/SS. An
internal 3µA current source pull-up is connected to the
RUN/SS pin, allowing a soft-start ramp to be generated
with a single external capacitor to ground. The 3µA current
source is active even when the LTC1704 is shut down,
ensuring the device will start when any external pull-down
at RUN/SS is released.
The RUN/SS pin shuts down the switcher drivers when it
falls below 0.5V (Figure 4). Between 0.5V and about 1V,
the LTC1704 wakes up and the duty cycle is kept to
minimum. As the potential at RUN/SS goes higher, the
duty cycle increases linearly between 1V and 2V, reaching
its final value of 90% when RUN/SS is above 2V. Some-
where before this point, the feedback amplifier will as-
sume control of the loop and the output will come into
regulation. When RUN/SS rises to 1V below VCC , the MIN
feedback comparator is enabled, and the LTC1704 voltage
feedback loop is in full operation.
LTC1704/LTC1704B
flowing in it. In a buck converter, the average current in the
inductor is equal to the output current. This current also
flows through QB during its on-time. Thus, by watching
the voltage across QB, the LTC1704 can monitor the
output current.
Any time QB is on and the current flowing to the output is
reasonably large, the SW node at the drain of QB will be
somewhat negative with respect to PGND. The LTC1704
senses this voltage and inverts it to allow it to compare the
sensed voltage with a positive voltage at the IMAX pin. The
IMAX pin includes a trimmed 10µA pull-up, enabling the
user to set the voltage at IMAX with a single resistor, RIMAX,
to ground. The LTC1704 compares the two inputs and
begins limiting the output current when the magnitude of
the negative voltage at the SW pin is greater than the
voltage at IMAX.
The current limit detector is connected to an internal gm
amplifier that pulls a current from the RUN/SS pin propor-
tional to the difference in voltage magnitudes between the
SW and IMAX pins. This current begins to discharge the
soft-start capacitor at RUN/SS, reducing the duty cycle
and controlling the output voltage until the current drops
below the limit. The soft-start capacitor needs to move a
fair amount before it has any effect on the duty cycle,
adding a delay until the current limit takes effect (Figure 4).
This allows the LTC1704 to experience brief overload
conditions without affecting the output voltage regulation.
VOUT
CURRENT
LIMIT
0V NORMAL
START-UP
OPERATION
5V

4V
COMP CONTROLS MIN HARD
Switcher Supply Current Limit DUTY CYCLE COMPARATOR CURRENT
ENABLE LIMIT
The LTC1704 switcher supply includes an onboard cur- 2V
RUN/SS CONTROLS
rent limit circuit that limits the maximum output current to 1V
DUTY CYCLE
MINIMUM DUTY CYCLE
a user-programmed level. It works by sensing the voltage 0.5V
0V
drop across QB during the time that QB is on and compar- 1704 F04

DRIVER DISABLE MODE

ing that voltage to a user-programmed voltage at IMAX. LTC1704 ENABLE
Since QB looks like a low value resistor during its on-time,
the voltage drop across it is proportional to the current Figure 4. Soft-Start Operation in Start Up and Current Limit
1704bfa

13
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The delay also acts as a pole in the current limit loop to
enhance loop stability. Prolonged overload conditions will
allow the RUN/SS pin to reach a steady state, and the
output will remain at a reduced voltage until the overload
is removed. Under current limit condition, if the output
voltage is less than 10% of its normal value, the soft-start
capacitor will be forced low immediately and the LTC1704
will rerun a complete soft-start cycle. The soft-start ca-
pacitor must be selected such that during power-up the
current through QB will not exceed the current limit value.
Power MOSFET RDS(ON) varies from MOSFET to MOSFET,
limiting the accuracy obtainable from the LTC1704 current
limit loop. Additionally, ringing on the SW node due to
parasitics can add to the apparent current, causing the
loop to engage early. When the load current increases
abruptly, the voltage feedback loop forces the duty cycle
to increase rapidly and the on-time of QB will be small
momentarily. The RDS(ON) of QB must be low enough to
ensure that the SW node is pulled low within the QB on-
time for proper current sensing. The LTC1704 current limit
is designed primarily as a disaster prevention, “no blow-
up” circuit, and is not useful as a precision current regu-
lator. It should typically be set around 50% above the
maximum expected normal output current to prevent com-
ponent tolerances from encroaching on the normal cur-
rent range. See the Switching Supply Current Limit Pro-
gramming section for advice on choosing a valve for RIMAX.
BURST MODE OPERATION (For Non-B Parts Only)
Theory of Operation
The LTC1704 (non-B part) switcher supply has two modes
of operation. Under heavy loads, it operates as a fully
synchronous, continuous conduction switching regula-
tor. In this mode of operation (“Continuous” mode), the
current in the inductor flows in the positive direction
(toward the output) during the entire switching cycle,
constantly supplying current to the load. In this mode, the
synchronous switch (QB) is on whenever QT is off, so the
current always flows through a low impedance switch,
minimizing voltage drop and power loss. This is the most
efficient mode of operation at heavy loads, where the
resistive losses in the power devices are the dominant loss
term.
14
Continuous mode works efficiently when the load current
is greater than half of the ripple current in the inductor. In
a buck converter like the LTC1704, the average current in
the inductor (averaged over one switching cycle) is equal
to the load current. The ripple current is the difference
between the maximum and the minimum current during
a switching cycle (see Figure 5a). The ripple current
depends on inductor value, clock frequency and output
voltage, but is constant regardless of load as long as the
LTC1704 remains in Continuous mode. See the Inductor
Selection section for a detailed description of ripple
current.
As the output load current decreases in Continuous mode,
the average current in the inductor will reach a point where
it drops below half the ripple current. At this point, the
current in the inductor will reverse during a portion of the
switching cycle, or begin to flow from the output back to
the input. This does not adversely affect regulation, but
does cause additional losses as a portion of the inductor
current flows back and forth through the resistive power
switches, giving away a little more power each time and
lowering the efficiency. There are some benefits to allow-
ing this reverse current flow: the circuit will maintain
regulation even if the load current drops below zero (the
load supplies current to the LTC1704) and the output
ripple voltage and frequency remain constant at all loads,
easing filtering requirements.
Besides the reverse current loss, the LTC1704 drivers are
still switching QT and QB on and off once a cycle. Each time
an external MOSFET is turned on, the internal driver must
charge its gate to PVCC. Each time it is turned off, that
charge is lost to ground. At the high switching frequency
that the LTC1704 operates, the charge lost to the gates can
add up to tens of milliamps from PVCC. As the load current
continues to drop, this quickly becomes the dominant
power loss term, reducing efficiency once again.
To minimize the efficiency loss due to switching loss and
reverse current flow at light loads, the LTC1704 (non-B
part) switches to a second mode of operation: Burst Mode
operation (Figure 5b). In Burst Mode operation, the
LTC1704 detects when the inductor current approaches
zero and turns off both drivers. During this time, the
voltage at the SW pin will float around VOUTSW, the voltage
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APPLICATIO S I FOR ATIO
across the inductor will be zero, and the inductor current
remains zero. This prevents current from flowing back-
wards in QB, eliminating that power loss term. It also
reduces the ripple current in the inductor as the output
current approaches zero.
IRIPPLE
INDUCTOR CURRENT
IAVERAGE
TIME
Figure 5a. Continous Mode
INDUCTOR CURRENT
IRIPPLE
IAVERAGE
1704 F05
TIME
Figure 5b. Burst Mode Operation
The LTC1704B does not shift into Burst Mode operation at
light loads, eliminating low frequency output ripple at the
expense of light load efficiency.
The LTC1704 detects when the inductor current has
reached zero by monitoring the voltage at the SW pin while
QB is on (see BURST in Block Diagram). Since QB acts like
a resistor, SW should ideally be right at 0V when the
inductor current reaches zero. In reality, the SW node will
ring to some degree immediately after it is switched to
ground by QB, causing some uncertainty as to the actual
moment the average current in QB goes to zero. The
LTC1704 minimizes this effect by turning on the Burst
Comparator only at the last 180ns of the switching period,
before QB turns off. In addition, the Burst Comparator is
disabled if QB turns on for less than 200ns. Despite this,
care must still be taken in the PCB layout to ensure that
proper kelvin sensing for the SW pin is provided. Connect
the SW pin of the LTC1704 as close to the drain of QB as
possible through a thick trace. The same applies to the
PGND pin of the LTC1704, which is the negative input of
the burst comparator and it should be connected close to
the source of QB through a thick trace. Ringing on the
PGND pin due to an insufficient PVCC bypass capacitor can
also cause the burst comparator to trip prematurely.
Connect at least a 10µF bypass capacitor directly from the
PVCC pin to PGND.
LTC1704/LTC1704B
The burst comparator is turned on only at the last 180ns
of the switching period, the propagation delay of the
comparator is designed to be fast so that a zero or low
positive voltage on the SW node can trip the comparator
within this 180ns. Low inductor ripple current coupled
with low MOSFET RDS(ON) may prolong the delay of the
burst comparator and prevent the comparator from trip-
ping. To overcome this, reduce the inductor value to
increase the ripple current and the SW node voltage
change.
The moment LTC1704 (non-B parts) enters Burst Mode
operation, both drivers skip several switching cycles until
the output droops. Once the voltage feedback loop requests
for an additional 10% duty cycle, the LTC1704 enters Con-
tinuous mode operation again. To eliminate audible noise
from certain types of inductors when they are lightly loaded,
LTC1704 includes an internal timer that forces Continuous
mode operation every 15µs.
In Burst Mode operation, both resistive loss and switching
loss are minimized while keeping the output in regulation.
The total deviation from the regulated output is within the
1.5% regulation tolerance of the LTC1704. As the load
current falls to zero in Burst Mode operation, the most
significant loss term becomes the 4.5mA quiescent cur-
rent drawn by the LTC1704—usually much less than the
minimum load current in a typical low voltage logic sys-
tem. Burst Mode operation maximizes efficiency at low load
currents, but can cause low frequency ripple in the output
voltage as the cycle-skipping circuitry switches on and off.
VSW
0V
TIME
5V
VBG
0V
TIME
BURST BURST
COMPARATOR
DISABLED IF QB
COMPARATOR
TURNS ON
1704 F06
TURNS ON FOR
LESS THAN 200ns
180ns BEFORE
QB TURNS OFF
Figure 6. Burst Comparator Turns On 180ns Before QB Turns Off
1704bfa
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Maximizing High Load Current Efficiency
Efficiency at high load currents is primarily controlled by
the resistance of the components in the power path (QT,
QB, L) and power lost in the gate drive circuits due to
MOSFET gate charge. Maximizing efficiency in this region
of operation is as simple as minimizing these terms.
The behavior of the load over time affects the efficiency
strategy. Parasitic resistances in the MOSFETs and the
inductor set the maximum output current the circuit can
supply without burning up. A typical efficiency curve
shows that peak efficiency occurs near 30% of this maxi-
mum current. If the load current will vary around the
efficiency peak and spend relatively little time at the
maximum load, choosing components so that the average
load is at the efficiency peak is a good idea. This puts the
maximum load well beyond the efficiency peak, but usu-
ally gives the greatest system efficiency over time, which
translates to the longest run time in a battery-powered
system. If the load is expected to be relatively constant at
the maximum level, the components should be chosen so
that this load lands at the peak efficiency point, well below
the maximum possible output of the converter.
Maximizing Low Load Current Efficiency
Low load current efficiency depends strongly on proper
operation in Burst Mode operation. In an ideally optimized
system, when Burst Mode operation is activated, gate
drive is the dominant loss term. Burst Mode operation
turns off all output switching for several clock cycles in a
row, significantly cutting gate drive losses. As the load
current in Burst Mode operation falls toward zero, the
current drawn by the circuit falls to the LTC1704’s back-
ground quiescent level, about 4.5mA.
To maximize low load efficiency, make sure the LTC1704
(non-B part) is allowed to enter Burst Mode operation as
cleanly as possible. Minimize ringing at the SW node so
that the Burst comparator leaves as little residual current
in the inductor as possible when QB turns off. It helps to
connect the SW pin of the LTC1704 as close to the drain
of QB as possible. An RC snubber network can also be
added from SW to PGND.
16
SWITCHER SUPPLY EXTERNAL
COMPONENT SELECTION
Power MOSFETs Selection
Getting peak efficiency out of the LTC1704 switcher sup-
ply depends strongly on the external MOSFETs used. The
LTC1704 requires at least two external MOSFETs—more
if one or more of the MOSFETs are paralleled to lower on-
resistance. To work efficiently, these MOSFETs must
exhibit low RDS(ON) at 5V VGS to minimize resistive power
loss while they are conducting current. They must also
have low gate charge to minimize transition losses during
switching. On the other hand, voltage breakdown require-
ments in a typical LTC1704 circuit are pretty tame; the 6V
maximum input voltage limits the VDS and VGS the MOSFETs
can see to safe levels for most devices.
Low RDS(ON)
RDS(ON) calculations are pretty straightforward. RDS(ON) is
the resistance from the drain to the source of the MOSFET
when the gate is fully on. Many MOSFETs have RDS(ON)
specified at 4.5V gate drive—this is the right number to
use in LTC1704 circuits running from a 5V supply. As
current flows through this resistance while the MOSFET is
on, it generates I2R watts of heat, where I is the current
flowing (usually equal to the output current) and R is the
MOSFET RDS(ON). This heat is only generated when the
MOSFET is on. When it is off, the current is zero and the
power lost is also zero (and the other MOSFET is busy
losing power).
This lost power does two things: it subtracts from the
power available at the output, costing efficiency, and it
makes the MOSFET hotter, both bad things. The effect is
worst at maximum load when the current in the MOSFETs
and thus the power lost, are at a maximum. Lowering
RDS(ON) improves heavy load efficiency at the expense of
additional gate charge (usually) and more cost (usually).
Proper choice of MOSFET RDS(ON) becomes a trade-off
between tolerable efficiency loss, power dissipation and
cost. Note that while the lost power has a significant effect
on system efficiency, it only adds up to a watt or two in a
typical LTC1704 circuit, allowing the use of small, surface
mount MOSFETs without heat sinks.
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Gate Charge
Gate charge is amount of charge (essentially, the number
of electrons) that the LTC1704 needs to put into the gate
of an external MOSFET to turn it on. The easiest way to
visualize gate charge is to think of it as a capacitance from
the gate pin of the MOSFET to SW (for QT) or to PGND (for
QB). This capacitance is composed of MOSFET channel
charge, actual parasitic drain-source capacitance and
Miller-multiplied gate-drain capacitance, but can be ap-
proximated as a single capacitance from gate to source.
Regardless of where the charge is going, the fact remains
that it all has to come out of PVCC to turn the MOSFET gate
on, and when the MOSFET is turned back off, that charge
all ends up at ground. In the meanwhile, it travels through
the LTC1704’s gate drivers, heating them up. More power
lost!
In this case, the power is lost in little bite-sized chunks, one
chunk per switch per cycle, with the size of the chunk set
by the gate charge of the MOSFET. Every time the MOSFET
switches, another chunk is lost. Clearly, the faster the
clock runs, the more important gate charge becomes as a
loss term. Old fashioned switchers that ran at 20kHz could
pretty much ignore gate charge as a loss term. In the
550kHz LTC1704, gate charge loss can be a significant
efficiency penalty. Gate charge loss can be the dominant
loss term at medium load currents, especially with large
MOSFETs. Gate charge loss is also the primary cause of
power dissipation in the LTC1704 itself.
TG Charge Pump
There’s another nuance of MOSFET drive that the LTC1704
needs to get around. The LTC1704 is designed to use
N-channel MOSFETs for both QT and QB, primarily be-
cause N-channel MOSFETs generally cost less and have
lower RDS(ON) than similar P-channel MOSFETs. Turning
QB on is no big deal since the source of QB is attached to
PGND; the LTC1704 just switches the BG pin between
PGND and PVCC . Driving QT is another matter. The source
of QT is connected to SW which rises to VIN when QT is on.
To keep QT on, the LTC1704 must get TG one MOSFET
VGS(ON) above VIN. It does this by utilizing a floating driver
with the negative lead of the driver attached to SW (the
source of QT) and the PVCC lead of the driver coming out
LTC1704/LTC1704B
separately at BOOST. An external 1µF capacitor (CCP)
connected between SW and BOOST (Figure 2) supplies
power to BOOST when SW is high, and recharges itself
through DCP when SW is low. This simple charge pump
keeps the TG driver alive even as it swings well above VIN.
The value of the bootstrap capacitor CCP needs to be at
least 100 times that of the total input capacitance of the
topside MOSFET(s). For very large external MOSFETs (or
multiple MOSFETs in parallel), CCP may need to be in-
creased beyond the 1µF value.
Input Supply
The BiCMOS process that allows the LTC1704 switcher
supply to include large MOSFET drivers on-chip also limits
the maximum input voltage to 6V. This limits the practical
maximum input supply to a loosely regulated 5V or 6V rail.
At the same time, the input supply needs to supply several
amps of current without excessive voltage drop. The input
supply must have regulation adequate to prevent sudden
load changes from causing the LTC1704 input voltage to
dip. In most typical applications where the LTC1704 is
generating a secondary low voltage logic supply, all of
these input conditions are met by the main system logic
supply when fortified with an input bypass capacitor.
Input Bypass Capacitor Selection
A typical LTC1704 circuit running from a 5V logic supply
might provide 1.6V at 10A at its switcher output. 5V to
1.6V implies a duty cycle of 32%, which means QT is on
32% of each switching cycle. During QT’s on-time, the
current drawn from the input equals the load current and
during the rest of the cycle, the current drawn from the
input is near zero. This 0A to 10A, 32% duty cycle pulse
train results in 4.66ARMS ripple current. At 550kHz, switch-
ing cycles last about 1.8µs; most system logic supplies
have no hope of regulating output current with that kind of
speed. A local input bypass capacitor is required to make
up the difference and prevent the input supply from
dropping drastically when QT kicks on. This capacitor is
usually chosen for RMS ripple current capability and ESR
as well as value.
Consider our 10A example. The input bypass capacitor
gets exercised in three ways: its ESR must be low enough
1704bfa
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LTC1704/LTC1704B
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APPLICATIO S I FOR ATIO
to keep the initial drop as QT turns on within reason
(100mV or so); its RMS current capability must be ad-
equate to withstand the 4.66A capacitor ripple current is
not the same as input RMS current at the input and the
capacitance must be large enough to maintain the input
voltage until the input supply can make up the difference.
Generally, a capacitor that meets the first two parameters
will have far more capacitance than is required to keep
capacitance-based droop under control. In our example,
we need 0.01Ω ESR to keep the input drop under 100mV
with a 10A current step and 5.65ARMS ripple current
capacity to avoid overheating the capacitor. These re-
quirements can be met with multiple low ESR tantalum or
electrolytic capacitors in parallel, or with a large mono-
lithic ceramic capacitor.
IRMSIN = 5.65
IDCIN = 3.2A
IRIPP = (5.65)2 – (3.2)2 = 4.66ARMS
Tantalum capacitors are a popular choice as input capaci-
tors for LTC1704 applications, but they deserve a special
caution here. Generic tantalum capacitors have a destruc-
tive failure mechanism when they are subjected to large
RMS currents (like those seen at the input of an LTC1704).
At some random time after they are turned on, they can
blow up for no apparent reason. The capacitor manufac-
turers are aware of this and sell special “surge tested”
tantalum capacitors specifically designed for use with
switching regulators. When choosing a tantalum input
capacitor, make sure that it is rated to carry the RMS
current that the LTC1704 will draw. If the data sheet
doesn’t give an RMS current rating, chances are the
capacitor isn’t surge tested. Don’t use it!
Output Bypass Capacitor Selection
The output bypass capacitor has quite different require-
ments from the input capacitor. The ripple current at the
output of a buck regulator, like the LTC1704’s switcher
controller, is much lower than at the input because the
inductor current is constantly flowing at the output when-
ever the LTC1704 is operating in Continuous mode. The
primary concern at the output is capacitor ESR. Fast load
current transitions at the output will appear as voltage
18
across the ESR of the output bypass capacitor until the
feedback loop in the LTC1704 can change the inductor
current to match the new load current value. This ESR step
at the output is often the single largest budget item in the
load regulation calculation. As an example, our hypotheti-
cal 1.6V, 10A switcher with a 0.01Ω ESR output capacitor
would experience a 100mV step at the output with a 0A to
10A load step—a 6.3% output change!
Usually the solution is to parallel several capacitors at the
output. For example, to keep the transient response inside
of 3% with the previous design, we’d need an output ESR
better than 0.0048Ω. This can be met with three 0.014Ω,
470µF tantalum capacitors in parallel.
Inductor Selection
The inductor in a typical LTC1704 circuit is chosen prima-
rily for value and saturation current. The inductor value
sets the ripple current, which is commonly chosen at
around 40% of the anticipated full load current. Ripple
current is set by:
tON(QB) (VOUT )
IRIPPLE =
L
In our hypothetical 1.6V, 10A example, we’d set the ripple
to 40% of 10A or 4A, and the inductor value would be:
tON(QB)( VOUT ) (1.2µs)(1.6 V)
L= = = 0.5µH
IRIPPLE 4A
 1.6 V 
with tON(QB) =  1 −  / 550kHz = 1.2µs
 5V 
The inductor must not saturate at the expected peak
current. In this case, if the current limit was set to 15A, the
inductor should be rated to withstand 15A + 1/2IRIPPLE, or
17A without saturating.
FEEDBACK LOOP/COMPENSATION
Feedback Loop Types
In a typical LTC1704 switcher circuit, the feedback loop
consists of the modulator, the external inductor and
output capacitor, and the feedback amplifier and its com-
1704bfa

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APPLICATIO S I FOR ATIO
pensation network. All of these components affect loop
behavior and need to be accounted for in the loop compen-
sation. The modulator consists of the internal PWM gen-
erator, the output MOSFET drivers and the external
MOSFETs themselves. From a feedback loop point of view,
it looks like a linear voltage transfer function from COMP
to SW and has a gain roughly equal to the input voltage. It
has fairly benign AC behavior at typical loop compensation
frequencies with significant phase shift appearing at half
the switching frequency.
The external inductor/output capacitor combination makes
a more significant contribution to loop behavior. These
components cause a second order LC roll-off at the
output, with the attendant 180° phase shift. This roll-off is
what filters the PWM waveform, resulting in the desired
DC output voltage, but the phase shift complicates the
loop compensation if the gain is still higher than unity at
the pole frequency. Eventually (usually well above the LC
pole frequency), the reactance of the output capacitor will
approach its ESR, and the roll-off due to the capacitor will
stop, leaving 6dB/octave and 90° of phase shift (Figure 7).
So far, the AC response of the loop is pretty well out of the
user’s control. The modulator is a fundamental piece of
the LTC1704 design, and the external L and C are usually
chosen based on the regulation and load current require-
ments without considering the AC loop response. The
feedback amplifier, on the other hand, gives us a handle
with which to adjust the AC response. The goal is to have
180° phase shift at DC (so the loop regulates) and
something less than 360° phase shift at the point that the
loop gain falls to 0dB. The simplest strategy is to set up the
PHASE (DEG)
GAIN (dB)
GAIN
AV
–12dB/OCT
0 FREQ
PHASE –90
–180
–6dB/OCT
–270
–360
1704 F05
Figure 7. Transfer Function of Buck Modulator
LTC1704/LTC1704B
feedback amplifier as an inverting integrator, with the 0dB
frequency lower than the LC pole (Figure 8). This “Type 1”
configuration is stable but transient response will be less
than exceptional if the LC pole is at a low frequency.
Figure 9 shows an improved “Type 2” circuit that uses an
additional pole-zero pair to temporarily remove 90° of phase
shift. This allows the loop to remain stable with 90° more
phase shift in the LC section, provided the loop reaches 0dB
gain near the center of the phase “bump.” Type 2 loops work
well in systems where the ESR zero in the LC roll-off hap-
pens close to the LC pole, limiting the total phase shift due
to the LC. The additional phase compensation in the feed-
back amplifier allows the 0dB point to be at or above the
LC pole frequency, improving loop bandwidth substantially
over a simple Type 1 loop. It has limited ability to compen-
sate for LC combinations where low capacitor ESR keeps
the phase shift near 180° for an extended frequency range.
LTC1704 circuits using conventional switching grade elec-
trolytic output capacitors can often get acceptable phase
margin with Type 2 compensation.
“Type 3” loops (Figure 10), use two poles and two zeros
to obtain a 180° phase boost in the middle of the frequency
band. A properly designed Type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180° phase shift
well above the initial LC roll-off. As with a Type 2 circuit,
the loop should cross through 0dB in the middle of the
phase bump to maximize phase margin. Many LTC1704
circuits use low ESR tantalum or OS-CON output capaci-
tors need Type 3 compensation to obtain acceptable phase
margin with a high bandwidth feedback loop.
PHASE (DEG)
GAIN (dB)
IN C1
GAIN
R1
FB
– –6dB/OCT
R2 COMP 0 FREQ
VREF + –90
–180
PHASE
–270
–360
1704 F06
Figure 8. Type 1 Schematic and Transfer Function
1704bfa
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C2 rate results, but simulation can often get close enough to

PHASE (DEG)
GAIN (dB)
IN C1 give a working system. To measure the modulator gain and
R4 –6dB/OCT
phase directly, wire up a breadboard with an LTC1704 and
R1
FB
GAIN the actual MOSFETs, inductor, and input and output capaci-
– –6dB/OCT
tors that the final design will use. This breadboard should
R2 COMP 0 FREQ
use appropriate construction techniques for high speed
VREF + –90
PHASE –180
analog circuitry: bypass capacitors located close to the
–270
LTC1704, no long wires connecting components, appro-
–360
priately sized ground returns, etc. Wire the feedback am-
1704 F09 plifier as a simple Type 1 loop, with a 10k resistor from
Figure 9. Type 2 Schematic and Transfer Function VOUTSW to FB and a 0.1µF feedback capacitor from COMP
to FB. Choose the bias resistor (R2) as required to set the
IN C2
PHASE (DEG)
desired output voltage. Disconnect R2 from ground and
connect it to a signal generator or to the source output of
GAIN (dB)

C3 C1
R4
a network analyzer (Figure 11) to inject a test signal into the
R1 R3
FB
–6dB/OCT
loop. Measure the gain and phase from the COMP pin to
– +6dB/OCT –6dB/OCT the output node at the positive terminal of the output ca-
GAIN
R2 COMP 0 FREQ
pacitor. Make sure the analyzer’s input is AC coupled so that
VREF + –90
the DC voltages present at both the COMP and VOUTSW
PHASE –180
nodes don’t corrupt the measurements or damage the
–270
analyzer.
–360
1704 F10 5V
10Ω

Figure 10. Type 3 Schematic and Transfer Function +

10µF
MBR0530T
VCC PVCC
Feedback Component Selection VCOMP TO
COMP TG QT
ANALYZER
0.1µF BOOST
Selecting the R and C values for a typical Type 2 or Type 1µF
3 loop is a nontrivial task. The applications shown in this FB LTC1704 SW L
VOUTSW TO
R2 10k ANALYZER
data sheet show typical values, optimized for the power BG QB +
COUT
components shown. They should give acceptable perfor- AC SOURCE RUN/SS NC
FROM
mance with similar power components, but can be way ANALYZER
GND PGND

off if even one major power component is changed

1704 F11
significantly. Applications that require optimized tran-
sient response will need to recalculate the compensation Figure 11. Modulator Gain/Phase Measurement Setup
values specifically for the circuit in question. The under-
lying mathematics are complex, but the component If breadboard measurement is not practical, a SPICE
values can be calculated in a straightforward manner if simulation can be used to generate approximate gain/
we know the gain and phase of the modulator at the phase curves. Plug the expected capacitor, inductor and
crossover frequency. MOSFET values into the following SPICE deck and gener-
Modulator gain and phase can be measured directly from ate an AC plot of V(VOUTSW)/V(COMP) in dB and phase of
a breadboard, or can be simulated if the appropriate para- V(OUTSW) in degrees. Refer to your SPICE manual for
sitic values are known. Measurement will give more accu- details of how to generate this plot.

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*1704 modulator gain/phase TYPE 2 Loop:
*2001 Linear Technology
*this file written to run with PSpice 9.0
 BOOST 
*may require modifications for other SPICE
K = Tan  + 45°
simulators  2 
*MOSFETs 1
rfet mod sw 0.02 ;MOSFET rdson C2 =
2πfGKR1
*inductor
lext sw out1 1u ;inductor value (
C1 = C2 K2 − 1 )
rl out1 outsw 0.005 ;inductor series R K
R4 =
*output cap 2πfC1
cout outsw out2 1000u ;capacitor value VREF (R1)
resr out2 0 0.01 ;capacitor ESR R2 =
VOUTSW − VREF
*1704 internals
emod mod 0 comp 0 5 ;3.3 for 3.3V supply
vstim comp 0 0 ac 1 ;ac stimulus TYPE 3 Loop:
.ac dec 100 1k 1meg
.probe
 BOOST 
.end K = Tan2  + 45°
 4 
With the gain/phase plot in hand, a loop crossover fre-
quency can be chosen. Usually the curves look something 1
C2 =
like Figure 7. Choose the crossover frequency in the rising 2πfGR1
or flat parts of the phase curve, beyond the external LC C1 = C2(K − 1)
poles. Frequencies between 10kHz and 50kHz usually
K
work well. Note the gain (GAIN, in dB) and phase (PHASE, R4 =
in degrees) at this point. The desired feedback amplifier 2πfC1
gain will be – GAIN to make the loop gain at 0dB at this R1
R3 =
frequency. Now calculate the needed phase boost, assum- K −1
ing 60° as a target phase margin: 1
C3 =
BOOST = – (PHASE + 30°) 2πf KR3
VREF (R1)
If the required BOOST is less than 60°, a Type 2 loop can R2 =
be used successfully, saving two external components. VOUTSW − VREF
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance. SWITCHING SUPPLY CURRENT LIMIT
Finally, choose a convenient resistor value for R1 (10k is PROGRAMMING
usually a good value). Now calculate the remaining values: Programming the current limit on the LTC1704 switcher
(K is a constant used in the calculations) supply is straightforward. The IMAX pin sets the current
limit by setting the maximum allowable voltage drop
f = chosen crossover frequency across QB (the bottom MOSFET) before the current limit
G = 10(GAIN/20) (this converts GAIN in dB to G in circuit engages. The voltage across QB is set by its on-
absolute gain) resistance and the current flowing in the inductor, which

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is the same as the output current. The LTC1704 current
limit circuit inverts the voltage at IMAX before comparing
it with the negative voltage across QB, allowing the current
limit to be set with a positive voltage.
To set the current limit, calculate the expected voltage
drop across QB at the maximum desired current:
VPROG = (ILIMIT)(RDS(ON))
ILIMIT should be chosen to be quite a bit higher than the
expected operating current, to allow for MOSFET RDS(ON)
changes with temperature. Setting ILIMIT to 150% of the
maximum normal operating current is usually safe and will
adequately protect the power components if they are
chosen properly. Note that the ringing on the switch node
can cause error for the current limit threshold (illustrated
in Figure 6). This factor will change depending on the
layout and the components used. VPROG is then pro-
grammed at the IMAX pin using the internal 10µA pull-up
and an external resistor:
RIMAX = VPROG/10µA
The resulting value of RIMAX should be checked in an ac-
tual circuit to ensure that the current circuit kicks in as
expected. MOSFET RDS(ON) specs are like horsepower
ratings in automobiles, and should be taken with a grain of
salt. Circuits that use very low values for RIMAX (< 10k)
should be checked carefully, since small changes in RIMAX
can cause large ILIMIT changes when the switch node ring-
ing makes up a large percentage of the total VPROG value.
If VPROG is set too low, the LTC1704 may fail to start up.
Accuracy Trade-Offs
The VDS sensing scheme used in the LTC1704 is not
particularly accurate, primarily due to uncertainty in the
RDS(ON) from MOSFET to MOSFET. A second error term
arises from the ringing present at the SW pin, which
causes the VDS to look larger than (ILOAD)(RDS(ON)) at the
beginning of QB’s on-time. Another important error is due
to poor PCB layout. Care should be taken to ensure that
proper kelvin sensing of the SW pin is provided. These
inaccuracies do not prevent the LTC1704 current limit
circuit from protecting itself and the load from damaging
overcurrent conditions, but they do prevent the user from
22
setting the current limit to a tight tolerance if more than
one copy of the circuit is being built. The 50% factor in the
current setting equation above reflects the margin neces-
sary to ensure that the circuit will stay out of current limit
at the maximum normal load, even with a hot MOSFET that
is running quite a bit higher than its RDS(ON) spec.
REGULATION OVER COMPONENT
TOLERANCE/TEMPERATURE
DC Regulation Accuracy
The LTC1704’s switcher controller initial DC output accu-
racy depends mainly on internal reference accuracy and
internal op amp offset. Two LTC1704 specs come into
play: feedback voltage and feedback voltage line regula-
tion. The feedback voltage spec is 800mV ±12mV over the
full temperature range and is specified at the FB pin, which
encompasses both reference accuracy and any op amp
offset. This accounts for 1.5% error at the output with a 5V
input supply. The feedback voltage line regulation spec
adds an additional 0.1%/V term that accounts for change
in reference output with change in input supply voltage.
With a 5V supply, the errors contributed by the LTC1704
itself add up to no more than 1.5% DC error at the output.
The output voltage setting resistors (see R1 and R2 in the
Typical Applications) are the other major contributor to DC
error. At a typical 1.xV output voltage, the resistors are of
roughly the same value, which tends to halve their error
terms, improving accuracy. Still, using 1% resistors for
R1 and R2 will add 1% to the total output error budget.
Using 0.1% resistors in just those two positions can nearly
halve the DC output error for very little additional cost.
Load Regulation
Load regulation is affected by feedback voltage, feedback
amplifier gain and external ground drops in the feedback
path. Feedback voltage is covered above and is within
1.5% over temperature. A full range load step might
require a 10% duty cycle change to keep the output
constant, requiring the COMP pin to move about 100mV.
With amplifier gain at 85dB, this adds up to only a 10µV
shift at FB, negligible compared to the reference accuracy
terms.
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External ground drops aren’t so negligible. The LTC1704
can sense the positive end of the output voltage by
attaching the feedback resistor directly at the load, but it
cannot do the same with the ground lead. Just 0.001Ω of
resistance in the ground lead at 10A load will cause a 10mV
error in the output voltage—as much as all the other DC
errors put together. Proper layout becomes essential to
achieving optimum load regulation from the LTC1704. A
properly laid out LTC1704 circuit should move less than a
millivolt at the output from zero to full load.
Transient Response
Transient response is the other half of the regulation
equation. The LTC1704 can keep the DC output voltage
constant to within 1% when averaged over hundreds of
cycles. Over just a few cycles, however, the external
components conspire to limit the speed that the output
can move. Consider a typical 5V to 1.5V circuit, subjected
to a 1A to 5A load transient. Initially, the loop is in
regulation and the DC current in the output capacitor is
zero. Suddenly, an extra 4A start flowing out of the output
capacitor while the inductor is still supplying only 1A. This
sudden change will generate a (4A)(RESR ) voltage step at
the output; with a typical 0.015Ω output capacitor ESR,
this is a 60mV step at the output, or 4% (for a 1.5V output
voltage.)
Very quickly, the feedback loop will realize that something
has changed and will move at the bandwidth allowed by
the external compensation network towards a new duty
cycle. If the bandwidth is set to 50kHz, the COMP pin will
get to 60% of the way to 90% duty cycle in 3µs. Now the
inductor is seeing 3.5V across itself for a large portion of
the cycle, and its current will increase from 1A at a rate set
by di/dt = V/L. If the inductor value is 0.5µH, the di/dt will
be 3.5V/0.5µH or 7A/µs. Sometime in the next few micro-
seconds after the switch cycle begins, the inductor current
will have risen to the 5A level of the load current and the
output voltage will stop dropping. At this point, the induc-
tor current will rise somewhat above the level of the output
current to replenish the charge lost from the output
capacitor during the load transient. During the next couple
of cycles, the MIN comparator may trip on and off,
preventing the output from falling below its – 5% thresh-
LTC1704/LTC1704B
old until the time constant of the compensation loop runs
out and the main feedback amplifier regains control. With
a properly compensated loop, the entire recovery time will
be inside of 10µs.
Most loads care only about the maximum deviation from
ideal, which occurs somewhere in the first two cycles after
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirely controlled by the ESR of the capacitor and amounts
to most of the total voltage drop. To minimize this drop,
reduce the ESR as much as possible by choosing low ESR
capacitors and/or paralleling multiple capacitors at the
output. The capacitance value accounts for the rest of the
voltage drop until the inductor current rises. With most
output capacitors, several devices paralleled to get the
ESR down will have so much capacitance that this drop
term is negligible. Ceramic capacitors are an exception; a
small ceramic capacitor can have suitably low ESR with
relatively small values of capacitance, making this second
drop term significant.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC1704 to
recover after the output voltage has dropped due to output
capacitor ESR. Optimizing loop compensation entails
maintaining the highest possible loop bandwidth while
ensuring loop stability. The Feedback Component Selec-
tion section describes in detail the techniques used to
design an optimized Type 3 feedback loop, appropriate for
most LTC1704 systems.
Measurement Techniques
Measuring transient response presents a challenge in two
respects: obtaining an accurate measurement and gener-
ating a suitable transient to use to test the circuit. Output
measurements should be taken with a scope probe di-
rectly across the output capacitor. Proper high frequency
probing techniques should be used. In particular, don’t
use the 6" ground lead that comes with the probe! Use an
adapter that fits on the tip of the probe and has a short
ground clip to ensure that inductance in the ground path
1704bfa
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doesn’t cause a bigger spike than the transient signal
being measured. Conveniently, the typical probe tip ground
clip is spaced just right to span the leads of a typical output
capacitor. Make sure the bandwidth limit on the scope is
turned off, since a significant portion of the transient
energy occurs above the 20MHz cutoff.
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test, and switch it on and off while
watching the output. If this isn’t convenient, a current step
generator is needed. This generator needs to be able to
turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC1704 and the transient generator
must be minimized.
Figure 12 shows an example of a simple transient genera-
LINEAR REGULATOR SUPPLY
Linear Regulator Output Voltage
The linear regulator senses the output voltage at VOUTREG
with an internal amplifier (see Figure 13). The amplifier
negative input is connected internally to an 800mV refer-
ence, while the positive input is connected to the REGFB
pin. The amplifier output drives a P-channel transistor
MREG, which is in turn connected to the external NPN pass
transistor. The linear regulator output voltage can be
obtained using the following equation:
 R5 
VOUTREG = 0.8 V 1 + 
 R6 
LTC1704 VCC

tor. Be sure to use a noninductive resistor as the load 1.9µA

RREGILM
REGILM
element—many power resistors use an inductive spiral VREGON
pattern and are not suitable for use here. A simple solution CDELAY
+ IP
is to take ten 1/4W film resistors and wire them in parallel
AMP
to get the desired value. This gives a noninductive resistive
–
load which can dissipate 2.5W continuously or 50W if REG MOFF REGOFF
VREF
pulsed with a 5% duty cycle, enough for most LTC1704 ILM
VCC
–
circuits. Solder the MOSFET and the resistor(s) as close to
the output of the LTC1704 circuit as possible and set up REGFB MREG VINREG
+ REGDR
the signal generator to pulse at a 100Hz rate with a 5% duty QEXT

cycle. This pulses the LTC1704 with 500µs transients 2mA

10ms apart, adequate for viewing the entire transient REGFB

R5
+
COUTREG VOUTREG
recovery time for both positive and negative transitions
R6
while keeping the load resistor cool.
1704 F13

LTC1704 VOUTSW Figure 13. Linear Regulator

RLOAD

PULSE IRFZ44 OR Linear Regulator Supplies Requirement

GENERATOR EQUIVALENT
50Ω The linear regulator operates with two supplies: VCC for the
0V TO 10V
100Hz, 5% LTC1704 and VINREG for the external NPN transistor QEXT.
DUTY CYCLE
1704 F12
Both supplies must be higher than the minimum value
LOCATE CLOSE TO THE OUTPUT
determined by the linear regulator output voltage, VOUTREG.
For a desired VOUTREG, use the following formula to
Figure 12. Transient Load Generator
calculate the minimum required VCC:
Minimum VCC = VOUTREG + VBE(QEXT) + VDROPOUT
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where VBE(QEXT) is base emitter voltage of QEXT and
VDROPOUT is the LTC1704 linear regulator controller drop-
out voltage.
The MJD44H11 from ON Semiconductor has a VBE of
around 0.9V at IC = 2A, 25°C and the LTC1704’s VDROPOUT
is 1.1V maximum with 30mA of drive current.
If the computed minimum VCC is less than the LTC1704
requirement of 3.15V then 3.15V should be used.
The minimum VINREG is determined by the VCE saturation
voltage of QEXT when it is driven with a base current equal
to the maximum REGDR pin drive current. The D44H11
has a saturation voltage of around 0.2V at IC = 2A, 25°C.
A typical 1.5V VOUTREG, 2A application will need a mini-
mum VCC of 1.5V + 0.9V + 1.1V = 3.5V and a minimum
VINREG of 1.5V + 0.2V = 1.7V to operate.
If a VOUTREG of 0.8V is needed, the minimum VCC should
be 3.15V and the minimum VINREG is 0.8V + 0.2V = 1V.
External NPN Pass Transistor
The external NPN Pass transistor for the LTC1704 linear
regulator supply should be selected based on the follow-
ing criteria:
1. Maximum output current
2. DC current gain hFE
3. Total allowable power dissipation
4. Gain bandwidth product fT
The NPN transistor must be able to supply the maximum
operating current for the linear regulator supply. At the
same time, the DC current gain hFE must be large enough
such that the pass transistor can supply the maximum
load current with 30mA of base current. The transistor
must not be subjected to power dissipation higher than
the rated value, both during normal operation and over-
load conditions. Heat sink can be used to increase the
alloweable power dissipation rating. The gain bandwidth
product fT of the transistor determines how fast the linear
regulator can follow an output load change without losing
voltage regulation.
LTC1704/LTC1704B
The MJD44H11 from ON Semiconductor and SGS-
Thomson can be used in the LTC1704 linear regulator
supply with current ratings up to 2A. The MJD44H11 from
ON Semiconductor can supply 8A of output current and
the minimum DC Current Gain hFE is 60 at IC = 2A. The
power dissipation rating is 1.75W without heat sink and
the gain bandwidth product fT of the MJD44H11 is typi-
cally 50MHz.
Linear Regulator Supply Current Limit Programming
The LTC1704 linear regulator uses an external resistor
RREGILM to program the NPN pass transistor base current.
This indirectly programs the linear regulator current limit
threshold. Figure 13 shows the setup. One end of the
resistor RREGILM is connected to an external voltage
source VREGON or, alternatively, it can be connected to the
VCC pin. The other end of the resistor is connected to the
REGILM pin. REGILM is internally regulated to 0.8V. The
voltage difference across this resistor generates the
REGILM pin input current. This current, together with the
internal 1.9µA current source, programs the REGDR maxi-
mum output current. The actual linear regulator current
limit depends on the pass transistor’s widely distributed
DC current gain hFE, which makes this current limit scheme
not particularly accurate. Nevertheless, this method re-
moves the expensive current sense resistor and with
careful design, it is sufficient to protect the external NPN
from over damaging.
The following equation shows the relationship between
RREGILM and the linear regulator current limit threshold
ILT:
RREGILM =
( VREGON – 0.8)(2100)
 ILT 
 – 7.5mA
 hFE 
where VREGON is the pull-up voltage source for RREGILM
(see Figure 13).
When there is an overload at the linear regulator output,
the current limit circuit fires and the output voltage drops.
To protect the NPN from excessive heating, the controller
1704bfa
25
LTC1704/LTC1704B
U U W U
APPLICATIO S I FOR ATIO
reduces the available base current to minimize the ILOAD •
VCE product across the pass transistor. The amount of
current reduction depends on the REGFB pin voltage and
the RREGILM resistance (refer to the Typical Performance
Characteristics Curves). This current limit foldback scheme
limits the NPN power dissipation and prevents it from
blowing up. However, in cases when there is a constant
current load at the regulator output, this current limit
foldback scheme can create a start-up problem. In spite of
this, most applications do not have full load requirement
during start-up. To fulfill majority applications require-
ments, the LTC1704 linear regulator allows a small amount
of base current when the linear regulator output is shorted
or VREGFB = 0V. The actual regulator short-circuit current
can be calculated from the following equation:
 V – 0.8  than the calculated value.
ISH = hFE  4.8mA + REGON • 300
 RREGILM  The LTC1704 linear regulator turn-on delay circuit is
This short-circuit current should be checked against the
load requirement to allow proper start-up.
Linear Regulator Power Down
The linear regulator can be powered down easily. A pull-
down device (MOFF as shown in Figure 13) that is capable
of overcoming the REGILM pin 1.9µA weak pull-up current
can shut down the linear regulator. As shown in Figure 13,
if the resistor RREGILM is smaller than 400k, forcing
VREGON to ground can overcome the pull-up current and
power down the linear regulator. When both the REGILM
and RUN/SS pins are forced low, LTC1704 enters shut-
down mode and the quiescent current is reduced to 75µA.
Linear Regulator Turn-On Delay
The external capacitor CDELAY from the REGILM pin to
ground allows the REGILM pin to ramp up slowly and adds
26
a delay to the turn-on time of the linear regulator. The
current through the resistor RREGILM, the internal pull-up
current and the external capacitor CDELAY controls the
REGILM pin slew rate. To power up the linear regulator,
the potential at the REGILM pin should not be below 0.8V.
To add power sequencing to the linear regulator is easy.
Once the current limit resistor RREGILM is chosen, the
capacitor CDELAY can be added to program the turn on
delay using the following equation:
0.8 • CDELAY
tDELAY =
VREGON – 0.8
+ 1.9µA
RREGILM
The actual turn-on delay, which includes the time for the
external NPN to charge the output capacitor, will be longer
versatile; CDELAY capacitance should be larger than 100pF
to allow instantaneous power up to seconds long delay.
Linear Regulator Output Bypass Capacitor
The linear regulator requires the use of an output capacitor
as part of the frequency compensation network. A mini-
mum output capacitor of 10µF with an ESR lower than
100mΩ is recommended to prevent oscillations. Larger
values of output capacitance with low ESR should be used
to provide improved transient response for large load
current changes.
Many different types of capacitors are available and have
widely varying characteristics. These capacitors differ in
capacitor tolerance (sometimes ranging up to ±100%),
equivalent series resistance, equivalent series inductance
and capacitance temperature coefficient. Low ESR tanta-
lum capacitors are recommended for this linear regulator.
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 LTC1704/LTC1704B
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)

.045 ±.005 .189 – .196*

(4.801 – 4.978)
.009
(0.229)
16 15 14 13 12 11 10 9 REF

.254 MIN .150 – .165

.229 – .244 .150 – .157**

(5.817 – 6.198) (3.810 – 3.988)

.0165 ± .0015 .0250 TYP

RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8

.015 ± .004
× 45° .053 – .068 .004 – .0098
(0.38 ± 0.10)
(1.351 – 1.727) (0.102 – 0.249)
.007 – .0098
0° – 8° TYP
(0.178 – 0.249)

.016 – .050 .008 – .012 .0250

(0.406 – 1.270) (0.203 – 0.305) (0.635)
NOTE: BSC
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE GN16 (SSOP) 0502

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

1704bfa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27
LTC1704/LTC1704B
U
TYPICAL APPLICATIO

VID Controlled Power Supply

10Ω
VIN
5V DCP +
CIN +
330µF MBR0520LT1 1µF RREGILM 10µF
1µF 5k
10V 470k
×3
16 15 11
CCP
1µF CDELAY
BOOST PVCC VCC
QTA QTB 1000pF
L1 1 12
TG PGOOD
0.68µH
2 10
SW REGILM
COUTSW 3.3V
VOUTSW + 14 4 +
1.3V TO 3.5V 180µF QBB QBA BG RUN/SS 10µF
4V RMAX CSS
15A 0.1µF
×6 13.7k 3 LTC1704
8
IMAX GND
VIN QEXT
6 R3 13 7
C3 PGND REGDR ON SEMICONDUCTOR
SENSE 1.8k D44H11
5 10 1800pF 6
VCC FB FB
9 LTC1706-81 C1 R4 C2 R5
GND
1800pF 11k 330pF 5 9 1.69k + COUTREG VOUTREG
VID0 VID1 VID2 VID3 VID4 COMP REGFB 100µF 2.5V
R6 TANT 2A
CIN: KEMET T510X337K010AS 806Ω
COUTSW: PANASONIC EEFUE0G181R
FROM µP L1: SUMIDA CEP125-4712-T007 1704 TA02

QTA, QTB, QBA, QBB: FAIRCHILD FDS6670A

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No RSENSE is a trademark of Linear Technology Corporation.
1704bfa
LT/TP 0303 1K REV A • PRINTED IN USA
Linear Technology Corporation
28 1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ●
www.linear.com  LINEAR TECHNOLOGY CORPORATION 2001