Lab2: Verilog operators

1.Work on operators
Logical operators:
Simulation code:
module logicalop_tb();
reg [2:0]a,b;
reg c;
reg x,y,z;
initial
begin
a=3'd5;
b=3'b111;
c=1'bx;
x=a&&b;
#10;
y=a||b;
#10;
z=b&&0;
#10;
x=!a;
#10;
end
initial $monitor("a=%d,b=%b,c=%b,x=%b,y=%b,z=%b",a,b,c,x,y,z);
endmodule
Simulation waveform:
Transcript:

Bitwise operators:
Simulation code:
module bitwise_tb;
reg [2:0]a,b,c,x,y,z;
initial
begin
a=3'd5;
b=3'b111;
c=3'bx;
x=a&b;
#10;
y=a|c;
#10;
z=b^3'b1;
#10;
x=~a;
#10;
y=a~^b;
#10;
end
initial $monitor("a=%d,b=%b,c=%b,x=%b,y=%b,z=%b",a,b,c,x,y,z);
endmodule
Simulation waveform:
Transcript:

Reduction operators:
Simulation code:
module reduction_tb;
reg [3:0]a,b;
reg y,z;
initial
begin
a=4'b0010;
b=4'b1000;
y=~&b;
#10;
z=^a;
#10;
y=|a;
#10;
z=&b;
#10;
y=~|a;
#10;
z=~^a;
#10;
end
initial $monitor("a=%b,b=%b,y=%b,z=%b",a,b,y,z);
endmodule

Simulation waveform:

Transcript:

Relational operators:
Simulation code:
module relation_tb;
reg [3:0]a,b;
reg y1,y2,y3,y4;
initial
begin
a=4'b0010;
b=4'b0011;
y1=(a>b);
#10;
y2=(a<b);
#10;
y1=(a<=b);
#10;
y2=(a>=b);
#10;
a=4'b101x;
b=4'b1010;
y3=(a>b);
#10;
y4=(a<b);
#10;
end
initial $monitor("a=%b,b=%b,y1=%b,y2=%b,y3=%b,y4=%b",a,b,y1,y2,y3,y4);
endmodule

Simulation waveform:

Transcript:
Equality operators:
Simulation code:
module equality_tb;

reg [3:0]a,b;

reg y1,y2,y3,y4,y5,y6;

initial

begin

a=4'b0010;

b=4'b0011;

y1=(a==b);

#10;

y2=(a!=b);

#10;

a=4'b101x;

b=4'b1010;

y3=(a===b);

#10;

y4=(a!==b);

#10;

y5=(a==b);

#10;

y6=(a!=b);

#10;

end

initial $monitor("a=%b,b=%b,y1=%b,y2=%b,y3=%b,y4=%b,y5=%b,y6=%b",a,b,y1,y2,y3,y4,y5,y6);

endmodule

Simulation waveform:
Transcript:

Shift operators:
Simulation code:
module shift_tb;
reg [3:0]a,b,x,y,z;
reg signed [3:0]c;
initial
begin
a=4'b0110;
b=4'b1100;
c=4'b1101;
x=a<<1;
#10;
y=a>>2;
#10;
z=a>>>1;
#10;
z=c>>>1;
#10;
end
initial $monitor("a=%b,b=%b,c=%b,x=%b,y=%b,z=%b",a,b,c,x,y,z);
endmodule

Simulation waveform:

Transcript:

Concatenation operators:
Simulation code:
module concat_tb;
reg a;
reg [2:0]b,c;
reg [7:0]x;
initial
begin
a=1'b1;b=3'b100;c=3'b110;
x={1'b0,a,b,c};
#10;
x={{2{a}},b,{2{c}}};
#10;
end
initial $monitor("a=%b,b=%b,c=%b,x=%b",a,b,c,x);
endmodule

Simulation waveform:

Transcript:

Conditional operators:
Simulation code:
module condition_tb;
reg [3:0]a,b,c,y,z;
initial
begin
a=4'b1010;
b=4'b0010;
c=4'b1110;
y=(&c)?a:b;
#10;
z=(c)?a:b;
#10;
$monitor("a=%b,b=%b,c=%b,y=%b,z=%b",a,b,c,y,z);
end
endmodule
Simulation waveform:

Transcript:

Arithmetical operators:
Simulation code:
module ari_tb;
reg [3:0]a,b,c;
integer d,e;
reg [3:0]x,y,z;
integer k,l,m;
initial
begin
a=4'b0010;
b=4'b0011;
c=4'b101x;
d=3;
e=8;
x=a*b;
#10;
y=a+b;
#10;
z=b-a;
#10;
k=c*a;
#10;
l=e/d;
#10;
m=e%d;
#10;
end
initial $monitor("a=%b,b=%b,c=%b,k=%b,l=%b,m=%b",a,b,c,k,l,m);
endmodule

Simulation waveform:

Transcript:
2. Write a Verilog code and testbench for ALU using arithmetic and logical operators

Design code:
module alu(input [7:0]a,b,
input [3:0]command,
input oe,
output [15:0]y);

parameter ADD = 4'b0000, // Add two 8 bit numbers a and b.

INC = 4'b0001, // Increment a by 1.
SUB = 4'b0010, // Subtracts b from a.
DEC = 4'b0011, // Decrement a by 1.
MUL = 4'b0100, // Multiply 4 bit numbers a and b.
DIV = 4'b0101, // Divide a by b.
SHL = 4'b0110, // Shift a to left side by 1 bit.
SHR = 4'b0111, // Shift a to right by 1 bit.
AND = 4'b1000, // Logical AND operation
OR = 4'b1001, // Logical OR operation
INV = 4'b1010, // Logical Negation
NAND = 4'b1011, // Bitwise NAND
NOR = 4'b1100, // Bitwise NOR
XOR = 4'b1101, // Bitwise XOR
XNOR = 4'b1110, // Bitwise XNOR
BUF = 4'b1111; // BUF
reg [15:0]out;
always@(command)
begin
case(command)
ADD:out=a+b;
INC:out=a+1;
SUB:out=a-b;
DEC:out=a-1;
MUL:out=a*b;
DIV:out=a/b;
SHL:out=a<<1;
SHR:out=a>>1;
AND:out=a&b;
OR:out=a|b;
INV:out=~a;
NAND:out=~(a&b);
NOR:out=~(a|b);
XOR:out=a^b;
XNOR:out=a~^b;
BUF:out=a;
default :out=16'h0000;
endcase
end
assign y = (oe) ? out : 16'hzzzz;

endmodule

Simulation code:
module alu_tb;
reg [7:0]a,b;
reg [3:0]command;
reg enable;
wire [15:0]y;
alu DUT(.a(a),.b(b),.command(command),.oe(enable),.y(y));
task initialize;
begin
{a,b,command,enable}=0;
end
endtask
task en_oe(input i);
begin
enable=i;
end
endtask
task inputs(input [7:0]j,k);
begin
a=j;
b=k;
end
endtask
task cmd(input [3:0]l);
begin
command=l;
end
endtask
task delay();
begin
#10;
end
endtask
initial
begin
initialize;
inputs(8'd20,8'd10);
cmd(4'b0101);
delay;
en_oe(1);
inputs(8'd25,8'd17);
cmd(4'b0010);
delay;
en_oe(1);
inputs(8'd20,8'd10);
cmd(4'b0100);
delay;
en_oe(1);
$finish;
end
initial $monitor("a=%b,b=%b,y=%b",a,b,y);
endmodule

Simulation waveform:

Transcript:
Synthesis circuit: