EE 315 Homework 5

Due Thursday, March 10, 2022

Submit your solutions as a pdf file in Canvas.

1. The circuit below contains a 9.1 V zener diode. It is known that when the zener voltage is 9.1 V,
the zener current is 3 mA. The incremental zener resistance is 25 Ω. Find the resistor R if the zener
current is 5 mA.

R
+ IZ
25V VZ
-

2. Design a 7.5 V zener regulator circuit (similar to that in our Ex 3-19) using a 7.5 V zener specified
at 10 mA. The zener has an incremental resistance rZ = 30 Ω and a knee current of 0.5 mA. The
regulator operates from a 10 V supply and delivers a nominal current of 5 mA to the load.
(a) What is the value of R you have chosen?
(b) What is the regulator output voltage when the supply is 10% high? 10% low?
(c) What is the output voltage when both the supply is 10% high and the load is removed?
(d) What is the larges load current that can be delivered while the zener operates at a current no
lower than the knee current while the supply is 10% low? What is the load voltage in this case?
3. An NMOS transistor that is operated with a small vDS is found to exhibit a resistance rDS . By what
factor will rDS change in each of the following situations?
(a) vOV is doubled.
(b) The device is replaced with another fabricated in the same technology but with double the width.
(c) The device is replaced with another fabricated in the same technology but with both the width
and length doubled.
(d) The device is replaced with another fabricated in a more advanced technology for which the oxide
thickness is halved and similarly for W and L (assume µn remains unchanged).
2
4. An NMOS transistor fabricated in a technology for which kn0 = 511 µA/V and Vt = 0.4 V is required
to operate with a small vDS as a variable resistor ranging in value from 250 Ω to 1 kΩ. Specify the
range required for the control voltage vGS and the required transistor width W . It is required to use the
smallest possible device, as limited by the minimum channel length of this technology (Lmin = 0.13 µm)
and the maximum allowed voltage of 1.3 V.
5. Sketch a set of iD –vDS curves (similar to those in Fig 5.4). Let the MOSFET have kn = 10 mA/V2
and Vt = 0.4 V. Sketch and clearly label the graphs for vGS =0.4, 0.6, 0.8, 1.0, and 1.2 V. Let vDS be
in the range 0 to 50 mV. Give the value of rDS obtained for each of the fine values of vGS .
6. An n-channel MOS device in a technology for which oxide thickness is 1.4 nm, minimum channel length
is 65 nm, kn0 = 540 µA/V2 , and Vt = 0.35 V operates in the triode region, with small vDS and with
the gate–source voltage in the range 0 V to +1.0 V. If the device has the minimum channel length,
what must its width be so that the minimum available resistance is 100 Ω?