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  • Placement CTS Lab

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    Deepak Kumar S Nadiger
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    This document contains questions about placement and clock tree synthesis for a design. It asks about the number of scan chains and non-clock nets with high fanout, commands for including optimization cells, enabling I/O optimization, creating placement bounds and blocks, adding clock uncertainty, comparing QOR reports before and after enabling a timing mode, generating PVT and timing reports, identifying clocking structures and relationships, controlling hold violations, enabling CRPR, restricting I/O latency updates, comparing classic and CCD CTS, balancing pin delays, specifying cell libraries for CTS, and reporting the driving cell for a port.

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    Placement_CTS_lab

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    This document contains questions about placement and clock tree synthesis for a design. It asks about the number of scan chains and non-clock nets with high fanout, commands for including optimization cells, enabling I/O optimization, creating placement bounds and blocks, adding clock uncertainty, comparing QOR reports before and after enabling a timing mode, generating PVT and timing reports, identifying clocking structures and relationships, controlling hold violations, enabling CRPR, restricting I/O latency updates, comparing classic and CCD CTS, balancing pin delays, specifying cell libraries for CTS, and reporting the driving cell for a port.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    37 views2 pages

    Placement CTS Lab

    Uploaded by

    Deepak Kumar S Nadiger
    This document contains questions about placement and clock tree synthesis for a design. It asks about the number of scan chains and non-clock nets with high fanout, commands for including optimization cells, enabling I/O optimization, creating placement bounds and blocks, adding clock uncertainty, comparing QOR reports before and after enabling a timing mode, generating PVT and timing reports, identifying clocking structures and relationships, controlling hold violations, enabling CRPR, restricting I/O latency updates, comparing classic and CCD CTS, balancing pin delays, specifying cell libraries for CTS, and reporting the driving cell for a port.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 2

    Placement_CTS_lab

    Sunday, June 6, 2021


    4:19 PM

    Q1-> How many Scan chains are there In your Design?


    Q2-> How many Non clock HFN present with Fanout greater Than 60?
    Q3->What command / option used To include Cells used for optimization?
    Q4->Enable optimization fo INPUT/OUTPUT/INOUT path group using app option.
    Q5-> For Our Design ,It is desirable to have the On-chip clocking (OCC) logic together, and within a
    defined area, Create a Bound to place it near to the Clock ports , after this have a placement run
    separately and see the impact.
    Q6->Write Your own script to create Checker Box pattern of placement Blockages?
    Q7->Write a script to add extra uncertainty Of 50% on top of original uncertainty for SYS_CLK in ss_
    corner, Have a separate Placement run for this.
    Q8-> Compare QOR of Default run with Ques 7.
    Q9->Write a Script to do cell padding in particular area , along with its algorithm?
    Q10-> Which is highest routing layer set for your Design, if not set please Set M8 as Highest Routing
    layer.
    Q11-> Exercise For Understanding add variables ->

    printvar search_path
    printvar REFERENCE_LIBRARY

    Q12-> Report configuration of host option and set it with 8 cpus?


    Q13->If u find unresolved reference and You need to add Library related to that , How will you do?
    Q14-> which Analysis is Enable for test_ss_125c.
    Q15->Write a script to Ensure No clock is propagated Prior to CTS.
    Q16->Generate a QOR report and then enable ZIC timing mode and regenate QOR report and compare
    both reports.
    Q17->Generate a PVT report and find out if any Mishmatch is there For PVT values defined in Each
    corner vs the available in library?
    Which Corner(s) PVT is mismatching, what is mismatch and what is cause of Mishmatch.
    Q18-> How many MASTER CLOCKS,GENERATED CLOCK,VIRTUAL CLOCK are there in design.
    Q19->What is source of SD_DDR_CLK?
    Q20->Which clock group is Mutually exclusive or Asynchronous?
    Q21-> How many Sinks SD_DDR_CLK have?
    Q22-> In CTS flow how to increase effort of Hold optimisation at maximum.
    Q23-> What are ways in which You can control Hold time violations for Scan chain paths in CTS
    stage.Write the Command for same.
    Q24->write a command to enable CRPR during CTS execution.
    Q25-> For this Design, I don’t want I/O latency get updated , except for v_PCI_CLK , Write Script for
    same.

    *****Try to have Two separate Runs For classic CTS and CCD********
    Record Various clcok QOR statistics,

    Number of clock buffers (clock repeaters)

    Clock tree area (Clock repeaters + other clock network cells )


    complete below table for func mode
    Ss_125c GLOBAL SKEW MAX LATENCY

    PHYSICAL DESIGN Page 1


    Ss_125c GLOBAL SKEW MAX LATENCY
    SSY_2x_CLK
    SDRAM_CLK

    Q26-> Generate a Timing report Summary before and after CTS optimisation and fill below Table,

    WNS TNS NVE


    Setup
    Hold

    Q27-> Confirm Design don’t have any congestion and Timing issue post-CTS . If timing issue there try
    fix it by clean by construct.

    Q28-> Write a script to put balancing point for all S0 pin of I_SDRAM_TOP/I_SDRAM_IF/sd_mux_*/S0
    all modes.
    Q29-> WAS to choose list of inverters and Buffers you want to use in CTS.

    Q30-> WAS to specify NBUFFX16_RVT as driving cell for the port ate_clk, Then report this port to
    the same.

    PHYSICAL DESIGN Page 2

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