7 ON TO Low INTRODUCTI a UNIT POWER VLSI DESIGN sia cho PART-A SHORT QUESTIONS WITH SOLUTIONS Q1. What is average power consumption? Ans: Model Papers, ayy In conventional CMOS circuits, average power consumption is the sum of dynamic power constimption, short citcuiy Power Consumption and leakage power consumption. Inthe systems, other than conventional CMOS, there exists anos Current component called static curent consumption. It is expressed as, Prat © 1° C\- Van Sin * Voo reas Megs * Hae) Where, cc —Node transition factor C, —Load capacitance Sa ~ Clock frequency Vy ~ Power supply voltage Jscnceoin ~AveTage short circuit current \ Tege Leakage power dissipation Tage Static current dissipation The dynamic power consum; iption or switching current consumption is the dominating current component in CMOS | circuits. : Q2. Draw CMOS logic gate representing switching power consumption, Ans: . ‘The CMOS gate representing switching power consumption is shown in figure below, Yoo Scanned with CamScannerne switching power consumption is expressed % essed as, i} aot on observing the equation, the average power consu {Be power consumption over soppy voltage, V., an be reduced by reducing, Voltage switching in intemal and output nodes Node transition factor Load capacitance. Draw the circuit diagram of VTCMOS inverter. mst The citeuit diagram of a variable threshold CMOS inverter is as shown in f as shown in figure, AY Veg 2 2M sete moan Bp 4V. inatand-by modo =0.2V Inactive modo 0.8 V In stand-by mode ¥ 0.2V inactive modo in = 0.6 V fn stand-by mode = Ven f OV, ecto mode fan ™ ..2.V in stand-by mode Figure _ 5 Draw the general structure of MTCMOS. ‘ae Modal Pavers 21) The circuit diagram of multiple-threshold CMOS inverter is as shown in figure, Yoo events subthreshold Pakage In stand-by mode 4 oparation wit righ-spo0. ndpere ‘consumplion tow powerUNIT-6 (Introduction to Low Power VLSI Design) as. Ans: What ar interconnects? chips. They provide, clock, input signals, power supply and ground yy Interconnects aré the wires that are used to de: various integrated circuits. There are two types of interconnects, Local imerconnects 2. Global interconnects Q7. Define following parameters, (i) Clock skew (ii) Latency (iii) Clock ron Model Papers, ayy) Clock Skew Clock skew is defined as the maximum difference of the clock arrival to the inputs of flip flops. Lateney Lateney is defined as the maximum delays from the clock source to any flip flop clock input. It also cerfies whether the external clock is properly synchronized with the internal elock of not. (ii) Clock Jitter Its defined as the variation of clock period from one cycle to another cycle. : QB. Whatis the difference between clock skew and clock jitter? An: ‘ovo different locations on the chip, wher: actus ti The difference between clock skew and jitter is, clock shew is the measure of difference between the same cfock edge 5 jitter is the measure of difference between the expected time of the clock edge ar ime point on the chip 2p SPECTRUM AlLaN-ONE JOURNAL FOR ENGINEERING STUDENTS SIA GROUP * Scanned with CamScannerPART-| ESSAY QUESTIONS WITH SOLUTIONS 6.1 INTRODUCTION To DEEP SUBMICRON DIGITAL tc py a9. Give brief description on origin of deep submicron digital Ic. Ans? The IC technology came into existence in betwee \ late 1990s- early 1970s with one metal layer amt 1 yan e with, Using this technology, a designer can integrate some fen to hundreds of yates on ene chip. So, this negate " 0, this inteyratnn ehenfog isteferred as ten mieron technology or Small Scale Integration (SSI) or Medium Seale Imeyration (1451) eu Laterafer 3 years, the size ofthe chip was sealed from I mim x 1 myn 00.7 mm x07 min. This resulted in edn cost per logic function for every generation. This trend was referred as Moore's law. In 1970s, the capacity of chips increased from few hundreds to few thousands of logic gates on one chip. So, this weenole ogy Was referred as Large Scale Integration (LSI). Around 1980, the capacity of chip rose to 1 million transistors, this lead to the revolution in the world of microe ics, So, this integration technology was called Very Large Seale Integration (VLSI), In 1980s, the channel width has led from 10 jum to 5 ym - 1 pm, Channel width is the spacing between two metals ona chip or metal line width. As the width of the channel is decreasing, number of metal layers were increased to enable all required interconnections. Later by mid 1990s, advancement in technology lead to more scaling of channel width to below 1 jam. The ICs that ‘were designed using this width are known as Submieron digital ICs. Further scaling continued to 0.5 jum to 0.35 jum and this is referred as Deep Submicron. These submicrons have some disadvantages like metal interconnection, RC delays, variations in delays, noise, voltage drops in power grid, degradation of metal reliability duc to high currents. Despite of these drawback, scaling still continued to 0.25 jm to 0.18 jm by 2001. This period of sclaling is referred as ‘Very Deep Submigron (VDSM) and Ultra Deep Submicron (UDSM). 6.2 LOW POWER CMOS LOGIC CIRCUITS: OVER VIEW OF POWER CONSUMPTION Q10. What is switching power dissipation? Give an expression for it. Ans: Model Papert, 713) ‘The power consumed or dissipated dl 1g logic transition of output node voltage of CMOS gate is known as switch Power consumption. ze the capacitor at ourput node In CMOS cites, power dias when ery rom he power supply i seit hag the cpa a oa White chasing the capacitor, he vole at ouput ode switches fam 010 Vag The este dean fom the power PRY dissipates as heat and the vollage at output node switches (rom V, 00. OF the total energy one hal is dissipated while MOS transistors and the other half during nMOS transistors. ‘The figure illustrates the switel ng power dissipation in CMOS gate, an re you bt Look for the SIA GROUP LOGO 47/5 on the TITLE COVER before you Duy Scanned with CamScannerUNIT-6 (Introduc network Vout Conn ZCrarcconc *E Cont Figura Jharge the capacitor at output node represents “The energy tha is used to charge the output voltage (from 0 0 V9) and disc the power dissipation/consumption of CMOS cireuit and is given as, Jus freee) ~) — Output node voltage Vy ~ Power supply voltage , ~ Load capacitance On solving equation (1), Va ony ZV o0-= Von Q) = Clock frequency Equation (2) is valid only when the CMOS circuit transits from 0 to V,,, in one clock cycle. Based on certain factors like topology of circuit, logic style and input signal statistics, output voltage may transit before the completion of one clock cycle. ‘Then, average power consumption is expressed as, Pra® yO, Von Su =) Where, lode transition factor which represents the number of transitions per one clock eyele, partial, Then the average power dissipation due to intemal and output node tr n(n Yooh 4) Where, ty, = Node transition factor C,- Parasitic capacitance Even though equation (1) gives the accurate power dissipation in CMOS circu ‘equation (4) is preferred to determine the switching power dissipatioa/eonsumption. SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS 1 is very complex to evaluate. $0. SIA GROUP & Scanned with CamScanner6.6 VLSI DESIGN [JN ITU-KAKINADA\ G11. Explain in detail about short-circuit power dissipation and give an expression for it. : Ans: ‘The current component that transmits from power suppl fom power supply, Vig to ground through nMOS and pMOS transistors wit charging load capacitance at the output is referred as short-circuit current, hen Figure (1) illustrates the CMOS circuit in which nMOS and pMOS transistors are conducting at the same time for short duration and resulting in short circuit current path between power supply voltage and ground, Case When load capacitance is small and rise and fal times of input signal are high. Figure (2) illustrates the VO voltage transitions, short-circuit waveforms in CMOS inverter and overall current drawn cr Figure 2) 4 Took for the SIA GROUP LOGO {fon the TITLE COVER before you buy from Vy ii oruge Scanned with CamScannerUNIT-6 (Introduction to Low Power VLSI Design) on, the ANTON transistor cond i attage reaches Vy ing this transition, the pMOS transistor is ON until input volts ; ane window between the wo transistors to switel| ON. Since input yoriage 2 pes ia nMtOS transistor. The voltage V9, OF PMOS transistor ame process goes with falls, by asa The same proeess goes with falling wmput voltae. SO, The magi. fo cond input voltage, 1 rising input tr Value. It ean be observed that, there ‘output voltage falls and the load capa ‘equals to zero and allows the transis “ of the short cirouit current is almost same fir rising and falling it citor at output and the current that is requir ige capacitor at output and the curr FeAwied fo svg ined to chy The average of the current that is Fe power consumption gives the overall current that is draw Irom Vi Whe heh Vem Wag LM hae 2 short-circuit eurrent drawn fom power supply yoy, = x then avera expressed as, (i) Lyglshort = cireuit) = [And the average short-circuit power dissipation is expressed as, 1 Op Pag (short circuit) = 5 kt Voy") From equation (2) it is clear that, the deerease in input voltage transitions intur decreases the shor. sumption, Case-2 When load capacitance is large and rise and fall times are low. Figure (3) illustrates the /O voltage transitions, short-circuit current low in CMOS inverter and overall curent dev from V, ‘9 — 29 — aed put s« wee venpe : a0 3 20 0 oo ° 1010" 2004 ‘3010* ‘010% ope cunentt9 cage op Decupteapactnes Sa aeeee aar E ° 110 2010¢ ao10* 4010" so10* LS | 200° 3010" wwe s000" Tens (9) 2 Figure 3) $) SPECTRUM ALLAN-ONE JOURNAL FOR ENGINEERING STUDENTS. SIA nov? & Scanned with CamScannerig rising input voltage, output vol During age retaing fr the input attains its final value, Dy fe ave uring this tran sit doth n y wi drain and source As ay ‘i ° 2 the Vp, between PProximately, equal to 2. obs sre switched ON but nMOS en + durin eats 8 filling “agar does not conduct because Vos is almost zero, From figure (3) it can be observed that, soris in saturation state during rise and fa the current H input vor ition, of input transi Supplied to charge ad ta Pacitance BE transition, eames outof str B ate jst Therefore, the short circuit power Reverse diode leakage current 2 Subthreshold current leakage, Reverse Diode Leakage Current Figure (1) illustrates the flow of reverse Jeakage current in high input CMOS inverter, Figure (1) 0 Few, when CMos in veen gutPlt Voltage drops ve Well resulting S10 p-type substeat ‘sagt the Mo Mage ch arsine 8 or tums ON, pMOS wes lage AMOS tras ms ON PN ae Fa rere is given with high input voltage, nMOS ty there exis a ees vo. Even though the pMOS transistor is in OFF state, er ea at pMOS in diode leakage via drain terminal. The reverse biasing '€ causes reverse leakage current, Pavol NOS inverter is giv 1 ang 588 Shares trom o i Pe substrate resul en with Low iny © VDD. Even thoi ing in nMOS transistor eet e voltg¢. Viv 3 ON, put voltage, then pMOS transistor tum | | off ant | es there exists a Teves tigh NMOS transistor isin OFF state, there Verse leakage current, w | “Sete leakaye current at Pn-junction is given as, jou buy 5 F OVER before y' a Seek forthe Stay GROUP bane AR on tho Scanned with CamScanner£3 LS (Introduction to Low Power VLSI Design) ———e—e« == 4 —Junction area J, ~ Reverse saturation current density Reverse bias voltage across the junction " * and it inereases with increase in tempering, iration current density is 1-SpA/m* an fore, the power dian ; 4 Feverse leakage is prevalent in those chips built with millions of trans | 2. Subthreshold Current Fusion of rs ftom source to drain. and vice-vers The subthreshold current leakage is due to the diffusion of carriers fr et a durin 1e subthres! 2 inversion as shown in figure (2), Figure (2) The MOS transistor acts as a bi on gate voltage ic. the current varies Very less and equals to threshold voltage, t ge, then the magnitude of with the magnitude of switching pow: | a ipolar device in subthreshold regi | fe dissipation. 3° curent, subthreshold curen also exists inthe systems operatin any switching events, ‘The subthreshold current is expressed as, Mn, sgh ’ Where, Iplsubthreshold) = D, ~ Electron diffusion coefficient ~ Subthreshold channel depth | L,— Length of barrier region 6, ~ Reference potential — Channel width Therefore, these subthreshold Currents can be reduced or restricte Such that, when input is very low or lo aa | ed by eliminating extremely low threshold °° sie Zero, then the patety. SOurce voltage, V.., of AMOS transistor will be less 2°” | if he inputs very high or logic 1 then V, of pMOS teansstor goes below [7] tf | te ai SPECTRA @LLAN-ONE JOURNAL FOR ENGINEERING StuDeNTs sig @rolP” Mm Scanned with CamScannera” NUTHR OUSH Itage sali Vo the influence of vo ng on po a bn explain er dissipation an, e ¢ of power supply vollage scaling on power se iluene : and delay ca -MOS circuits, beob, ppspessions oF P= eM fromthe oy ve — | tn 0-H) ‘ei 5, Wop" ew Yoo" x Teg 1 GS rp (2 or, ao + | Moo) Sut Wop" Hew Woot Fag ry ions, the scaling or decrease in > From the equations, ease in power supply voltage r 2 econsumption ut inreases the propagation delay, Bs reduces the dynamic pone din the influence of voltage seal Figure (1) represents t ge sealing on power dissipation and aa Propagation dey ri \_ | le = | | | Power Sub VeR8V sn M1 Figure (1) Since the speed of the circuit also depends on power supply, it also affects the power dissipsson On chev=s Sstcing power dissipation equation, it gives an assumption that, the switching frequency or ranston fst TAS SSS the CMOS circuit is operated continuously at its highest frequency and allowable propagation delay, 3ea 56 ‘ng with power supply reduces because propagation delay increases. i ; : sod by doses 7 In addition to power supply voltage, F'n. the increased propagation delay can also bs res stage, reased p cy foc vasoas og, but, cannot be reduced to the value of Vp Figure (2) illustrates the popagaon dees Mo ) v 208 . 120 109 F oay 0 ony oay Normalized Delay co i © } 20 oo 2 nd 10 20 30 ° power Supe versa# V 00 Figuro (2) zoo ye = nh qitue COVER se e Scanned with CamScannerUNIT-6 (Introduction to Low Power VLSI Design) From figure, the sealing of threshond value, V, from OS to 0.2 reduces the delay value by factor of reduction in delay, scaling of threshold voltage leads to small noise margins and subvhreshold current circuits, Q14, Explain briefly about Variable Threshold CMOS (VTCMOS) circuits. Ans: ‘Variable Threshold CMOS (VTCMOS) circuits are designed to overcome the drawhacks of low threshold voltage yalygg circuits such as subthreshold leakage and power dissipation. Fi control circuit. ze illustrates the variable threshold CMOS with substrate big av 2:V inactive mode Yop "4. 4.V instand-by mode O.2V Mectve mode 08 V Inetendby mode 0.2V hactve mode 0.6 V hi stand-by modo Figure Ina conventional CMOS circuit, all substrate terminals of nMOS transistors are interfaced with ground, whereas thal of pMOS transistors with power supply voltage, I,,- For a MOS transistor, the threshold voltage depends on substrate volta. Vis In this method, the transistors are developed with very less threshold voltages and substrate voltage of these transistors ae produced using substrate bias control circuit. If this inverter is operating in active mode, then M,, of aMOS transistor is V,, = 0 and of pMOS transistor is I, =! this mode, the transistors are not influenced by back-gate effect and operates at tow power supply and threshold voltages wil! high switching speed and low power dissipation. If the inverter is operating in stand-by mode, then substrate bias control circuit provides low V,, for nMOS and high Vss for pMOS. In this mode, transistors are influenced by back-gate effect resull .V,,and V5, Due these high threshold voltages, the subthreshold leakage current and power dissipation decreases consequently 1g in high threshold volt Using VTCMOS approach, the threshold voltages can be regulated automatically. This technique is referred 35S ‘Adjusting Threshold Voltage Scheme (SATS). ‘Therefore, the VICMOS technique is efficient in designing CMOS circuits with reduced subthreshold current lal and adjustable threshold values in the range of 1’,.,~ low Gis. Explain in detail about Multiple Threshold CMOS (MTCMOS) circuits with necessary circuit dia Ans: Multiple Threshold CMOS (MTCMOS) is the technique used to decrease the subthreshold current leakages ithe ire rating in stand-by mode. This technique uses two transistors with two distinet threshold voltages as shown in Big é SIA GROUP ae Scanned with CamScanner ope SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTSCMOS Logie bigh-spseq wit operat ith tow Vy fow power conan wth Provents subinreshoig | Yeakage In stand-by moda Figure tft CMOS logic is operating in active mode, then the transistors with high threshold voltage tuns ON ante chow threshold voltage operates with very less power dissipation and propagation delay. \Etbe CMOS logic is operating in stand-by mode, then the transistors with high threshold voltage tuns OFF ae “ssuith low threshold voltage tums ON and the path for condueting subthreshold curent leakages orignal cuits) are cut off. Teadvanage of MTCMOS is it is very simple to use and apply when compazed to VICMOS Dats of 4 «inthis technique, all the stand-by transistors connected in series increases the trl ccuk = 1 parasitic capacitance and delay in the circuit. 4 STION OF SWITCH \4 ESTIMATION AND OPTIMISATION OF SWITCHING ACTIVITY, REDUC ING CAPACITANCE * taplain briefly about the estimation of switching activity. sre ») rel wander 056 jrcuit from one lie AN Treswitching activity or the transition of output node vols es ovicig sti eo ctvity. It is denoted with node transition factor, Itis a8 mre cieut en iit ' , CMOS cits! ».itlishing power dissipation, the power consumption ‘or dissipation o so “chin turn depends on Boolean function of the logic Bt: higy ies 7 "eas to determine the power consuming ouput probate F ‘ape P represents the probability of occurrence of logic asi ; wie ‘then the probability of occurrence of power consuming *Pand ye ouput or a0 4 atthe om! o Genera ing transition “nol the probability of occurrence of power consuminl tran ‘tnd is given as, ai 2" } ‘ eae {ign iustates the probability of power const and NOR gates, barnsel 7 TITLE <1 ok Tor ne SIA GROUP Loco 0" —_ IPT T UA meen ED ME: ren en AIZEN Scanned with CamScannerUNIT-6 (Introduction to Low Power VLSI ESI ae 0.20 078 Transion probability for XOR/KNOR gata 0.20 0.15 0.10 Transition probability for NAND/NOR gate 0.05 0.00 Number of Inputs Figure (1) Example diagram of a multilevel circuit, NOR gate. Figure (2) represents the state trans A x 3/4 = O16 9/4 x 1/4 = 316 14 x 14 = 116 WA x34 = 18 Figure (2) Case-t O and | and four outputs that are equally Hie Ifa NOR gate has two independent and uniformly distributed inputs to occur; 00, 01,10 and 11. Then, . The probability of occurrence of logic 0, P= 3/4 ‘The probability of occurrence of logie 1, P, = 1/4 ‘The probability of occurrence of power consuming transition at the output of NOR gate is, 3403 a4" 16 Case-2 Ifa NOR gate has two inputs which are independent and not uniformly distributed, then itis not ‘ceurrence of logie 0 and 1 with same probabilities, Then, the probability of power consuming output transition fof input probability distributions. a SPECTRUM ALLIN-ONE JOURNAL FOR ENGINEERING STUDENTS Sia GROUP aA 1 ame - a TS Scanned with CamScannerJ se probability of o cobsbily ofoccurrence of Togic | at input = 7, ‘the P Them, the probability sccurrence of logic at input A= P, of oceurrence of logic 1 at output is, p.=(1-P, VP ip) the probability of occurrence of power consuming P From equation (2). Pi. = PoP a= Pp UHC) = Py =P) =P) Wansition at ony 8 given as, sherefore, equation (3) represents the probability of power consuming output transition . a Function of input pba ns and this distribution is shown in figure (3), Put rhshiy seston Figure (3) i luate the switching activity Thetefore, from equation (3) it can be observed that, itis litte complex to evaluate th na : ols to esti: it volving sequential components, feedback loops.cte. So, a designer prefers CAD 1 a a a 5 in them briefly. ”. Vihat are the methods used for optimization of switching activity? Explain the Ange , circuit re The various methods that are used to optimize or reduce the switching activity ina CMOS ! Algorithmic optimization 2. Glith reduction 3. Gated clock sipnals “eorithane Optimization es ny AMePrithmie ; depends une eemization is one of the technique used to reduce switching ¢ sion. 1 a the applications and characteristics of the data including 4 sot veneral nae Lew Methods such as Digital ing (DSP) which t “Hem PO imizes switche Pury ree search algorithm instead of full search algort™ 1 and adait 5 a Scanned with CamScanner. Aes (Introduction to Low Power VLSI Design) [by changing the data representation. Switching ves can be o mized greatly while representing a signed data, t UNr 2. Gliteh Reduetion 1 transitions caused due to the carry of propagation delays from one block to the other blog, Glitches are the fast signal tra ea ‘These glitches results in critical races or dynamic hazards. Ss 1a hazards. If ing it 1 the same time, it results in dynamic ae ut signals ofa gate does not transit from ground to V, at ears nals ron purely renin paral azards. I the input signals transit rom ground to Vio tthe canoe ‘occur in the output. ‘The main reason behind the occurrence of hazards is improper balance in the lengths of paths between gate ina neta This leads to the improper timing or propagation delays in transmitting signals between logic blocks. 3.2 Gated Clock Signals Using of gated clock signals or conditional clock signals is another way of reducing switching activi 7 the network. fy a network, ifa particular logic block is not used for a clock cycle, then disabling the clock signal for that particular block reduces the switching activity. In order to design a clock gating strategy for a circuit, the flow of signals and interconnections among the blocks and their operations have to be analysed carefully. Q18. What are the various techniques used to reduce the switched capacitance or parasitic capacitance in a circuit? Explain briefly. Ans: Switched capacitance or parasitic capacitance is one of the main factor for power dissipation in a circuit. This capacitane can be optimized using various techniques at various levels, They are, 1, System level 2. Circuit level and 3. Mask level System Level ‘The technique used at sy: meee tem level to reduce parasitic capacitance is restricting the usage of shared resources ant Example Figure (1) illustrates v; rious modules using a single bus to access CPU resources, Figure (1) Scanned with CamScanner; eh Fale bus is shared among various modules, a large bus cap 7 pai ge ofsame bus by al th drivers and receivers 0 parstc capacitance ofthe bus. a cert ase the bus, high amount of power is consume , itched capacitance is optimized by dividing the single © drive this trp ca pc 0508 tong bus ino smatt meg Ultiple buses 3s) mal i Somning Ste) Cou (o) Figure (2) ‘sse multiple small buses regulate the data transmission among various modules and also rede the sicher “hile acessing the bus. Creuit Level a cietorst ans ows The: i to desig tn “chnique used at circuit level to reduce parasitic capacitance is to change the logic syle onal ‘tthe main reasons for the increase in load capacitance in the circuit is the usage of large nt of Ore metho . transfer gates in the pla Bn pn L® milmize this load capacitance is to employ pass-tansistor loge oF though ‘ "th itreduces the load capacitance, it has several limitations, ech 6 », ites in accepnble — wing capail Bates require inverters at the output in order to generate output driving © ® ation J Usage of inver a ; . ipower ds ers results in increase of total area, propagation delay and Ps mre ro ‘ iy Ses dua eal Frail logic to g mplemer ol signals which i ‘Wansistors gic to generate complementary control sigt tum requires ys ; ined ae iaalltts disady, aa 8M the ‘nlazes overcome the advantage of pass-tranistor. SO, QuiRed pas | | vs a trade off | ‘Transistor has to be chosen carefully. bak yi vet ‘ 05 ed Nig - the dimensions me os a small g ths level to reduce parasitic capacitance is minimizing 4, <0 hat sacd en Parasitic capaci ita! ion, ‘ots in a logic circuit reduce the power consumph nd dyna PS ust be maintained between power consumption 9 Sor VER * for the Sta, GROUP Loco 4% on the TITLE CO" Scanned with CamScanner Stfore, a tade-oftINTERCONNECT DESIGN Q19. Describe briefly about interconnects. Ans: cts are the wires that are used to design chips. They provide, clock nP\t signals_power supply and ground to Interconnes sare two types of interconnects, various integrated circuits. There 1. Local interconnects 2. Global interconnects 1. Local Interconnects is in MOS technology and emitter, source and drain terminal titanium nitride (TiN) pretends ine, silicide, and high temperatures mnnects which connect gate, ‘hnology. In MOS, metals ike poly crystal II, highly resistive, and can withs ‘These are the basic level of interco base and collector terminals in bipolar tec! as local interconnects. These interconnects are smal 2. Global Interconnects sce are long and not highly resistant connects usually designed using Aluminium. The { various components and parts of a chip. ic layer in MOS technology: “These are the next level of Focal inte 4s local interconnects because they connec strates interconnects, vias, contacts isolated using diclectri igure illu Intermetal Dielectric —Fint Level ic Dielectric Figure ric layer separate this layer and highly resistive dielect ja ope connects and active the active region and interconnects V wntact is created in between From the figure, the contacts interface inte and local interconnects are also interfaced using vias, etive layer and global interconnects. An electrical 6 dielectric region and simultaneously global 6.6 POWER GRID AND CLOCK DESIGN power distribution design. ings in the What is power and describe briefly about . por. 78! 20. Model Pa wer supply, V,,,and grounds Vos O switching events. Ans: “The tenm power refers to power and ground distribution syste which includes po} Id be constant all over the chip, bu it varies along withthe s erally, the power value shou overt a yw and off-chip issues like de-de <¢ 1n is not simple as it involves many on-chip gate connections. In order to desizn & perfest PO" 4 Designing a power distibutios printed circuit boards, power planes. packages, sockets, power pins and em designers, thermal di poard designers and chip designers have to interact ization. g lobal optimizat Scanned with CamScannerrs which are responsible for the compen exity cot | Fabrication of are number of transistors on chip tmtereonnect nature of RIC operating frequency 7 1. Regirement of high-speed circuit gateof-art-esign the highest operating frequen ote has scaled to below 1.2 V. Vi FT result i the failure of the system, inte’ renccepable voltage noise is, + 10% x(V,,- Gnd), Therefore, to + sartstobe regulate depending upon the required current le . ese, 22,7 fractional noise budzet) Control the vaiations inte “ls The target impedance reused eee inde ea, be pe 3. Explain briefly about measurement of clock jitter. a west i Basically, there are two ways to determine clock jitter. They ar, (cto | i Inthis method, a clock signal (fitst clock signal) that 1s uniformly spaced in a given time perio Tita js | coleedas a reference. Then another clock signal (second clock signal) with jitters taken and is eps ae menzet ae ‘size points in time where jitter-free clock edges take place ic. 7, is compared with T.,, and T, wh 27, rds0v0 Therefore, absolute jitter is determined using T_- 7... (cot imei eerie ih Inthis method, the errors in the edge locations are ignored upto the last clock epee and Be RO Ty the lst clock edge. This represents the third clock signal which consists of same ta in rh “ss period of the clock is compared with the expected time period. This ree ‘tle in on-chip applications Figute below represents the jitter measurement in 80 methods. | | ais - z i q é a7) or ea pepe pees ae Figure Scanned with CamScanner