UNIT 8086 ARCHITECTURE SIA GROUP PART-A SHORT QUESTIONS WITH SOLUTIONS at. What is microprocessor? State its importance. Ans: Modo! Paper, aia) Microprocessor is a digital electronic Cireuit (IC). It contains a CPU, which include: connected to the CPU as shown in figure componerit with miniaturized transistors on a jingle semiconductor Integrate ‘ALU, register arrays and control circuits, Memory and VO ports are externally below. | —+fricw] Figure Importance: Microprocessor is a device, which include following features to make it as more important in electronic industry 1. Limited set of on-chip memory locations referred as registers to carry information. 2. Easily understand a fixed set of basic commands. 3.__ Generate signals to control extemal devices, Q2. List the segment registers of 8086. ‘The various registers of bus interface unit of 8086 processor are as mentioned below, 1, Queue (stores 6-byte instruction) Cod 2. Segment (CS) register 3. Data Segment (DS) register 4, Extra Segment (ES) register 5. Stack segment (SS) register 6. __ Instruction pointer (IP). 3. _List the flags of 8086 microprocessor. Ans: ‘The various flags available in 8086 a 1, Status flag (i) Carry Nag e divided into two groups, They are, ii) Auxiliary carry Mag CONE JOURNAL FOR ENGINEERING StaDEHTS ——— as gs SPECTRUM ALL 2 __+F Scanned with CamScannerMi (iv) Zero flag () Sign fag (vi) Overflow flag 3, Control flags (Interrupt flag (ii) Direction fag (ii) Trap flag, ee {white the function of ALE and MNINX pins of 3088. os Model Papers, atte) ue his an output pin used as an address latch enable gal During first clock cycle of machine cycle, it goes high siltches the lower 8-bit address into memory or external A win Thispin indicates whether the processor is operating in ‘eniimum mode or maximum mode. X = 1, indicates minimum mode M\/SIX_= 0, indicates maximum mode, ‘& Write the purpose of INTR pin of 8086. Jess Interrupt request (INTR) is a level triggered input, “Sch dctermines the availability of a request. This is done by ‘TRstich is being sampled atthe end of every instruction ‘Rstich is being sampled atthe end of every instruction, % What is interrupt? Classify the interrupts of tone, fone ‘europe Jom the signals that break Secgltictoprocessors,imerrups are owen af an water te sont ‘aa? program called Interupt Service Routine ISI) sggiterthe execution of ISR, the contol is retume ain program which was being halted. “ation of interrupts in 8086 gag! interrupts of 8086 can be classified into three ways Shown in figure A ICROPI ROCESSORS AND MICROCONTROLLERS [JNTU-KAKINADAI Interrupts Tet Hardware Veetored and Maskable and ‘and sofware non-vectored -non-maskable interrupts interrupts interrupts Figura Q7. State the need for jiterrupts. An: In microprocessors, the interrupts are needed due to the following reasons, 1 2 To execute the desired program module. To interface the microprocessor with external peri- pheral devices. Define hardware and software interrupts. Hardware Interrupts ‘The interrupts which are initiated by applying proper signals to INTR and NMI pins of 8086 are called as hardware interrupts. When IF (Interrupt Flag) is 1 the hardware interrupts ‘are unmasked/enabled, When IF is 0, the hardware interrupts are masked/disabled. Software Interrupts ‘The imterrupts which are initiated by *INT n’ instruction are called as software interrupts. All these interrupts are non- maskable interrupts. Q9. Define Bus. Ans: Bus isa set of conducting lines that caries data, address and control signals to the system components, Q10. Define machine cycl Ans: ‘The minimum time period required to complete an instruction or part of a complex instruction is called machine The eyele or time required by the processor to perform, one read of write transaction among the CPU and the external memory is referred as bus eye. The various bus eycles of $086 microprocessor are, Memory read eycle Memory write eycle VO read cycle VO write eyele 5." “Imerrupt acknowledge cycle. Look for the SLA GROUP LOGO GY on the TITLE COVER ‘before you buy Scanned with CamScanner1g UNIT-1 (8086 Architecture) PART-B ESSAY QUESTIONS WIT! 4.9 tans PeATeRED, Pitt DAORAMMESCRIPTION, 8006 M Q12. What are the important features of 8086. Ans: ‘The important features of 8086 an ‘iH SOLUTIONS CROPROCESSOR FAMILY Nisa 16-bit processor, 1 2 Iesarithmetical logical mit and inte cers works with 16-bit inary words. 3 or ¥-bits of data to a memory (oF) port at a time. Whas a 16-bit data burs, which reads or writes I 4. Whasa 20-bit address bus, S. Its frequency range is 6-10 ME. Wt can work only on fixed-point arithmetic operat m mode. At works ina multiprocessor environment, Hinceds +5 V of power supply. 10, has two units ie. BHU and 6 7. Weperates in two modes, mi 8. 8 11. Muses a 40-pin dual-in-line package. Q13. Draw the pin @lagram of 8086 processor and describe the function of each pin. Amst ‘Model Papers, a2(8) ‘CPU. The pin diagram of an 8086 microprocessor is as shown in figure ‘The 8086 is 40 pin microprocessor with a 16- below, 1 —[ ow vec |— 40 i AD, = 9 x —} an, AWS 8 4] ap, Ai, = 37 5 lap, 16 6) Ady AWS, |= 38 7 —1 an, RowOCCRU) ‘anys, 34 * — ap, ang |= 33 9 —| Ab, xo a2 wo —] av, wyvate|— yy | an, woven, | 39 Reapy |~ 22 user }—21 $$. ot} Figare: Pin Diogram of goag SPECTRUM @LLIP-ONE pouRTIAL FOR ENGINEERING STUDENTS , ————= ‘Sia GRour a Scanned with CamScanner" ® m a MICROPROCESSORS AND MICROCONTROLLELS LAU KARUN The deset iven below, GND: Ground pin, for internal circuitry, 2-16 AD,," AD, 9ADiy + Address and data lines. These are 16 time ~ multiplexed fines. Here, the data is available on the data bus during time 7, 7,, 7_ and 7,. The address is available ow the address lines du [NMI (Non-Maskable Interrupt) (input pin): Non-maskable interrupt i also. interrupt. The NMI cannot be disabled (masked) by any program instructions. time 7), allededge triggered input. W causes lype-2 The common use of NMI is to save program data in case of system power fa res. When power returns, all the saved data is restored into RAM, INTR: Interrupt request is a level triggered input, It determines the availability of INTR which is being sampled at the end of every instruction. request. This is done by the (LK: Clock input provides the tuning for CPU and all activities of bus contro. For different versions of 8086, frequency ranges from 5 MHz.to 10 MHz. GND: Ground pin. RESET: The processor terminates from current instruction and start execution from FFFFO H, when an active high input is given to it. RESET pin is internally synchronized and remains active for atleast four clock cycles. 8086 performs the following steps, (i) Flags register is reset to 0000 H, so IF is also zero, so INT disabled. (i) Instruction pointer is reset to 0000 H. (ii) Three segment registers DS, ES, SS reset to 0000 H. (iv) Only CS éets to FFFF H. () _Allthe six registers of instruction queue are cleared. ‘After RESET, 8086 executes program starting from physical address FFFFO UL pa= (FFFF [0 ea= [0000 FFFFOH Normally at this address FFFFO H, inter-segment direct jump instruction of system program. Jruction is stored whose target instruction is the first READY: After completion of data transfer fom slow devices or memory, the acknowledgement isnt as ready to 886, Thisis an active high signal. FEST: 1° TEST = 1, then 8086 entersan idle state conuition. In this state, the 8086 with extemal hardware, as external hardware luni his pin is made low. does nothing, ke state is used to synchronize slower than the processor. The 8086 enters normal condition in24 (Q8) and Pin.2$ (5) Pins 24 and 25 together eves the status ofthe instruction queue, The combinations of QS, and QS, are shown in table (I) roa banat Gene ‘o0,the TITLE COVER bafore you buy, ., ,. Scanned with CamScanneras, | as, caning 0 0 ‘No operation 9 1 | First byte of opcode from queue 1 (0 | Queue iseleared , 1 1 ‘Neat byte of opeode from queue. Table (1): Instruction Queue Status Bits Pin.26 (S,), Pin.27 (G1), Pin.28 (,): These pins generate the status signals for the 8288 bus controller. The controller in tum generates the control signals for memory or VO access. The logical combinations of these pins are shown in table (2), 5 s | Meaning ° 0 0, | Interrupt acknowledge ° ° 1 | Data from 1/0 read port ° 1 © [Data is written to the VO port 0 Halt 1 Opeode is fetched . 1 Read from memory ‘ 1 Write to memory a 1 Passive state status Signals 29. LOCK (Output and Tri-state): An instruction with a LOCK prefix is being executed without sharing the bus with another master. LOCK affects no flags. If LOCK =0, then the bus is locked, so that no system can share the bus. If LOCK = 1, thén the bus isnot locked, so that any system can share the bus, Pin.30 (RQ/GT,) and Pin31 (RQ/GT)): When other processors request the CPU,to release the local bus at the end of current bus cycle, either of the pins 30 and pin 31 is used. The signal RQ/GT, on pin.31 has lesser priority than the RO/GTy . 32, D+ It refers to read signal. It is an active low signal. When RD = 0, the CPU performs read operation. During bold acknowledge, the read signal remains in tri-state. ' 33. MN/MX:: This pin indicates whether the processor is operating in the minimum mode or maximum mode. MN = I, indicates minimum mode MX = 0, indicates maximum mode. 34. BHEIS, | A, Indication 0 0 | Whole word Upper byte from or to odd address Lower byte from or to even address None Table (3: Bus High Enable and A, eee SPECTRUM ALLAN-ONE JOURNAL FOR ENGINEERING StuDeNTs ">. eoup Scanned with CamScanner16 MICROPROCESSORS AND MICROCONTROLLERS [JNTU-KAKINADAI BHE pin is made low during data wansfer over D,, =D, Is used to determine chip selects of od adress memory Bank aepearheras: BITE is low during 7, for read, write and interrupt acknowledge cyeles whenever a byte isto be transferred on saderbste oF data bus, The status information is available during the states 7,7, and T,-The signal is i ; old. It is low during 7, fo ping bold Itis Tow during 7, forthe fist pulse ofthe interrupt acknowledge cycle. Tow and tri-stated 3s Au/Ss) These represents address/status lines, These are time rultiplexed. The status lines §, and §, indicate the x AwSs |_memory segments, These lines are low during VO gs, { oPerations whereas high for memory operations. The status information is available on these for T,, TT. aI, Ty, we AWSy The operation ofS, and S, status lines is shown in table (4), s, |s Operation 0 0 Attenuate data segment 1 0 Stack segment . 0 1 ‘Code segmentinone = 1 Data segment Table (8: Status Signals 4. VCC: This is the power supply pin (+ 5 V) to operate intemal circuitry, O14, Write a brief note on the overview of 8086 microprocessor family. Ans: ‘Overview of 8086 Microprocessor Family i as a CPU in microcomputer. It consists of arithmetic logie unit, Intel juced a 16-bit 8086 microprocessor to be used 8 sof bite ar 16 bite to memory or ports simultaneously using a 20-bit address bus, 8086 addresses 2° or 1, 048,576 memory lneations of each, byte-wide location. : : Based on the memory address location that stre bit words it decides the number of bus operations. Example Fora 16-bit word. dis at odd addres, then 8086 requires one bus operation to rea frst byte and anther bus Ifthe first byte of the wo rhe fat byte ofthe word is at even address then, S086 requires only one bus ‘pertion wo read second byte. On the other hand, ‘eration to read complete word. reo option bit data bus. Italways require two read operations for every 16-bit jmilar to 8086 except that it has a 8-it data ‘ ration ‘erin conto one ead orenton +086. It is used as CPU in IBM PC/XT, and several compatible PC's. vanced versions of 8086 and 8088 respectively, In aditon toa 16-bit CPU, they have ie an 08 ‘Oprammable peripheral devices. 4088 cannot execute 80186 and 80188 instructions. vita is ‘ed version of 8086 and is used as CPU in a multiuser or multitasking micro computer, "sem program from getting destroyed by different user's Programs ‘The intel 32-bit 80386 proces iis used in multi user and multi tasking environments. “ss and general purpose registers of 32-bi Look for the SIA GROUP Loco nthe TITLE COVER. before you buy Scanned with CamScanner(8086 Architecture) cessor (80387) integrated into CPU chip. Intel 8048 ivanced versi -32 architecture with floating point PF Intel 80486 is advanced version of IA-32 architecture with floating ee SSE 2.) per tread echn0gy, 59m ‘The other versions are pentium processors with multimedia (MMX, S' power saving modes etc, ECUTION UNIT 4.2. 2086 INTERNAL ARCHITECTURE, BUS INTERFACING UNIT, EX‘ Q15. Draw and explain the architecture of 8086 with neat diagram. (or) Explain the internal hardware architecture of 8086 microprocessor with neat diagram. : (or Explain the architecture of Intel 8086 with the help of a block diagram. ‘Model Papers, a2(s) Ans ‘The 8086 is a 16-bit microprocessor with 16-bit intemal and external data bus. It ean access 2 = 1 MB of memory with 20 address lines. ‘The functional block diagram of 8086 microprocessor is as shown in the figure below. ‘Memory interface [Control unit Operands “16 Flags Te ‘Block Diagram of 8086 Microprocessor ‘The architecture of 8086 is divided into two independent functional pars, the Bus Unit (EU) to speed up execution, Interface Unit (BIU) and Execution Bus Interface Unit (BIU): The bus interface unit interfaces $086 with the extemal worl. Itha ae gene the mart fom mene aa en nse da aster ‘and output devi t means all external operations are performed by BIU, ‘ice, and writes data to memory ECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS . SIA GRouP Scanned with CamScannerMICROPRO. Fa tonctional parts of BIU are, \CESSORS AND MICROCONTROLLERS [JNTU-KAKINADA] je: To speed-up the = : Ges chee ae ee ‘execution, the BIU fetches six instructions byte ahead of time from memory and stores in , * Since EU and BIU are independent, the BIU fetches additional instruction, while EU codes ad executes previously fetched instruction cecution unit reads the ir . The exe : - 1 s the instruction from the queue when it is ready for its next instruction. Fetching of the next ipsretion is overlapped with the execution of current instruction, This is called “pipelinina™ egment pene 8086 BIU gives 20-bit address for accessing (2""= IMB) the memory. The four segment resisters oh wih memory are used to hold the upper 16-bit addresses of memory segments. The four segment related registers are, 1, Data Segment (DS) register 2, Code Segment (CS) register 4,__ Extra Segment (ES) register 4, Stack Segment (SS) register Instruction Pointer (IP): The IP is updated by BIU so that it contains the offset (distance in byte from thenext instruction. i.e. IP points to the next instruction to be fetched from code segment. ‘be fetched to bus interface unit, and Iocations. This address is then base address) of twetion Unit (EU): The execution unit gives the information of the instruction oF data 10 aexesand executes the instruction. The execution unit provides effective addresses of memory ‘Holto base address provided by segment registers in bus interface unit ‘he functional parts of execution unit are contol system and instruction decoder. These include, 1. Arithmetic and logie unit 2, Flag registers 3. General purpose registers 4. Stack pointer 5. Pointer and index registers. Since, the two operations that is fetching instruction from memoly by bus interface unit and execution of instruction by ‘ection unit is performed simultaneously, itis called parallel processing. Discuss the general functions of all general Purpose registers of 8086. Explain the special function of each register and instruction support for these functions. Ans: The 8086 microprocessor has four 16-bit general purpose BI 8 follows, 1. AX register 2 BX register 3. CX register 4. DX register: AX Register: This register consists rive &-bit registers AL and AH, which can be combined together and used as 16-bit ‘register. AL contains the lower oder byte of tne word and 'AH contains the higher order byte of the word, This register is enerally used for data storage- Example: MOV AL, 53 / It stores immediate data 53H into AL register. MOV AX, 0301 ; data 03 H into AH register. Itstores immediate ! Look for the SIA “GROUP LOGO ‘on the TITLE COVER before you buy . . - till Scanned with CamScanner2 3. Special functions ofthe general purpose registers: The special functions performed By the in the table below. Giz, Describe in detall about the register organization of 8026 microprocessor. Register rand used asa 16. (8086 Architecture) BX Register: This register consists of bit register. BL contains the lower order byte and BH contains 4 Tan be combined 103 the word. This register is generally Gers BLand BH, ne higher order by used for data storage. Example: MOV BL, 72H MOV BX, 0625 H anbe combined together and used as a 16. ist 1d CH, which & registers CL an Tiss er order byte of the wort CX Register: This register consists of two 8-bitr bit register. CL contains the lower order byte and CH used for data storage. is generally contains the high Example: MOV CL, 12 H MOV CX, 1204 1 and DH, which ean be combined together and used asa DX Register: This register consists of two 8-bit registers DI higher order byte of th 16-bit régister. DL contains lower order byte and DH contains used for data storage. : .e word, This register is generally Example: MOV DL, 03H MOV DX, 6234 general purpose registers are shown Name of the register Special function ~ Supported instruction ithmetic | ADD AX, 16-bit d bit accumulator ‘Stores the 16-bit result of certain AX 1 and logic operations: This is also used ANDAX, 16-bit data for inpuvousput (VO) operations and string manipulation S-bit accumulator Stores the 8-bit result of certain arithmetic | ADD AL, 8-bit data and logic operations. ADD AL, 8-bit data Base register Holds a data pointer used for based, MOV AX, [BX+08 HI] based indexed or register indirect addressing, Count register This can be used in loop, ROL rep, CL shifUrotate instructions and asa counter in "| SHR reg, CL REP string manipulation Data register ‘This can be used as a pon number in VO MUL eg, 16-bit data operations and to hold the data for DIV reg, 16-bit dat multiplication and division operations G2-bit) Table Moda Papert. O22 for) praw tho register organization of 8086 and explain typical application of each registe ister. ore JOURNAL FOR ENGINEERING STuDENTS a5 gf SPECTRUM ALLAN-O! . Sia GROUP a _t Scanned with CamScannera 30. jon: 8086 contains the following it Seti following registers with 8, 16 or 32 bit wide, These are used in the program. pore are several types of registers sich as, 1, Accumulator Temporary registers General purpose registers special purpose registers 5, Segment registers. Accumulator (A): When microprocessor performs any arithmetic (or) logical operations, accumulator provides one of the operand and holds the result of operation, The user ean access this register. 8-it data is collected in AL and 16-bit daa iscollected in AX. ‘Temporary Register These registers are no acessible to ser, They ae used by microprocessor to hold operand and addresses of memory, input and output devices. General Purpose Registers: 8086 has 8 registers each of bits AH, AL, BH, BL, CH, CL, DH, DL. Each register can store cay Sits To store more than 8 bits, two resisters are sein pai. There are register pairs AX, BX, CX, DX. Each register ircan store maximum 16-bit data. . ‘These registers perform following function. () BN/BL[B— Base Register}: For reading data from memory or writing data into memory, SO86 has to select ane memory location, 16-bit effective address of this memory location can be stored in register BX. ® CNCLIC-> Counter]: For rotate and shif instructions, register CL i used as 8-bit counter i.e it used to store 8-bit count In some instruction like REP (repeat), Loop uses CX as 16-bit implicit counter. . (Dx [D> Data Register: For multiplication and division instruction, if data or result is of 32-bits, then register DX is sed to store 16 MSB and register AX is used to store 16 LSBS ic, register pair DX, AX is used to store 32-bit data or result 1a 886, input port adres is of 16-bit and itis stored in reser DX. The name of reser DX is given alongwith IN snd OUT instruction Example: MOV DL, 0001 H (port address) IN AL,DX + Special Ppose Registers: Special purpose resisters are pointe and index register, instruction pointer and program counter, These are 16-bit registers used by 8086 for specific purposes. "nie and Index Group SP __ | Suck Pointer BP | Base Pinter S| Source inex DI___| Destination tnx . Bs, Look for the SIA GROUP LOGO {Yon the TITLE COVER before you buy Scanned with CamScannerUNIT. {HONG ALUitoctin) Ue poten and tae S ntenp benintors ate used we memory palate A) Stet Poin (SUE HE iy used to hold the auldvoss af stavk top memory, Whenever the JK top te upper most fitted YY Hei gta is seat stack anemvory, the cent ab atack pointer bn deerementer Mt Io ineremengg ater cal stack rae operation, ‘ (i) Base Bai ive of I, De w stack AUDYE The use of AP as pointer to a memory hacaton ty sont ha 1619, BP eplatersety 8.4. Memory pointer 49 stack seyrment Lopate Jw nevens any focation diteety jn (i) Sourve tndlex (81) and Destinath nadex (D1): Stand DEhete ae memory painters ive to neyment sexister Di, Hoy, suds the effective adress a data fiom St wh . i Stove {y)_Tnstruetion Pointer (IM: The I contains the oflset address of the next instruction, Le., 1 points to the next instructing tw be fetched from code segment (©) Program Counter (PC): I holds the ad ress ofan instruction which is to be executed next, When rexet is activa DC is sot to the address of the first instruction to he fetehed, Th d 4sthe rem content of program counter is auto i Segment Registers: There are four segment registers. (i) Data Segment (DS) register: It is used to store the hase address of dala sepment Code Segment (CS) register: It is used to store the base address of code segment, (iii) Stack Segment (SS) register: is used to store the base address of slack memory segment (iv) Extra Segment (ES) register: Its used to store the base address of extra memory segment. Default and Specified Segment Registers: For selecting any The E) icroprocessor transfers 20-bit PA. For generating For each memory pointer, there is fixed segment nent register of memory pointers is called default segment registers. Apart from actual segment register, microprocessor can take base address from other segment regi PA, microprocessor adds BA and E, registers for BA. This fixed sey ers. But, the programmer has to specify the name of these registers in the instruction, Hence, these registers are called specified segment registers, The table shows default and specified segment regi fers for each m mnory pointer. sor Specified * Nit : from memory. Microprocessor storing stack of sp SS Nil data (PUSH/POP) Microprocessor performing be cS, Ds, ES simple data transfer from Bx CS, 88, BS memory DI [FA] given in si bs 8.88, ES instruction bs C8,88, 8 bs cS, 8s, Source of string data sl ra CS, ES, 88 Destination of string data Table : A ILINONE JOURNAL FOR ENGINEERING Stapents Hs SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING stupents Sia GROUP £ Scanned with CamScannerMICROPROCESSORS AND MICROCONTROLLERS [JNTU-KAKINADAI 18. Draw the flag register. Classify the flags and explain the function of each flag using an example. (or) Give the 16-bit flag register format of 8086 and oxplain about each flag in detail. Flag register of 8086 is aiags are divide 4 16-bit register which contains 16 fl 10 two parts flops. 9 bits are used as flags as shown in figure (1). These 1. Status flags 2. Control flags », DD, 9, or [se] zr] x Lar] x [ee] x [er SLsps (xExT TxToro ee Sst Xe unpecied Figure (1f Format of Flag Register Status Flags: In this register, 6 flags are used as status flags. When microprocessor performs any arithmetic or logical operation in ALU, depending upon the status of result, microprocessor stores corresponding status bits 0 or | in status flags. The status flags are CF, PF, AF, ZF, SF, OF. Operation of each status flag is as follows. @ Carry Flag (CF): When microprocessor performs addition of two 8 or 16 bit numbers, the result obtained in ALU is maximum of 9 of 17 bit. The last carry generated is directly copied into carry flag. Similarly, when microprocessor performs subtraction of x— y of two 8 or 16 bit numbers then, 1. If > y, then no additional borrow is required to perform subtraction, so CF = 0. 2. If'x $y, then additional borrow is required. So, CF = | and the result of subtraction x — y is negative number represented using 2's complement method. © Auxiliary Carry Flag (AF): When microprocessor performs addition of two 8 ot 16 bit numbers, the carry generated afier addition of 4 LSBs is copied into AF flag é Similarly, when microprocessor perform subtraction of two 8 or 16 bit numbers, the borrow required to perform subtraction of 4 LSBs is copied into AF flag. (i) Parity Flag (PF): When microprocessor performs any arithmetic ological operation in ALU, the parity status of only 8 LSBs of 8 or 16 bit result is stored into parity flag, Mfnumber of ones in LSBs of result is even ie., 0, 2,4, 8 ete, PF = 1. [number of ones in 8 LSBs of result is odd i 1,3,5, 7 etc, PF =0. : (Zero Flag (ZF): When microprocessor performs any arithmetic or logical operation in ALU and all the 8 LSBs or 16 LSBs of the result are zero, then ZF = 1. If 8 or 16 bit result in ALU is non-zero, then ZE = 0, Sign Flag ($F): When microprocessor performs any arithmetic O logical operation of 8 bit number, the MSB of § LSBs of result (D,, bit) is direetly copied into sign Mag. Similarly, when microprocessor perform any arithmetic ological operation of 16 bt number, MSBs of 16 LSBs (D,) bit is direetly copied into sign flag. rn Overtiow Flag (OF): When microprocessor performs any arithmetic operation of signed binary numbers and if the sign ‘esultis within the range, then OF =O. Ifthe signed result is out of range, then OF = | jgned number is + 7F 1110 ~ 80 H and the range of 16 bit signed number is + 7FFE H to ~ 8000 H. The range of \ Look for the SIA GROUP Loco on the TITLE COVER before you buy Scanned with CamScanner——— ee rat Wer Control Flags Daina gm Bet commrolling flags are 2s follows, G) tnerrops Flag (IF) () Decticn Fieg (DF) (@ Trp Faz dF. Operation of each fag is ox folices, INT. WF is made 1 by giving te Interrupt Flag (IF): Imiecrope fag ix wed to enable’ Gable bar deere RTE P= ‘esmraction STI (Set imerrapt Flag), hes INTR is exabied WF is made thes INTR meerragt & Goaabet Bring the meracton CLI (Cex ime F | — To INTR Cava @ Dereon Fag (DF) Fipre Ci: Bioct Sema Trasster Serimg Sescurtions we weed Ser 2 Sic ox cha of deme 78 eration & wed to camafer 2 bine pte words Soe source memory incation 2 decinstioe memory lncxtion, “To rane he Game Selly Se 2 Sete ced Se acne asideoss of source and deminon of [* bytevward een Ss, ster each song specaton DF i made 0 asing the insrarson CLD (Clear Direction fag) swe dare Sina Sem ne bye ward, the cece aciteess of Hae byte weed of source amd ; spe second seme egies SU amd DL A ec ree ward ci he Se irs i Sa 1 ce For Se ster meng opermicn DF § made | eng Se Race STD (St Smccce gh qq Trap Pag Sop See Ste 0 Se ope ces ome oe oe ein ed cs oming cpenio S mop Gig & ade |e ercmee cteos Se See ssie eecping ade SOE weopiy mak Seed ae ee eee tee tee Ges. Explain with nest diagram bow S086 access 2 byse or word trom even and oad memory banks. seeing copenty of SOME miccpmeseer & shor 15 & Aes: Tae Scanned with CamScannerMICRO} The organization OF even and odd me PROCESO} ‘memory RS AND MICROCONTROLLERS (JNTU-KAKINADAL nks of 8086 microprocessor is figure below, Data Bus Even Memory Bank IC's Memory, Bank IC's sinks (512k 8) si2kB (512k x8) CEN EN (Odd Memory Bank Even Memory cee Bank Setect Signal 18 Menery Adres Space FFFFF, a FFFFE, FrFrp,| 51248 084 Memory 51243 Even Memory FrFFC| rever,| “itssSoee 7 > rrpre,y tS Frees, FrFrD FrFFc, FFFFA, Ferra FerFa — =| > ‘00007, 00006, 000, 0008, 00003, 0002, 001, 0000, Figure : Memory Organization The accessing ofa byte ora word from even and odd memory banks by 886 is deséribed below. 4 MeAccess froin Even Bank: The pins Ay “te ineven memory bank. By enabling eve 4 “Te Access from Odd Bank: The pins Ay ‘odd memory bank. By enabling odd Look for the Sli and IIE must be asserted low and high respectively for read/write operation of a in bank, the data is transferred through D,-D, lines, and TIE must be asserted high and low respectively for readwrite operation of a bank, the data is transferred through D,-D,, lines. | GROUP LOGO Qf; on the TITLE COVER before:you buy Scanned with CamScanner2.15 —NIT-1 (8086 Architecture) T6086 Architecture) operation of n memory + for read Word Access from Even Bank: The pins A, and BHE must be asserted 10w a ‘ ren and od backs, the at bank (i.e., lower byte in even address and higher byte in odd address). By enabling both © through D,-D,, lines. transferreq 5 ite operation of a word in odd memory bank Word Access from Odd Bank: The processor executes two bus eyeles for read/write operatio (ie. lower byte in odd address and higher byte in even address). During the first cyele, the pins Ay and My : apenas high and low respectively. By enabling the odd bank, the lower byte of 16-bit operand is transfered throug brie the higher re the second eyele, the pins A, and BHE must be asserted low and high respectively. By enabling the even bank, the higher byte of 16-bit operand is transferred through D,-D, lines 1.3 INTERRUPTS AND INTERRUPT RESPONSES Q20. What is an interrupt? Classify the interrupts of 8086. Ans: Interrupt Jn microprocessors, interrupts are the signals that break the current execution of instructions and transfer the control toa special program called Interrupt Service Routine (ISR). Thus, afte the execution of ISR, the control is returned back to the main program which was being halted. Classification of Interrupts of 8086 The interrupts of 8086 can be classified into three ways that are shown in figure, Interrupts and software non-vectored —_non-maskable | | | Hardware Vectored and Maskable and interrupts interrupts interrupts Figure Hardware and Software Interrupts Hardware interrupts are the inerupt, which are intiaed by extemal hardware by sending an appropriate signal to the interrupt pin of the processor. Hardware interrupts of 8086 are NMI and INTR. Software interrupts are the interrupts, which are initiated by insertin, '# @ special instructions in the program during its execution, In 8086 processor, there are 256 software interrupts denoted by i INT n, where n is type OOH to FFH. Maskable and Non-maskable Interrupts : ‘The processor has the facility to accept (or) reject interrupt, Programming the processor to accept an interrupt is called ny epee sprsbnaanailaed meade eed EN ‘masking (or) disabling 39 interrupt. nhs way the interrupts ae lassie into mashable and non mayhae nn : errupts. In 8086 processor, NMI —Non-maskable interrupt. INTR — Maskable interrupt, Vectored and Non-vectored Interrupts ‘When an interrupt is accepted by the processor, ifthe pro Tam Control automatical vectored address, then the interrupt is called vectored inte ‘Tupt. The vector address is Whereas, in non-veciored inerus, the iterupt device must supply the address of the Interrupt Service Routing (ISR) {o be executed in response to the interrupt. See iL FOR ENGINEERING ST) a SET ALONE URN FOR EVENS aé & * Scanned with CamScanner6 M 43 ICROPR a ‘Write about interrupt sequen, OCESSORS AND MICROCONTROLLERS [JNTU-KAKINADA] in an 8086 system, Explain the interrupt response sequence of om ans . The interrupt resPonse sequence of 8086 involves the following steps, sop Initially when interrupt occurs, the status of flag is saved in the stack. sep? Inthe next step, interrupt flag isd . isk ‘Tupt flag is disabled (IF = 0) to ensure that no other interrupt received on INTR line which interrupts sep 3 Then, trap flag is disabled (TF = 0), sup 4 Inthe next step, the CS register is pushed on to the stack. ep In this the IP register is pushed onto the stack. Sep 6 In this the control is transferred to a ISR in different code ségments, which is called as “far jump’. Sep? Then, ISR executes the interrupt request. After execution of interrupt, the last instruction IRET is executed that means ‘epointer retums to the previous program, which was stopped during execution. Sep 8 Inthe next step, IP and GS values are taken back from stack one after the other to get back the address of the next instruc- ‘oxin the normal sequence. Sep9 ‘The content of lag register is taken back from stack to restore the original staus of the flag Sep 10 Inlast step, control is transferred and instruction equest i as shown in figure below. ‘execution resumes from point where it was stopped. The steps involved in processing an interrupt r MAIN PROGRAM yt Pst CLEARIE CLEAR TE 15k, Pusit cs ust P SETISR. on the TITLE COVER before you buy GROUP Loco Scanned with CamScannerUNIT-1_ (8086 Architecture) Q22, Explain tho types of Interrupts In 8086. Model Papert, a2) erupts is important because through this high Ine interrupts of a certain Tevel and below. The Ans: Interrupt srvcrre refers tote proveence of interns, The precedence oF precedence intemupt can preempt intemupt of ower pity. Ths, processor ca ist Mie the memory size of tert Yetr ale following figure shows the internipt ttre of S086, also cle interop weet" ee sé ypes of interrupt vectors cach oF 4 PYTES: is of 1024 bytes of addressed from ODO 1 to OO3FF H. Itcontains 25 44 vectors) are defined by INTEL, s0 they 27) are reserved for their use in various first line interrupt veetors are identical pe 010 tye In $086, among 256 types of intesupt vectors first S types (Le 9 31 (ies are known as predefined interrupt vectors. The veetors from type $10 OPE microprocessor families. The last 224 vectors are avaiable as use interrupt vector TH in all INTEL microprocessor family members from the 8086 to the pen! OOuFF HH Type 255 vector oonFC H (Available) Available interrupt vectors (224) F ft Type sz vector | [._ (Available) 00080 H i FI vector ooo7F HH [_ Types! vector _1 0007C H (Reserved) Reserved interrupt vectors (27) FF ar Tresor} ap font (Reserved) 00013 H Typed vector 00010 (Overflow) “Type 3 vector 0000C H (Breakpoint) a 5 Type 2 vector Predefined interrupt vectors (3) 00008 H (Nonmaskable) “Type I vector 00004 (Single-step) a Terbit code segment base [Bre 0 vector res Té-bit offset \.00000 (ivide-by-0) Interrupt vector Figure: Interrupt Structure of 8086 Each vector is of four bytes long and contains the starting address of the interrupt service procedure. The first two bytes of the vecior contains the offset address andthe ast two bytes contains the segment addeess. The following are the INTEL predefined (or dedicated) interrupts. “Type 0: Division by zero occurs whenevershe result ofa division overflows dr whenever an temp is made to divide by 26° ‘Type 1: Single step or wap occur afer the execution of each instalation i the Trap Fag (TF) its set. Upon accepting hs pt, the TF-bit is cleared, so thatthe interrupt service executes at full sped a meme interruy ‘Type 2 + Non Maskable Interupt (NMI is a result of placing logic ton the NMI input pin tothe mi i ° ic input jsnon-maskable, which means that it cannot be disabled opsoccsser TE a ‘Type 3 Breskpointintrapt is used to implement a breakpoint Faston, which executes. program party or ypto the es! point and then retum the contol 19 set vector used with the INTO instruction. The INTO insteuction is ‘ype 4: Overflow isa spec = et instruction. The INTO instruction interrupts the program ifan ovestlo¥ flected by the overflow flag. congition exists 35 10 IR ENGINEERING STi —————___ our ts ORE UDENTS, 7 JOURNAL F SIA GR SPECTRUM ALLA . | Scanned with CamScannerORS AND MICROCONTROLLERS [JNTU-KAKINADA] Explain the advantages of using interrupt vector table for 8036. 8086 execu inet ae era cada Ne steuction, it ranches from min program to ISR uting intersegment nrc essing mode go W6bit effective address and have addnen is taneferred from four quccessive [ovations to [Pad CS. The phy goa memory location is obtained by using address of | equation 4 +n. So, for each INT o instruction four memory locations are required Henee. for INT 256 instruction, numberof tastions required 286 «4 10M TK, The starting 1 k memory locations which are uted for EA ant BA of INT # instruction gaemupt pointer table called interrupt vector table of ‘The interrupt pointer table consisting of 1 k locations ie as chown in figure Below Mera wibewe Memes Leesteen 157 0S ommnn meen — mer bee | own comet } owns owe Ht | ore contort } wer ass corr it Int 255 — on Figure: Interrupt Vector Tabla Aevantapes 1. The entries un IVR are consecutive, it means, the frst entry pointed by the IDTR isan interrupt 2. Wis easy to get the address of interrupt handler 3 det to change the interrupt handler, ils Sires in the table must be change a. asia coed ara that cause the 6086 to perform each of the following types of Interrupts. Describe the ‘Type-0, Type-t, Type-2. Type-3 and Types. ‘Ler lnterrapt): The type oterruptsanpementel by intl ay apart execution ofthe divide Brpe 8 insarrups otis by 7 docs atype-d wernt afte oul ofa diviiow operation is too lange fit in the destination santo. Ma ne ean on pe aceon be sie ttn a we he Reyer and this witernupt 1 pat i wo a - jive laterrupt): When the Trap/Tr oe «Flay (TE) in set, the 8086 procesor Type faterrupt single SteP FE ae ‘exceution of each instruction. Uhe user can write an ISR for type-1 interrupt vay epee cmtan eh ne halt the processor temporanl) STINT pruveed lo euecute Heat instruction. Executing One instruction at time is Srercan te vei FO nr ant Os we lay ogra singe step exe tense ey nein wero COVER before you buy GROUP LOGO Gf on the TITLE A Look tor the SI Lo — a Scanned with CamScannerInte Non-maskable Interrant): The 2086 orocessor 2 terete @ typeré Serrupe woen ‘Type-2 Interrupt (Non-maskable Interrupt): The 8086 processor ngage a ox masked The ype-2 intern ‘ eceives a low-to-high transition on its NMI input pin. This interrupt cannot be dis rn + failure. is used to save program data or processor status in case of system AC powe 4. Type-3 Interrupt (Break-point Interrupt): The type-3 interrupt is used to implement a oe function, which executes a program partly or upto the desired point and then return the contro! to user. The bea im met initiatey by the execution of INT3 instruction. The system designer has to write an ISR for type-3 to impl ea 1¢ breakpoint function, which displays a message and return the control to user whenever type-3 interrupt is initiate is set i ithmet 5. Type-t Interrupt (Overflow Interrupt): In 8086 processor, the overflow flag is set, if the aged ni tt eatin Benerates a result whose size is larger than the size of destination register/memory, During such condition, the type. 5 , naan interrupt can be used to indicate an error condition. The typé-4 interrupt is initiated by INTO instruction. 1.4 8086 SYSTEM TIMING, MINIMUM MODE AND MAXIMUM MODE CONFIGURATION Q25. Explain the minimum mode operation of 8086 with appropriate pin diagram. Ans: The 8086 can operate in minimum mode iising the pin \(N/MIX - The only pins that change according to the mode of operation are pins 24 to 31 and the other pins remain same. When MN/MX is made logic ‘1’ or 5 V is supplied, 8086 operates in minimum mode. The pin diagram for minimum mode operation is as shown in figure (1). oo 5 BL ve v0, —] 2 wh a0, mols ae as, : 4 ” AWS AD, 5 % Aas mele ashe awn 1, —4 > se: ema, Wm tow Lave ountboe 9 alow , —| a Le row on wb moa wo, —| 2 phew wo, — 6 al wis wo, J aL pvt wo, 4s we ome wo, —| she ae wa a ule ome po — Bp— Test |) 2 b~ neavy oxo —| a» | eee Figure (1k: 2086 Pin Configuration (Minimum Made) ‘The pin description for pins 24 10 31 is as follows, Pin.24 -(INTA) The Inerrupt Acknowledge signal (INTA ) is generated on pin 24 of $086, Wis an active tow pin - Wis an active low pi in.25 -(ALE): The Adress Latch Enable signal (ALE) is generated on pin 25 of 8086 t goes hi; Tad enables the microprocessor 1 Tnth aes neither 5283 o¢ $282 adden etches Boes high during OR ENGINEERING sta . SPECTRUM ALL-IN-ONE JOURNAL F Dents —————six crour a ee 4 Scanned with CamScanner \ 4MICRop; ROCESSORS AND MICROCONTROLLERS [JNTU. KAKINADAI ( When the octat bus ranseeive fate seal WeMEBIS When ite onge “Wet $286/8287 is used, Data Enable signal (DEN ) indicates an output yina8? OWIO): Using MID, the epy setand when its ow. an as ane cither access memory or VO devices. When M/TO is high, memory is accessed tris controlled. When "a NTRS INTA| READY | READY RESET Figure (2k Minimum Mode System * 5 | Exptain the Tiaximum mode operation of 8086 with appropriate pin diagram, ‘8° The 8086 can operate in maximum mode using the pin MIN/MX. The ony pins that change according othe mode of * ‘sar en, MX is mac | mate" Ae pins 24 49 31 and the other pins remain the same. When MN/MIX is made logic 0, the processor operates io wim mode operation is given in figure (1). ‘ode, The pin diagram for maxim Look for ine SUA GROUP LOGO 4} on the'TITLE COVER before you buy Scanned with CamScannerNIT-1._ (8086 Architecture) GND (en 30 KO ADs ADw gg Le AWS Dy ae Ps ee ¥ . ADs . 36 LAW'S Da 35 > Awis, AD, Me BEES, AD, 8086 33 |= MN wo, oxo | as aoe 31 no 20 AD, 2» AD, 28 AD, u AD, wt & ADs wf oe . NMI wr Qs, : ie 3 TEST cuK 2 fe READY oxo ‘The pin description for pins 24 to 31 is as follows, Pin.24 (QS,) and Pin.25 (QS): Pin 24 and 25 together gives the status ofthe instruction queue. These pins indicates the operation in the queue during the previous clock interval, The combinations of QS, and QS, are given in table (1). Qs, Qs, Meaning : 0 0 | Nooperation 0 1 | First byte of opcode from queue 1 0 | Queue is cleaned 1 1 Next byte of opcode from queue. Table ( I Instruction Queue Status Bits pin.26 Go), Pin.27 (1), Pin.28 (Ss): ache ent the sas signals forthe $288 bus controler. The conglleri8 smory or VO access. The logical combinat — generates the control signals for memory sical combinations of these pins are given in table (2), 7 WT ALLIN-ONE JOURNAL FOR ENGINEERING STUDENTS Sia GRouP > "Scanned with CamScanner122 MICROPROCESSORS AND MICROCONTROLLERS [NTU-KAKINADA] ‘ Meaning, Interrupt acknowledge U o 1 | Data from 70 read port 2 1 0 | Datais written to the 10 port — o i Malt 1 o 0 Opeode is fetched 1 0 Read from memory 0 | Write 10 memory 1_| Passive stare Toblo (2k: Status Signals tis (LOCK): In multiprocessor systems, te instructions pefined wih lock ar executed and the bus isnot accessible by nother potential master. Pie30 (RQIGT) and Pin.31 (RQGT,): When othe * processors request the CPU to release the local bus either of the pins 30° saipin31 is used. The signal RQ/GT, on pin.31 has lesser priority than the RQIGT, The configuration of maximum mode operation i as shown in figure (2). | ann READY- clock RESET _¥. OE _ CLK Reser FP ces [BBE neabye—| Lat ~— 1 88) bE. BHE — Ay Au apis” ap — he 8086 Transceivers} (Two 8286s) Data bus ~ (2) be re be | orate a) See caters F | 3i] 7 le “| j wri 4 stot | Hi wre Pins men | = cy ner | maT R250 and ocr es | . logic | | . cu | Loco A Look for the SI GROUP — on the TITLE COVER before you buy | Scanned with CamScanner1S UNIT (08s Arentecnre) rain cyclen? Compas ‘G27. Discuss the system bus cycle of 6086 with a neat diagram. What is the use ‘of wait cycles? Compare wait and idle cycles. ns Model Papers cz System Bus Cyele of $086: In $086, the address bus and data bus are multiplexed inorder 19 $22 maximum utilization of the process pins. This multiplexed address and data bus commonly termed.as time multiplexed adress and data bus. Demultpetcg of address and data bus can be done using a few latches and transceivers. Basically, 8086 processor bus ¢¥ ele Conse: of 4 clock eqgeles ie, TT, Ty Tp During 7, clock eye, the processor transmits the address, hich i of one cycle duration. During 7, the trstated bus changes ite direction with respect to data read cycle. During 7, and 7, data wansfer kes eee les “NOT READY” state, These Wait states (7) are introduced between 7, and T,, when the device is slow and indicat states are referred as idle state (I), wait tate (T_) and inactive states. [ALE: ALE stinds for Address Latch Enable. During 7, state, a pulse i applied to ALE pin. This signal is active high and is never tistated. BAE /s.: BRE 's_sands for Bus High Enable Status. This is used to indicat the transfer of data over the higher order (D.-D) datz bus. DI/R: DIR seands for Dota Transmit Receive. This output is used to decide the direction of data flow through the trans- receivers (bidirectional bufers). When the processor sends out data this signal is high and when the processor is receiving des, this signal is low. ° DEN: DEN stands for Data Enable. This signal indicates the availabilty of valid data over the address/data lines. Itis used enable the transreceivers (bidirectional buffers) to separate the data form the multiplexed address/data signal. It is active fom the middle of *7,’till the middle of ‘7,”. This is tistated during “hold acknowledge” signal. : Mero eetqce = Memerywete erie. — Te si Twi Te TH) Tl 13! Twi os = vesces —X SREY BK oe ome Bb) Care i more Wf rr A a eee Figure: General Bus Operation Cycle of 8086 oat FOR ENGINEERING stuDEREy a Specrnan aULaneOnE journal DENTS ——______s iq GRouP a = Ee Scanned with CamScannera UERULEDDUK: Gesot Wait State SAND MIGHOCUNIKULLEKS JN TU-KAKINADAL Wait state is used to reduce the energy consimption ofa processor. py reducing the clock, it keeps the processor core cool Inextends battery life in portable computing device. comparison between Wait m Idle States L wait state and e Both wait state and idle state exist between two clock cycles when the device is stow and indicates “NOT READY” state, Wait state is of the same duration as a clock eyele, But, idle state can be more or less than a clock cycle. During a wait state, the signals on the buses remain the same as they were at the start of the wait state. Butin idle state, the system becomes inactive. 28. With neat diagram explain the minimum mode of operation of 8086. Anst The read and write cycle timing diagrams of, 8086 operating in minimum mode are shown in figures (1) and (2) respectively. ONE. BUS CYCLE CLK fr i i AI9IS,- A16,5, inimum Mode Memory Read One pus CYCLE. — ‘And BHE/S; \ AD g-AP, yarns omy ax) — | ALE, a TOW= TO WRITE HK MEMORY WRITE ‘The Timing Di ‘ Look for the SIA GROUP LOGO yum Modo Memory Write n the TITLE COVER before you buy 1 ____—» alld Scanned with CamScanner(8086 Architecture) 1.25 ‘The above timing diagrams can be understood by the following stePS- . A During the clock pulse 7, just before starting the bus eycle, processor gives 2 pulse to ALE ‘The signals DT/R, M/IO, DEN, BHE and address must be stable, before the occurrence of falling edge of ALE. The signal DEN= 1 and DT/R- must be low for input and high for output. ICs 741.8373 or 8282 holds the address during clock interval 7 atthe falling edge of ALE signal. 4, During the clock pulse 7, the address signals of the processor are disabled and the status bits S, to S, are present on pins AD,/S,-AD,/S, and BHE/S, respectively. 5. Transceiver is enabled by lowering the data enable (DEN) signals i.e., (DEN) = 0. ; 6. During T,clock pulse, the read signal (RD) is made active low and all the address/data signals i.e., AD, to AD,, transit to high impedance state, 7 If the memory of VO interface is capable of transferring the data without any buffering overhead, then there is no wait state. In this case, data is directly placed on the bus during clock pulse 7,. 8 During the raising edge of clock pulse T,, RD goes high after the data is received by the processor. 9° Transition of RD to 1, serves as an intimation taken by memory or VO devices to disable their data 10. During the write operation, the data is directly placed on the bus during 7, clock pulse by making WR signal low. M1, After receiving the data, processor raises the writg signal ie., WR =I during 7, state and all the memory and /O devices disable their respective data signals. 12. For either read or write operation, transceiver is disabled by raising Data Enable (DEN) signal. 13. * Ready input of 8086 is disabled and additional wait states (7,) are employed between clock cycles T, and T,, when processor memory or 1/0 devices are not quick enough in responding to data transfer. 29. Draw and discuss the maximum mode 8086 system with relevant read and write cycle timing diagrams. Ans: The read and write cycle timing diagrams of 8086 operating in maximum mode are shown in figures (1) and (2) respectively. | One bus eyele To) oe | yond 990 Sie Oe Address/status == BHE, A1S-A16 Adaresidate | 5S eROE@ TRE] sori. a OURNAL FOR ENGing BE, A19-A16 Float ‘and BHE/S7 Addvess/data {AD15-AD0) }—Cirr] Data out D15-D0, *ALE om RG 0 ORE CORI or POW erate rarer f *DeN [- bes +8288 bus controller outputs. Figure (2 Write Operation ‘The above timing diagrams can be understood by the following steps. |. During the clock pulse 7, just before starting the bus cycle the status signals (S) , ,,5:) are set to ‘1’. By the change in the status signals, controller gives a pulse to ALE. After raising edge of ALE, the signals MRDC/IDRC (Memory Read Command/Input Output Read Command) and DT/ Rare stable until 7, state. This can be achieved by making DEN = 0 and ‘DT/R low for input and high for output. Then IC 8282 holds the address during clock pulse 7, at following edge of the ALE signal. During clock pulse ‘7,’, address signals of the processor are disabled and the status bits S,-S, are present on AY/S,~d, /S, and BHE/S, respectively. ‘The transceiver is activated by making Data Enable high. signals MRDC or TORC in 7, state and maintained tll7, carried out by enabling the During the write operation, the signals MWTC or ATOWC are enabled from 7, to 7, state and the signals MWTC or TOWC are enabled from 7, to 7, sate ‘fer the reception of data in the clock pulse 7,, the processor raises the signal MWTC ie., MWRC Detecting the change in the write signal, ll the memory and 1/0 devices disable their respective daa signals, For either read or waite operation, transceiver is disabled by raising Data Enable (DEN) signal. When the READY input of 8086 is not ativated, adltional wait states (7) are employed between the clock pulses 7, and 7, . ee eee eee ee Ee Look for the SIA GROUP LOGO QJ on the TITLE COVER before you buy Scanned with CamScanner