UNIT PIC MICROCONTROLLE PART-A SHORT QUESTIONS WITH SOLUTIONS Q1. Write any four features of PIC microcontroller. An: ‘The various features of PIC microcontrollers are, 1. PIC microcontrollers are RISC computers and employ Harvard Architecture for their memory organization. The seq lilies separate memories je. data memory of $bits and program memory ranging from 12 lo Té-bite 2. ‘The instruction set of PIC involves only 35 instructions of 4-bits ‘cach, with execution time of about 0,2 ps (for: ‘maxim Clock rate). These instructions are highly orthogonal they are non-overlapping or mutually independent. ‘The machine eycle of PIC microcontrollers employ 4-clock pulses ‘Any operation in PIC controller is accomplished using any ofthe available register and addressing modes, Thisis due the similar format of all the instructions handled by PIC Q2. Draw the pin diagram of PIC16F877. Ans: Model Papers crt The pin diagram of PIC16F877 ‘microcontroller is as shown in figure. CI MCLE, THY —41 40h-— reveco RAOANO —]2 2h— Rewrcc RAWANI —13 33-— ras RAYANIVs¢,— ——la yh rps RASANSV yg, + —5 36}-— RBIPGM 6 3sf-— RB Rawtockt —17 Mh RoI RAS/SS/ANS 8 33 RBOINT REORDIANS 49 cigegey 32h V0 10 (6F874 I Vg " 30—= aD riPsp7 n 29-— Ros PSP6 oscuctKiy 15 2s rospsps oscucLkout — 14 27-— eospsps ReoTOsoTICKI —4 15, 26}-—- ROIRXDT Revmioscyccr2 —4 16 25je— ROBTICK Rcxccet —i7 24 Resispo RCBSCKISCL ali 2p rcusprspa RDoPSPO —fi9 ni rpseses RDVPSPI —l20 21}-—~ rowpsp2 Le | 2m SMG Ee. WA GROAN Scanned with CamScanner: Mic ROPROCESSORS ANI B i fe ID MICROCONTROLLERS, G&_ Write any four features of Bic serarp pee microcontroe SES LINTU-KAKINADAL An’ The features of PIC 16F877 fash microcontol ontroller are, 1. PIC T6FS77 isa lash microcontroller with a Mach Programmable memory of SK bytes and 14 words of ln 3 Itusesaseto memory of 8K bytes an a instructions 3 Reonsins e ‘at memory of 368 «8 hytes of RAM and 256 * 8 bytes of EEPROM. 4_lsupporss 3 timers (Timer 0, Timer 1, Timer 2) along with watchdog timer. a4, List the types of interrupts in PIC16F877, - Ans . Model Papert, a1(f) ‘The various types of interrupts in PICI6F877 are, }._ Extemal interrupt RBOINT. 2. PORTB change interrupt 3. Timer-O overflow interrupt and 4 Peripheral interrupts. QS. List the advantages of PIC microcontrollers. Ans: ‘The advantages of PIC Microcontroller are, {PIC microcontrollers are consistent and faulty of PIC percentage is very less. (i) The performance of the PIC microcontroller is very fast because of using RISC architecture. (ii) Low power consumption and easier programming compare to other microcontrollers (iv) _Interfacing of an analog device is easy without any extra circuitry. Q6. List any five applications of PIC microcontrollers. Ans: : Model Paper, 10 The PIC microcontrollers find applications in the following areas as, a Household Appliances (i) Office Equipment (i) Instruments ©) Peripheral Devices (Motor Control i) Industry ——————————a, iP on the TITLE COVER before you buy GROUP LOGO ' ne SIA Look for tl Scanned with CamScannerPART-B ESSAY QUESTIONS WITH SOLUTIONS 8.1 INTRODUCTION CHARACTERISTICS OF PIC MICROCONTROLLER, Pic MICROCONTROLLER FAMILIES Q7. Briefly explain aboutevolution of PIC microcontrollers. Ans: Evolution of PIC Microcontrollers [The peripheral interface controller, abbreviated as PIC, is an 8-bit microcontrolletandit ‘was introduced by the ‘Microg efmoey corporation” in the year 1976, i ha high epabiliy to store and execute programs which increased its demand wig a short span of time, The PIC MCU (Microcontroller Unit) has many features of RISC system and its memory was upgraded after its inventing Using memories such as ROM, EEPROM, UV-EPROM flash ROM, OTP and masked ROM etc. PIC Microcontroller with ROM In the early days, PIC MCU was built with ROM to store programs and microcodes. The PICI8 MCU has large rogrn Rony Sbace With 2MB and is available in various memories like Mash ROM, masked ROM and OTP ROM. The size Of progran ROM varies from 4 kB to 128 kB, PIC Microcontroller with EPROM In the year 1985, PIC was upgraded with EPROM which can produce a programmable channel controller. Some ofthe FIC MCU's use UV-EPROM for on-chip program ROM, but it takes more lime to erase the ROM and thus, Producing mere delay in programming. “Hence, it led to the introduction of flash memory version into PIC family, PIC Microcontrollers with Flash Memory PICISFXXX Family The family number includes the leter F” which stands for ‘Flash’. The flash ROM can be erased electrically and is inbuilt erasing (by ROM itself) eliminating the need of external ROM eraser. The fash ROM enhances the speed ofprosranning and erasing. This flash version of PIC is used for product development. PIC Microcontroller with OTP OTP stands for ‘One Time Programmable’ and was introduced by microchip. The OTP ROM is indicated by the leet “C* inthe PIC family i, PICLECXXX family. The only drawback with OTP version is that once the programming of chip st done, it eannot be reprogrammed, i. the chip can be programmed once while manufacturing, ‘This OTP version of PIC is used after the design of product for mass production, since, the OTP ROM is cheaper thst flash ROM. PIC MCU Data RAM ‘The RAM is used in microcontroller unt to store data while ROM is used to store program (or) code, The range of RAN is 256 bytes to 4096 bytes for PIC 18 MCU and it has large space for data RAM with 4 kB. ‘The PIC families are classified as follows, in which every family has more number of components which provides bi in special features, First Family of PIC : PICLOFXXX js the first family of PIC from microchip technology. Itis called low end PCU and is of low cosh performance, 8-bit, flly static, Nash-based CMOS MCU. These are provided with an 8-bit ALU and a working revise. Second Family PIC 12(PIC12FXXX) is the second family of PIC MCU which are more popular PIC chips and are called mid-rande ‘Third Family ' PIC16(16FXXX) is the third family of PIC. It is provided with 3.5 to 14 KB of flash memory and 256 byte of RAM Fourth Family PICI7/18(I8FXXX) is provided with 16-bit program word architecture and has advanced RISC architecture. SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS ‘SIA GROUP & Scanned with CamScannerMIcRop! ROC! ry Gaithe features Of PIC microcontra ESSORS AND MICROCONTROLLERS [JNTU-KAKINADAI 3 w Model Papers aT sefpherl Interface Controller (PIC) isan embe ee Fehip eho "ied controller that belongs to the family of microcontrollers designed ant ‘pe various features of PIC microcontrollers are. 1C microcontrollers are RISC computers and e . tS and employ Harvard Architecture for their memory organization. The system separate memori lecture for their memory ore Y nae is Le. data memory of 8-bits and program memory ranging from 12 to 16-bis instruction set of PIC involves only 35 me Ge ee volves only 35 instructions of 4-bits each, with execution time of about 0.2 us (for maximum aka ions are highly orthogonal ie, they are non-overlapping or mutually independent. 3 Tee machine cycle of PIC microcontrollers employ 4-clock pulses. 4) Aay operation in PIC controller is accomplished using any ofthe available register and addressing modes. This is due to the similar format of all the instructions handled by PIC. .) P1C microcontrollers also provide functions such as, (©) Analog-to-digital conversion (8) Built-in power-on-reset (©) Built-in brown-out-reset (ic., PIC automatically resets whenever the suppl y voltage falls below 4 V). " PIC supports a fully static design. The oscillator frequency of PIC in any of the desired frequency range can vary from ‘minimum to maximum and can also be stopped and restored back at any time. The components used for estimating the cscilator frequency of PIC are low-cost RC circuit or Quartz crystal ot ceramic resonator. It can also be 2 selectable EPROM. 1) also provides a power saving mode called ‘SLEEPY. In this mode, the clock is freezed by restoring al its dats in the processor memory. The controller remiains inthe SLEEP mode until the next RESET of PIC. (3) The microcontroller supports a watch Dog Timer (WDT) along with on-chip RC oscillator which prevents the controller fiom “endless loop hanging condition”. (%) The PIC microcontrollers such as 16C6X and 16C7X require an operating voltage of about 30 to 60 V with very less consumption of power. ‘9. PIC supports « maximum of 12 independent interrupt sources (0) The program memory of PIC controllers range from 1024 » 14 words to $192 * 14 words (3) Pic microcontrollers operating aa maximum speed of 20 ME suppor data memory ranging fom 36 bytes to 368 bytes (user RAM). °8. “Compare PIGTEFEXX and PIC16CGXI7X families. Ans: Model Papers, 718) PICLOESXx are 8-bit CMOS lah microcontrollers, whereas PICIGCEX are S-bit microcontoUers The features common to both PICIGFSXX and PICIOCE: ‘ architect The core is of RISC processor and uses Harvard architecture ilies are, These have interrupt capability GROUP LOGO <5 on the TITLE COVER before you buy Look for the SIA Scanned with CamScannera Sersunery he instruction set has 35 single word instructions only. Operating speed, (@__ DC-20 MHz clock input Gi) DC-200 ns instruction eyele, They have $-level deep hardware stack. ‘They supports direct, indirect and relative addressing modes. ‘They have inbuild Power-On Reset (POR) and Oscillator Start-up Timer (OST) They have power-up timer (PWRT) and oscillator start-up timer (OST). 9 They have watchdog timer (WDT). They have programmable code protection and supports power saving SLEEP mode. i They have selectable oscillator options. These can be operated at commercial industrial and extended temperature ranges. The ferences between PIC16F8XX and PICI6COX families are given below. PICIGF8XX_ PICL6CXX Ithas low-power, high speed CMOS __ | thas low-power, high-speed CMOS EPROM/ROM, FLASH/EEPROM. It operates from 2V to 5.5 V. It operates from 2.5 V io 6 V. Power consumption: ‘ . | Power consumption: > <0.6mA @3V,4MHz >. <2mA — @5V,4MHz > <20HA @3V,32KHz > <1SHA @3V,32 KHz > <1WA — @Standby current. > “ wsttuction. Ts ‘The term ‘Register types of register files namely. C ‘The general purpose register fi special purpose register file employs inpuvoutput ports and control registers, SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS Ss SPECTRUM ALL-IN- J FOR IEERING STUDENTS SIA GROUP $ «is used to store the intermediate data and variables. (Eg ; g-pit RAM locations) ™ Scanned with CamScannerrant su L___Jern Baek 0128 bytes Bank 1128 tes Figure (3): Aeistr File Structure of Y6C8X.. Figure a Reise File Structure of 16C7X Itcan be observ ‘ed from figures (3) and (4) that, ()_Theregister file consists of address location fom 00 to FFH. (i) The register structure requires 8-bit address, which gives a total of 256 locations. The instruction: ng direc ae ar at iret addressing mode inorder to ares the registers lize 7-its of instructions only. lection of any o' i i Hoes of any ofthe two register banks is caried out using the register bank select bi re, RDO hows STATUS The special-purpose registers are the registers at registers atthe lower bytes of register 25 ictions provided by these sFRs are abulted noble i bytes of register bank. The special functions provided by S.No | dares | Register Name [Description | | Address | Register Name | Docrpive n oor INDE | adie register 0 INDE | Copy of NDF 2 a ree Realtime st | option lockout reps 3 ret | Program counter | | a2 Peis | Progameounter 4 status | — staus word a | status | sums word veaiser reer s | owe FR Fileseect 4 Fs File select register repiser 6 05 PoRT A Pot a 88 TRIss | Data diecton regster PORT A 1. 06 PorT B Pon B 6 tase — | datrdirction register PORTB a or | anconor | avceonrot 8 | apconor | aDceoatat repiser repster 9° 0% aprest | ADC result ADRES* ADC rest reiter repste 0 w » i | oxee | pccarit outer | | 8a | rcLaTHC | Program counter byte Thoh byte ia} ope | antcon | tnterupt contat 4B | aetcons+ | tateupt contol reper reeister bo | = Bank 1 Bak 2 Table (1): Register File Structure Look for the SIA GROUP LOGO {i} on the TITLE COVER before you buy = Scanned with CamScannernO CON ONES) Registers marked with a single asterisk * “aware used for 16C71 PIC ™ can be addressed from either of the two banks. (b) OPTION Register Figure (5) represents the OPTION register of PIC w INT. i.e., Interrupt is on falling edge for INTEDG =| Interrupt is on raising edge for INTEDG microcontroller. 6 5 4 2 2 icrocontrolict> 1 RPO RTE [PSA pareDs [RTS PS? pst | P50) -BPU enables the internal pull " (i) INTEDG- Interrupt Edge Select Bit; INTEDG determines the falling or rising eds 10 (5|: OPTION Register of 16 I-ups for PORT B, which is OF (iii) RTS: RTS specifies the signal source of RTCC ie, RTS= | (0 Internal 1 TransitiononRA4/RTCC pin (iv) RTE: RTE decides the signal edge of RTCC i re { (v) Presealar Assi 1 LowtoHigh [0 Hightolow ment Bit (PSA): PSA = I indicates the prescalar assigned to Watch-Dog Timer (WDT), whereas PSA |XX F for RBPU =1 and ON for RBPU =o, ¢ sensitivities for external inter =0 denotes the P assigned to RTC. Table (2) represents the bit values (PS2, PS1, PSO) for RTCC and WDT. ps2 | pst | pso | Rrcc | woT ofofo fiz fas o feof: tus fiz of: [o [us fis oft [a [rs fie to fo fix fie tfeo[i fue fim Ce ee ee Table (2) (©) INTCON Register - Interrupt Control Register Figure (6) shows the INTCON register of 16C61/71 microcontroller. GIE *ADIE, Toe | INTE | RBIE Tor | NTF | RBF 7 6 5 4 3 2 1 0 Figure (6): INTCOW Register of 1661/71 i) RBIF: The RBIF bit corresponds tothe external interrupt change of PORT B where RBIF = i rthe PORT B bits ffom RBS to RB7. ss re RBIF= 1 indicates a change in 37 i (ii) TOIF - RTCC, INT-- Interrupt Flag: INT is an interrupt flag with extemal input and indicates the occurrence of interrupt for INTI imer Interrupt Flag: It specifies the overflow interrupt lag of timer 0 ic. TOIF = 1 denotes the overflow of Ree SPECTRUM ALLIVONE JOURNAL FOR ENGINEERING STupENTs —————_"> > -eoup ab sateen cre Scanned with CamScannerMICROPROCESSORS AND MICROCONTROLLERS [JNTU-KAKINADA] "Tupt enable bit which enables and disables all the interrupts for RBIE = 0 and RBIE =I respectively. INTE: This bit is an interrupt enable bit ie., and enabled for INTE = 1 errup is disabled for INTE «TOE: Its a timer 0 interrupt enable bit , which is disabled for TOIE = 0 and enabled for TOIE ADIE: ADIE is an analog-to- enables them for ADIE ‘digital conversion interrupt enable bit, which disables all the interrupts for ADIE = 0 and (vi) GIE- Global Interrupt Enable Bit: GLE is used to cither disable or enable the interrupts i.e, __ | Interrupt are disabled . 6.3 PARALLEL AND SERIAL INPUT AND OUTPUT | 012. Explain the interfacing of a PIC microcontroller with a PC using parallel slave port. | The interfacing of a PIC microcontroller with a PC using parallel slave por is illustrated in figure. Address_V0 lines Personal >| RE2|CS computer Pont E REL | WR REORD ps }-——___>|_ rps i ps +} ros, oi) = {pats ps f+ +} ros we {bus ps [+ + aps eG pz fp_ +] rw 2 pi je———+]_ rr t po }-—_—————+|_rpo Figure In the figure, a PIC microcontroller includes two ports namely Port D and Port E for transmission of data between PC ‘al microcontroller, The port D is configured as a parallel slave port by enabling bit-t in TRISE register and the pins in port E ‘sas contol pins -e RD, WR, CS for this data transmission. Ia PC wants to write data onto the PIC microcontroller, it fist Wiese the address decoding circuit. Then, VO address decoding circuit, decodes the address given by PC and sets the CS Fino low. Simultaneously, the PC sets TOW pin fow and allows the data to loa through the data bus (D, ~D,) and writes data | the microcontroller. : 13, Explain in detail about synchronous and asynchronous interfaces, | Ans: | Stehronous Serial Interface Synchronous interfaces are mainly used to connect peripheral devices tothe microcontrollers that are relatively within ho ae nina closed system. In thi, the transmitter and receiver are synchronized with a clock signal that i sent Nang ee ta jeige generating the clock signal is efered as master and the other devices which synchronize with it ree ate TH paste generates the clock signal Which is used by slaves to carry out simultaneous transmission and “pon, Look for the SIA GROUP Loco GY on the TITLE COVER before you buy Scanned with CamScannerUNIT-6 (PIC Microcontroller) There are bo main synchronous seri 1. Seriat Peripheral Luterface (SPD) other devices. Muses cajherwcen microcontrotter nd Om ty SPI is a standard for synchronous serial e0 cation wse rtrmultanccvs transmis of dat 9 Henge ye 6 nd an extra [in 1. The mine, ine for output (SDO), fine for input (SDI), another dh aaeeaee een controller (Masten and pe phicral devices (Shiv it supports full duplex communication between host allowable bit rate is 10 Mbits/s slave's, Inte to transfer farce annouints oF data, An additional Slave Select jg SPI promotes no control of software that is suits r ices) tw aveess the device by ($8) mast be conocte to ach sevice (ie the HO pins inerease wth here aa master. Figure (1) shows the block diagram of SPH interface, pie SPI peripheral SPI interface 2K | | sek spo| +s sptfq—Rat —_] spo Figuro (1): Block Diagram of SPI Examples: MCP320XA/D conver ter, MC Inter-Integrated Circuit (PC) Bus FC isa multi-master synchronous serial bus used between ICS and low speed peripherals, It uses one wire for data, anor for clock line and no wire for sirmult travel of data) between ma mission of dat Hence, it supports half duplex communication (one way te is 1M imum allowable bit In this, multiple devices ean be used. ‘masters and share the bus using a simple protocol. The protocol involves transtetion of bits by addressing a particular slave and then acknowledging of its addre to confirm the suecessful reception, the itiates communication by generating a elock signal. In other complex applications, PC operates mode where the target slave provides the seven-bit address for the master to sele. of FC i multimasir - Figure (2) shows the block diagram erface. PIc2a VC peripheral FC imterfuce | Clock (SCL) Data (SDA) «<-> (Master) (Slave) Figuro (2k Block Diagram of HC tntertaco Example MCP98XX temperature sensors, MCP322x A/D converters Asynchronous Serial Interface ‘An asynchronous interlace is a simph ation betwee more peripheral devices operating at iff " les ver Larger Mistans® In this two d 500 Kbits/s. The data tran SPECTRUM ALL-IN-ONE JOURHAL FOR ENGINEERING srapErTs — Sian allowable biti — SIA GROUP x a i Scanned with CamScannerMICROPROCESSORS AND MICROCONTROLLERS (JNTU-KAKINADAI id receiver, The use of nformation from data stream is responsible for synchronization between transinttier = improves the noise immunity and other hazards ofthe system, Since, no clock signal is transmitted. Ret in separate fFames exch of which sccivet Full duplex communication j formation Fe responsible to maintain synchronization of separate clocks in the transmitter and \d reception. colved in separate processes for transiissic The block Pics2 ‘Asynchronot UART interface peripher RX Examples S232, RSA2, LIN bus, RS485 ‘The most widely used asynchronous serial channél is UART(Universal Asynchronous Receiver and Transmitter. 1 provides full-duplex capability by combining the functionality of a dedicated transmitter and a receiver into a single module: 14, Explain FC bus interface structure with a neat diagram. Anst Inter-Integrated Circuit (FC) bus is designed by philips semiconductor company and now calling itas NXP semiconductors, huismainly adopted by the manufactures to make ituse in IC modules and peripheral devices where board-level interconnections ts o be performed. The FC being a synchronous serial protocol, it uses SDA (Serial Data) line and SCL (Serial Clock) line to produce/build a half-duplex multidrop bus having the ability to deal multiple masters and multiple slaves. The SDA line serves the purpose of carrying the transferred data while SCL line puts all the bus transfer operations in synchronization TEC bus finds its use as an intra-system serial bus which can accommodate all types of peripheral devices such as MCUs, data converters, memories, display devices, RTC (Real Time Clock) calenders and GPIO modules which exists in embedded systems, The FC bus provides software addressing facility tots devices with an address field of 7-bit or 10-bit. The single master~ suliple slave topology used in FC protocol adds an advantage to al the evices to act as a master, since it provides collision {Ltccon facility and bus arbitration which are essential to cerry operations in the presence of multiple-masters. The FC bus can support a maximum speed ofS Mbps and short distances (in inches), The inetease inthe distance (in fet) will make the spocitance to increase which results in the reduction of speed making the bus slower and less efficient. The lines SCL and SDA feature which can be attained by ope tas bidirectional multidrop f 1g in either oped-collector or in open-drain drivers. The PC bus topology is illustrated in figure (1)- Figuee (1): PC Bus Topology [ook forthe SIA GROUP LOGO {ff on the TITLE COVER before you buy Scanned with CamScanner‘Fagore (Zt taternal Stracture of FC Bus letertace: Drs doves to comect wr des pends an crface which can generate signalization stated by the FC protocol. Froa Be tons pure, can Ne umn’ thet [FC bes interfive inrorporates two stuft registers namely Receive SR (for receiving! sane Transmit SR (fhe Tumewiting) whack as ss received packets to either self address comparator to kno» ¢ access with the CPU oe condhtions in the channel the master Ser examines the stanas of spare named as star, transfer and stop conti ‘s the data transfer by controlling the bus upon checks ‘Ne channel by using SDA and SCL lines, where the chars!) “\ period. The master makes SDA line low after knowing i! h indicates setting up of a 4. SOP Of 2 Sar condition. The timing diagram of FC signals ® Scanned with CamScannereit < 5 MICROPROCESSORS AND MICROCONTROLLERS (JNTU-KAKINADAI The devices that are connected ww PC bus wall ws will move fo feten mode rel becoming busy. The master can also cer the eh a sat comuition while processing the message and this action is termed as restart condition which 1s useful in altering the ear ietion oF the wrent message, | The PC channel can transfer an S-bit characters hut with an MSH (Most Significant Bit) first, As shown figure (1), data | atatonty ifthe SCL tine is high and when SCL becomes fo a change in the it takes place, The bus is able to carry single * rail character transfer, The master generates a stop condition (P) by making SDA line high without altering the SCL fine which i at high, The gow also illustrates the status OF SDA and SCL fines forall the con spemaster sents the address field ofthe slave wns that takes place between the master and the slave, to which the message has to be sent aver FC bus and the message transfer cers aly after issuing start condition by: the master. The FC message structure is illustrated in the figure (2), sot Moste Aeaoonindgrort Bt ome bd Soe yim 3] camwtea [a] oom [tT freon |S] eee Figure (21: PC Message Structure The last bit ofthe address field contains read/write which represents the transfer action i.e, either to perform read or write te destination slave. All the connected slave devices receives address field sent by the master and checks whether it matches wih their own addresses. 5 The device whose address matches with the address field sends an acknowledgement by raising SDA line indicating the ‘maser to start/nitiate transfer, In write transfer case, the master plays the role of the transmitter by controlling SDA and SCL tes whereas the slave will be the transmitter in the ease of read transfer. 6.4 TIMERS, INTERRUPTS Q16, Write a short note on PIC 16C61/71 timers. Ans: mer 0 PIC 16C61 supports only one timer ie Tener 0 Timer 0 is a 8-bit counter clocked by intemal system clock fx) or extemal clock. These elec! cording to the requirement of prescaling are divided by 2 The extemal clock to timer is shown in figure (I) RAATock | fr (Extemal clock} 4c foe umet 0) Cie Figure (1: External Clock Source for Timor 0 TOLF fag of INTCON is enabled fora timer 0 overflow from OFFHL 10 008, Timer 0 interrupt oceurs when TOIE bit is enabled fora timer 0 overflow with GIE bit of Interrupt Control register (STCON) and is shown in figure 2). Look for ine SIA GROUP LOGO 4 on the TITLE COVER before you buy Scanned with CamScannerfcmotinere (5) Tessar) Timer 0 with Sits GEL [ror re awe [rower An) source Da ire (2h: Timer O Overflow and Interrupt The external clock at Tock 1 synchronized with the intemal clock using on timer 0, the delay circuit which take two eyeles is made to reset andi the cycles are uncounted, -cycle delay when a write operation is executed Timer 0 module increments at leading or trailing edge for an external clock at RA4/Tock 1. mn option register, PSA bit provides the presealing to watchdog timer or timer 0 whereas PSO, PS1, PS2 bits are usedio estimate the pre-scaler value. ue The $-bit maximum value of timer count ean work on large events of interval by using prow 0.,The maximum frequency of the clocking source for timer 0 is 50 MHz. The frequency the frequency of the device. mmable prescaling of tier of the extemal clock may be greater thin ‘The delay of the timer 0 using prescaling is given by, ‘Timer 0 ~ Delay = [Timer 0 ~ Count] x Pre-scaler value x _4 ‘The preload count which shouldbe observed by TOLF interrupt bit afer a timer i wiven by, ‘Timer 0-Preload count = 256 — | Timer O—Dehay As Prescalar prs The rounding error ea be reduced by declaring a nop instruction and adjusting the delay, req red preload count Watchdog Timer Watchdog timer is used avoid the occurrence of the endless lop inthe processor Inde any condition, programming, the watchdox timer once enabled ordis abled, ca not be turned ely wine timed on respes ‘The CLRDWT instruction in statu register or power up procedures set the ti {HiT Wihe exceution of CLOW! is not sequential, then, watchdog timer resets the Zi bit ERI SPECTRAM ALL-IN-ONE JOURNAL FOR ENGINEERING StupeNTs — SIA Group Scanned with CamScannersc opertion of watchdog timer which affecis a 1e PIC power-down mode is shown in figure (3). Watchdog, Timer When CLRDWT instruction Reset PICbis not executed before the time S out period of WOT Ictear time out flag | 638, MICROPROCESSORS AND MICROCONTROLLERS [JNTU-KAKINADA] i ae ers register = |RPO} To | po] Zz | pc | C Set timé out fag when CLRDWT is, executed Figure (3: Watehdag Timer Watchdog timer is driven by the intemal RC oscillator. The PSA, PSO, PSI, PS2, in option register are used to obtain the sogammable scaling ‘The sleep command execution in PIC microcontroller enters it into power down mode and disables the watch down timer ssnel as allows it to run, In status register, Power Down ( PD ) flag is set for an execution of CLRDWT instruction or power on reset. PD flag is made to reset by sleep command, The sleep command is used to execute the instructions in the processor and slowsit to wake from the sleep mode by watchdog timer time out Of7, Discuss the interrupt structure in PIC microcontrollers. Also list the various interrupt sources in PIC 1671. (or) Briefly explain about the different types of interrupts handled by PIC 16C61/71 microcontroller. Model Papert, a7(%) interrupt logic diagram of PIC 16C61 is shown figure (1). INTF- “Interrupt to CPU, oor) Le _ _— Ge Figure (1: Interrupt Logie Diagram ‘There are three interrupts supported by 16C61 and another extra interrupt is ‘supported by 16C71. They are, | |. External Interrupt |X Timer 0 Interrupt | 3. power ciangetterunt 4. ADC Interrupt External Interrupt Estemal ntrrapt isan edge sensitive interrupt which occur fora trasition at pin RBOVINT. Abit in OPTION register “tote tne oinerrpt ie. ier sng ee testo ling de gered. INT inrrpt functions used only before izing RBO in port B. Look for ine SIA GROUP L060 {J} on the TITLE COVER before you buy Scanned with CamScanner€ routine, UNIT-6 (PIC Microcontroller) able (or reset) by interrupe ser INTER, di INTF bit in INTCON is enabled for a interrupt signal an in advance for a processor to wave it from steep mode. 2 Timer 0 Interrupt cerflow interrupt is produced by timer 0 overt a TOIE bit of INTCON shoutg tet FFH to OOH. HN GIE bit When counter/timer 0 overflow occurs from O! A setting) TOIF flag in interrupt control register (INTCON). Hence, is also used for program handling. 3. PORT B Change Interrupt ins X In port B, when a low to high or high to low change occurs orBIF ‘The RBIF flag bit is set when the current pig. interrupt is enabled by setting RBIE and GIE along with the flag bit device from steep mode by configuring the change o, does not match with previous one. This interrupt is used to wake the dev curs when the mismatched of RB4 to RB7 pins of port B. RBIF bit is cleared by reading port B. This interrupt oct Outpt “OR’ ed to get a single output RB port change output. 4. ADC Interrupt RB4 to RB7, a port B change interrupt cca » The ADC interrupt in 16C71 occurs after a complete conversion of analog to digital. This interrupt eccurs by en, the ADIE bit of INT CON and master control bit GIE. ADIF flag bit of ADCONO register represents the end of conversion. GIE bit in INTCON which is enabled internally or externally is used to enable of disable the interrupts simultaneoai Apart from this, another two bits of INTOCN are used to enable or to detect the occurrence of interrupt respective After the éxecution of instruction of interrupt service routine of CPU is executed, other interrupts are served by ena, GIE bit automatically. IE bit disables all the interrupts and gets cleared upon occurrence of RESET operating ‘The programmer needs to initialize the INTCON register prior to occurrence of interrupt 6.5 Pic 167877 ARCHITECTURE, INSTRUCTION SET OF THE PIC 16F877 Q18. Write about the signal description of PIC 16F877 flash microcontroller. Ans: Model Papers, PIC 16F877 is a 40 pin microcontroller consisting of five inpuvoutput ports ie., portA, port B, port C, port D ant? E. The pin diagram of 16F877 microcontroller is as shown in figure (1), 1 2 B RAYANDV , - —¢ RAVANSY,,, + —s — RasTock! —17 RASSBANE 1 REOADANS —9 1 RALATRANG ——t19 PICISEST7 errs OSCLCLKIN 3 @SCLCLKOUT —f14 RCOTIOSOTICKE — 15 ReiTosci.cce2 — te — eonrsr> Si RCESDUSDA i apzpsez 0 (1: Pin Disgram of PIC 16F877/874 URAL FOR ENGINEERING HODES SPECTRUM ALLIN-ONE JOURNAL bed ENGINEERING StubeNTs >. enouP @ em _ ae J Scanned with CamScannerMICROPROCESSORS AND MICROCONTROLLERS [JNTI al OF PIC 16F877 can be categorized into Unree groups, The Port pins i.e 33 VO pins belonging to port A, port B, port C, port D, port E. ‘Two pins lor supply voltage *V,." and two pins for reference ground voltage *V, ‘Two oslo pins input and output) OSC/CLK,, and OSC2ICLK,,,, anda master clear reset input pin (NICLR/V,»/THV) The pin description for each ofthese pins is piven as, 1p Supply Voltage): PIC 16F877 microcontroller consists of two supply voltage (V,) pins with pin numbers LI and 32, (Reference Ground): Two reference voltage (V,) osCUCLK,, and OSC2/CLK, ‘ninber 13 and can be used as source input for extemal (ACLRV,/THY): MCLR is a master clear reset input which is acti pins with pin numbers 12 and 31 are used as ground, ‘our? These pins serve as oscillator connections in crystal oscillator mode. OSC1/CLK,, is pin clock. OSCICLK yy in number 14 which serves as output to the oscillator at one-fourth of OSCI frequency in RC node. low, Its pin number is 1 and can also function as ogamming voltage input. Fert A: Port A isa bi-directional inpuvoutput port consisting of 6 pins from RAO to RAS with pin numbers 2 to 7. The pins 2A0,RAI, RA2, RA3 serve as analog inputs ANO, AN1, AN2 and AN3 respectively. Port: Port B is a RAO/ANO (Pin 2) : . RAV/ANI (Pin 3) RAZ/AN2/V pep (Pin 4) — This pin performs an alternate function of negative analog reference voltage. RA3/AN3/Vjc, + (Pin 5) ~ This pin performs the alternative function as analog positive reference voltage. RA4/TOCKI (Pin 6) ~ This pin acts as clock input for timer 0 timer/counter (TOCK1) RAS/SS/AN4 (Pin 7) — This pin can either function as analog input 4 (AN4) or Slave Select (SS) for the Synchronous Serial port. rectional 1/O port consisting of 8 pins from RBO to RB7 with pin numbers 33 to 40. RBO/INT (Pin 33) ~ This pin serves as an external interrupt RB3/PGM (Pin 36) It functions as a fow voltage programming input RBG/PGC (Pin 39) ~ Its alternative function is a serial programming clock RB7/PGD (Pin 40) ~ This pin also act as a serial programming data pin RB4 to RB7 supports an additional feature of interrupt on change. Por. Ports is a bi-directional /O port consisting of 8 pins from RCO to RC7 with 15 t0 18 and 23 to 26 as their respective Fit numbers. = RCO Pin 15) ~This pin either functions as output to the timer 1 oscillator T1OSO or a clock to timer 1 = RCI (Pin 16) ~This pin could be input to timer 1 oscillator or input to capture 2 CCP2 or output to compare 2 oF output to PWM: RC2 (Pin 17)~ This pin is either capture I input or compare | oulpat or PWMI output RC3 Pin 18) This pin ean aet a8 synchronous Serial clock ipuWoutput for both SPL and FC modes. RCA/SDYSDA (Pin 23) ~ Its SPI data in SPT mode or data VO in FC mode RCS/SDO (pin 24) ~ It acts as output to SPI data in SPI mode REGTXICK (Pin 25) ~ This ean be ither a USART asynchronous transmit or a synchronous clock, is as a USART asynehr Jhronous data, ver or RETIRXIDT (Pin 26) ~ THis Pi Look for the SIA GROUP Loco QB o1 the TITLE COVER before you buy Scanned with CamScannera processor bus act as a parallel shave poy UNIT-6 (PIC Microcontroller) a he mie Port-Di Pore-D is a bicdireetional 1O port which when interfaced S10. nective: consists of § pins from RDO to RD7 with pin number 199 223427 0" soo 10s their corresponding in mun, Port-E: Port-E is a bi-directional UO port consisting of 3 pins ie ee| for parallel slave port or as an analog Pata, trot for parallel slave port oF as an analog input ay, REO/RD/ANS (Pin 8) ~ This pin can either serve a5 2 Te slave port or analog input Atyy REIAVRYANG (Pin 9)—Thispineanecitherserveasa THE CONT tay RE2CS/AN7 (Pin 10) — This pin can either serve a8 2 sets aa A8. Explain about the architecture of PICTSF77 with the helP Ani Mode Papert gy, grate address and data buses are used for progr. ‘The 16F877 PIC microcontroller employs Harvard Architecture i.» S°P2 and data memory (Data memory for special function registers and internal RAM (ii) EEPROM data memory ii) Program memory, interrupt vectors . constant data and flash memory Figure represents the architecture of PIC16F877 microcontroller. Toe aoe Ey Syeteosot Seria pot usART lot ah ADE Team Tim cori Figure Program Counter and Internal Program Memory Bus 16F877 PIC controller supports fash program memory of size8k and length -bi fora 13-bit address. Thus, a program counter of length 13-hit is used i reenwotin a reset points to the address location 00H. The location 00041 which st program counter provided the interrupts are enabled, 1g Of the 8k memory desi rogram counter, after eve ‘ores the interrupt vector is automatically loaded into Internal Data Bus Internal data bus is of 8-bit wide, which connects revisters, RA 'sters, RAM, internal peripherals an 7 STATUS register exist in internal data bus, since both are of 8-bit wide naeiinanecaaael SPECTRUM ALLIN-ONE JOURNAL FOR ENGINEERING stupj - “rane : ents "sia croup & EIST at Scanned with CamScanner20, mn 620 — in about the Inte CROPROCESSORS AND MICROCONTROLLERS IJNTU-KAKINADA} Expl mm oe ‘Upts in Pictorary | The 16F877 PIC mictocontea roller supporis cist? total of 14 interrupt sources. The following are the types of interrupts in | _Esteral interrupt RBOANT PORTE change interrupt Timer0 overflow interrupt and Peripheral interrupts. The periheral interrupts are corresponding tothe follow ing, Parallel slave port USART * Timer! and Timer? overflows AD converter {Synchronous serial port 4 CCPL, CCP2, SSP bus collision and EEPROM write operation interrupt. Interrupt Control Register (INTCON) The INTCON register of 16F877 is shown in figure cae | ree [row [ore [rote | ror | ate | nar Figuro: 16F877 INTCON Register The flags in INTCON register are explained as follows, GIE + Global interrupt enable bit IGE => Enable all = 0 = Disable all 2 PELE — Peripheral interrupt enable bit IPE able all unmaskable peripheral interrupts = 0, = Disable all the peripheral interrupts TOLE ~> Timer0 - Overflow interrupt enable bit M, TOI = 1 => Enable = 0 = Disable INTE.-5 RBOMNT extemal intzrupt enable bit Winre, Enable = 0 = Disable RIE Rit port change interrupt enable bit HERBIE = 1 > Enable = 0 = Disable Look for the SIA GROUP LOGO 4h on tho TITLE COVER before you buy Scanned with CamScanner6 (PIC Microcontroller) 6. TOIF — Timer-0 overflow interrupt flag IfTOIF = 1 => TMRO register overflow = 0= No overflow of TMRO register 7. INTF > RBO/INT extemal interrupt flag If INTF = => Occurance of external interrupt = 0= No extemal interrupt 8. RBIF > RB port change interrupt flog bit IERBIF = 1 = Atleast one of RB7 to RBS lines changed their state = 0 = No change in state Along with INTCON register, 16F877 also supports different types of peripheral interrupts and are mentioned beloy, 1. PIL register PIE2 register PIRI register, and PIR2 register, Here, both PIEI and PIE have individual interrupt enable bits, but PIR and PIR2 have individual interrupt fg bi, 1. PIE Register Here, RCIE => USART receive interrupt enable bit ‘TXIE = USART transmit interrupt enable bit CCPHE = CPI interrupt enable bit 2. PIE2 Register Baia 6 8 4 3 2 1 o pspie | ADIE | RcIE | TxIE | spre |CCPIIE | TMR2IE| TMRIIE PSIE = Parallel slave port read/write interrupt enable bit, ADIE => Analog to digital converter interrupt enable bit 'SSPIE => Synchronous serial port interrupt enable bit TMRZIE => TMR2 (o PR2 match interrupt enable bit ‘TMRIIE => TMR1 overflow interrupt enable bit. Bit 7 6 5 4 3 2 1 0 EEIE | BCLIE : CcPaiE Here, 1,2, 5, 6 and 7 bits are unimplemented, EEIE => EEPROM write operation interrupt enable BCLIE => Bus collision interrupt enable CCP2IE = CCP2 interrupt enable bit + always kept clear. SeEerqan GULHVONE jouRNal FOR ENGINEERING SrabeNRS oop oh Scanned with CamScanner[ON FU AKIMADAL MICKOPROK z ICR SE rneame ' nit L ~ 5 1 ‘ 2 ' [Pee [= [a [em fr AND MICROCON FROLEE HE 0 Heres Parallel slave port re rst Wovrite interrupt flay, ADIF-=> Analog (0 digital converter interrupt fay 5 USART receive interrupt flay, USART tran pt flay NI ssPiF =3 Synchronous serial port interupt fag CCPIIF => CCP interrupt Nay MR2IF => Timer 2 to PR2 mateh mferrupt flag TMRIIF = Timer! overflow interrupt flag, {PIR Register Bits_7 6 5 4 3 2 1 ° ccna BCLIF Here, The bits 1, 2, 5, 6 and 7 are made ‘0", jc., cleared so, called unimplemented bits, EEIF => EEPROM write operation interrupt fag, BCLIF => Bus collision interrupt flag CCP2IF => CCP? interrupt flog. GROUP LOGO ‘on the TITLE COVER before you buy Look for the SIA Scanned with CamScanner