b. FULL ADDER: Full adder is a MSI circuit that adds two input bits and carry Form the previous stage and out a SUM bit and CARRY OUT bit. A and B are the main bits. carry from the previous stage, SUM produced is: in is the sum 4 AB Cin + AB Cin + ABCin = APEBDCin Camis the output carry bit and is: Cout = ABCin + ABCin + AB Cin+ ABCin = AB +Cin (AB + AB) = AB + (ADB) Cin 2. Half Adders and an OR gate is required to implement a Full Adder.a an ad & y 8—19) Mat -Aaser Fig 1.3: Circuit Diagram of Full Adder using 2 Half Adders Table 1.3: Truth Table of Full Adder INPUT ouTPUT A B | Ci | SUM | Co o | 0 T 0 1 o | 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 FULL SUBTRACTOR: A full subtractor is an arithmetic circuit that subtracts two bits and a borrow and difference bit is generated as output. This circuit has three inputs and two outputs. D=XYZ+XYZ+XVZ+XVZ B=XY+XZ+YZ lalf Subtractors and an OR gate is required to implement a Full SubiractorCoe Half Subtractor Half Subtrector Bout Fig 1.4: Circuit Diagram of Full Subtractor using 2 Half Subtractor Table 1.4: Truth Table of Full Subtractor INPUTS x Y Z D B 0 | 0 0 0 0 of} 1 1 0 1 0 1 1 | 0 1 1 0 1 1 0 0 1 0 I 0 1 0 0 1 1 0 0 0 1 I 1 Il I¢. PARALLEL BINARY ADDER: For performing the addition of binary numbers with more than one bit, more than one full adder is required and the number of Full Adders depends on the lel Adder, is a combination of Multiple Full Adders and is used mber bits. Thus, a P for adding all bits of the two numbers simutltancously. By connecting ‘n’ number of full adders in parallel, an n-bit Parallel Adder can be constructed. From the below figure, it is to be noted that there is no carry at the least significant position, hence we can use either a halfadder or make the carry input of full adder as zero at this position. Boo BAe [J—li di J cou} pun [Se Se] run [Se Se} Fun [ee Corl rut oie adder | Adder Adder adder Se S: st So Block Diagram of Parallel Binary Adder _ The following figure shows a Parallel 4-bit Binary Adder, which has three full adders and one- half adder. The two binary numbers to be added are ‘A; Az A Ao’ and “Bs B By Bo’, which are applied to the corresponding inputs of the Full Adders. This parallel adder produces their result as “Cz $3 S2 $1 So’, where Cs is the final carry. Boo Bs | | | | & Cany Cary Cany Full cs Full c Full oo Half [Cis Adder Adder ‘Adder Adder L . ig 1.6: Circuit Diagram of Parallel Binary AdderPROCEDURE 1. Make 2 half adder and 2 half subtractor circuits discussed in previous part and appropriate ICs, Place them properly on their respective places. 3. Make the connections as per the circuit diagram, 4. The circuit can be verified using various values of inputs and then testing the values of output as per truth table. PRECAUTION! 1. Circuit should be properly connected. 2. Do not short circuit in the trainer kit during operation. 3. Wires should be held by their heads while being removed else they may get damage.