EXPERIMENT No. 5 AIM: To Analyse and Implement SR, JK, T-type and D-type Flip-Flop using logic gates. APPARATUS: Digital trainer kit, its associated componer THEORY: S-R Flip flop: It is required to set or reset the memory cell in synchronism with a train of pulses known as clock, Such circuit is referred to as a clocked set reset (S-R) FLIP FLOP. Also, the circuit responds to the input signal only if the clock is present. : ig 5.1: S-R Flip Flop ‘Table 5.1: Truth Table of S-R Flip Flop ‘Outputs Ss R CLK on, x 0 0 ot Qa(No Change) 4 0 T T mean d 1 0 T 7 i 1 T ‘Ambiguous If Sy before the clock pulse i.e., Qn1=Qn. 0 and CLK is applied, the output at the end of the clock pulse is same as output 4J-K flip flop: The uncertainly in the state of an § R flip flop when Sq = Ry = | can be eliminated ' by converting it into a J-K flip flop. The data inputs are J and K which are ANDed with @ and ' G to obtain $ and RCLK Fig §.2: J-K Flip Flop Table §.2: Truth Table of J-K Flip Flop ; x cK OUTPUT Qoet 7 0 CLK Qa (No Change) 0 t | T ie T 0 T ' 1 1 T Qu (Toggles) D -Type flip flop: The circuit diagram of D type flip flop shows that it has only one input reference to as D-input or data input. It is truth table shows that the output Qos at the end of the clock pulse equal the input Ds before the clock pulse. Fig 5.3: D Flip Flop‘T—Type Mip Mop: Ina J-K flip-flop, ifJ = K, the resu able 5.3: Truth Table of D Flip Flop ‘Output D CLK Quit p—--- 7 —— 2 0 aay 0 18 Mip flop is referred to as a T-type flip flop. It has only one input, referred to as T-input, A truth table shows that if T-1 it acts as a toggle switch. For every clock pulse, the output Q changes. Fig 5.4: T Flip Flop Table 5.4: Truth Table of T Flip Flop Output T CLK Qu T ieee ee 0 T Qn PROCEDURE: 1, Take the IC’s numbered 7404, 7408, 7432, 7486, 7400, 7402. 2. Place them properly on their respective places, : 3. Make the connections as per the circuit diagram, 4, The circuit can be verified using various values of inputs and then testing the values of output as per truth table.> > 5 5 PRECAUTIONS: 1. Circuit should be properly connected Do not short circuit in the trainer kit during operation Wires should be held by their heads while being removed else they may get damage.wewwv vvv wv wVveodaodgyY “Se ww EXPERIMENT No. 6 AIM: To Analyse and Implement SISO, SIPO, PISO and PIPO Shift Registers u flop and logic gates. ng JK flip APPARATUS: Digital trainer kits, logic gate & flip flop IC’s, connecting wires. THEORY: SISO Register: The shift register, which allows serial input (one bit after the other through’ a single data line) and produces a serial output is known as Scrial-In Serial-Out shift register. Since there is only one output, the data leaves the shift register one bit at a time in a serial pattern, thus the name Serial-In Serial-Out Shift Register. The main use of a SISO is to act as a delay element. a ® we @ TA FA Fa a seat r 1 seu DALAT : 1 af) ef mows i ‘ on dex |@ax | peun par I x ais ate 2 a, a, |_ae ar am Fores SO RCSTER] Fig 6.1: Circuit Diagram of SISO Register ‘Shift Register “Fo [ol olf o nLofte]o +fe>Tr [Tee to], To Aa QB CRD Data Movement in SISO register 6.2: Data Shit i SISO RegisterSIPO Register: The shift register, which allows serial input (one bit after the other through known as Serial-In Parallel-Out s| a single data line) and produces a parallel output register. The logic circuit given below shows a serial-in-parallel-out shift register. The circu Consists of four D flip-flops which are connected. The clear (CLR) signal is connected in addition to the clock signal to all the 4 flip flops in order to RESET them, The output of the fist flip flop is connected tothe input of the next Nip flop and so on, All hese flip-flops are synchronous with each other since the same clock si al is applied to each flip flop. They are used in communication lines where demultiplexing of a data line into several parallel lines is required because the main use of the SIPO register is to convert serial data into parallel data - - ti , 18 Foe a re : You a ox ax | 5 er ah ax a an facck | se —f > FRAT ORT TS) sect Fig 6.3: Circuit Diagram of SIPO Registera ee ee ee 4 PISO Register: The shift register, which allows parallel input (data is given separately to known as each flip flop and in a simultaneous manner) and produces a serial output Parallel-In Serial-Out shift register. A Parallel in Serial out (PISO) shift register us used to convert parallel data to serial data. : i aa mm hx re q La sas a La] mr. | | [a] (“| & aA INSERAL OTIS ccs] Fig 6.4: Circuit Diagram of PISO Register PIPO Register: The shift register, which allows parallel input (data is given separately to manner) and also produces a parallel! output is known as each flip flop and in a simultaneous Parallel-In Parallel-Out shift register. A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like SISO Shift register it acts as a delay clement. PARALLEL DATA DS ps De DI >of I y cu | Fig 6.5: Circuit Diagram of PIPO RegisterProc EDURE: Take the IC's mentioned in apparatus required. Place them properly on their respective places Make the connections as per the circuit diagram The citcuit can be verified using various values of inputs and then testing the values of output as per truth table PRECAUTIONS: Circuit should be properly connected Do not short circuit in the trainer kit during operation. Wires should be held by their heads while being removed else they may get damageEXPERIMENT No. 7 AIM: To Analyse and Implement Synchronous BCD Decade counter using J-K flip flop: a. Mod ~ Up Counter b. Mod ~ Down Counter APPARATUS: Digital trainer kits, logic gate & flip flop IC’s, connecting wires. - THEORY: Synchronous binary counters can be able to count either i increasing or decreasing order. In a count-up mode, the counter value sequentially increased and in a count down mode the counter value sequent lly decreased. a, Mod-Up Counter: As the input clock pulses are applied to all the Flip-flops in a synchronous counter, some means must be used to control when an FF is to toggle and when it is to remain unaffected by a clock pulse. This is accomplished by using the J and K inputs for a 4-bit, MOD-16 synchronous counter. Table 7.1: Truth Table of Mod-16 counter Count[[O [C [BIA 0 o0};o}olo 1 o}o}o}4 2 o}oli}o 3 OF Oe aiet 4 of1fofo 5 ofijo}i 6 OF) | ihe Zz olr{i}i 8 T{o][o|o 9 1 |0|0|1 10 [iit 10] 1|0 14 ttols{1 2 |{t]/1]olo 13) | 4] Ol wifi tatato 1 fia fatata 0 ofololo For a 4-bit (MOD-16) synchronous counter circuit, to count properly on a given NGT (negative transition) of the clock, only those FFs that are supposed to toggle on that NGT should have J Each FF should have its J and K inputs connected so that they are HIGH only when =k the outputs of all lower-order FFs are in the HIGH state.Fig 7.1: Circuit diagram of Mod-16 up counter b. Mod-Down Counter: As the input clock pulses are applied to all the Flip-flops in a synchronous counter, some means must be used to control when an FF is to toggle and when it is to remain unaffected by a clock pulse. This is accomplished by using the J and K inputs for MOD-8 synchronous counter. ig 7.2: Circuit diagram of Mod-8 down counter ‘Table 7.2: Truth Table of Mod-8 counter B [A Count 1 1 0 0 1 1 0 0 elelele|—|-|—|-|4) l—elesafufafoPROCEDURE: Take the IC’s mentioned in apparatus required 2. Place them properly on their respective places 3. Make the connections as per the circuit diagram 4. The circuit can be verified using various values of inputs and then testing the values of output as per truth table, PRECAUTIONS: 1. Circuit should be properly connected. 2. Do not short circuit in the trainer kit during operation, 3. Wires should be held by their heads while being removed else they may get damage.EXPERIMENT No. 9 AIM: To Analyse and Implement a simple Three-bit ripple counter. APPARATUS: Digital trainer kits, logic gate & Mlip flop IC’s, connecting wires. THEORY: Ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop drives the clock input of the following flip-flop. A 3-bit Ripple counter using a JK flip-flop is as follows: Fig 9.1: Circuit diagram of 3-bit Ripple counter In the circuit shown in the above figure, Qo(LSB) will toggle for every clock pulse because JK flip-flop works in toggle mode when both J and K are applied 1, 1, or high input. The following counter will toggle when the previous one changes from | to 0. Table 9.1: Truth Table of 3-bit Ripple Counter 5. Ti 6. Place them properly on their resp ke the IC’s mentioned in apparatus required. tive places, 7. Make the connections as per the circuit diagram.8. The circuit can be verified using various values of inputs and then testing the values of output as per truth table PRECAUTIONS: 4. Circuit should be properly connected. 5. Do not short citcuit in the trainer kit during operation, ' 6. Wires should be held by their heads while being removed else they may get damage. , i » , 5 ~ervrvee