FUJITSU MICROELECTRONICS 236 D mm Agu FUJITSU AAT ‘MIGH-SPEED C¥OS SINGLE-CHIP 4-BIT MICROCOMPUTER ‘The Fujitsu MBSSSOOH sortes CMOS single-chip 4-bit sicrocosputer family is a high-speed version of ‘the conventional HB88500 series. Its architecture and instruction set are sane as the ¥B88500 ries, but its minimus inatruction execution tine 4s reduced to 1.5 us min. using an 8 Miz crystal for external clock with a prescaler. (at 4 Mls, without prescaler) HIGH-SPEED CMOS ‘SINGLE CHIP 4-BIT MICROCOMPUTER ‘Tho W988500H series consists of the YBSBSOIH, HBs8503H, and MBSBSOSH. Farther all devices have @ wide voltage version (3.8V to 6.0V: A-version). ‘The MBSSSOIN and MBSESOSH contain a 4K by 8-bie ask ROM (program mezory) whereas HBS8S03H con~ tains « 2K by S-bit mask ROH. Besides the on-chip 256 by S-bit static RAM (data menory), each dovi~ ces have 36 1/0 Lines (including a sertal port), fan 8-bit tiser/eounter, and a clock generator. ‘They are fabricated by the silicon-gate CMOS Process, the HBGES0OH caries is packaged in a 4z-pin plastic standard, shrink DIP, 48% plastic flat package. They operate vith a single 45°V povor supply and a 4 Miz clock without @ prescaler (or 8 Miz clock with prescaler) over the teaperature range of ~40 °C to #85 °C. (20 °C to 470°C for « A-version) (GHOS technology allovs the device to operate with low pover dissipation (12 aA max, at 2 Mls), and further the standby function enables data reten tion with lover current (10 yA max. at Vog = 6 ¥). developnent of the HBS8SO0H series , Fujitsu provides the HB88400/S00 jebler and host-emulator which run on the P/-86 or PO-DOS machines (cross-assenbler also run on the Tntellee series III HDS), and the HB2115 series evaluation board ayatea, and the 1NB80508H piggyback EPROM evaluation have. exter HBN27C64). These developaent tools enables users to mininize their devolopsent time and cost, 2273 3?497b2 OOL2361 9 mm oe MB88500H SERIES ‘T867-4871: Janusey 1987 W@SRS0LN-P/S03H-P/S055-P ‘42-PIN PLASTIC STANDARD DIP (D1P-42P-H01) ‘MBasSOLN-PSH/S03E-PSH/SOSH-PSH 42-PIN PLASTIC SHRINK DIP ((prP-42P-402) MB8ASOLE-PF/SO3K-PF/SOSE-PE ‘49-PIN PLASTIC FLAT PACK (FT-4aP-102) wsasosx—c/ wmsasosn—cr/ protect the Inputs against danage ue to high statle voltages or trie flelds, However, Te te ade ‘thet. moraalpracautfone be taken t svold wppllcation of any vel higher “than saxiaua rated voltage to. Wile high lepedanes elrcultyFUJITSU MICROELECTRONICS 236 D m@ 3749762 0012362 0 mm T49-19-Uy ATTET ‘ees00H SERIES FUSTTSU ‘aa FEATURES + CMOS Single-chip 4-bit Mlcrocomputer «+ Program Nonory: 0 MBSGSOLK, MBSBSOSH: 4 Kx Sbit cask ROM ‘0 MBSESO3H 12K x QBit ask ROH + 36 1/0 Lines: 0 K-Port: s-bit parallel input only 0 Poort: G-bit parallel output only 0 O-Pore: S-bit parallel output only fo RPort: Four debit parallel or 16 individual input/output © C-Port: Sorial 1/0, external interrupt input, timer/counter input, and tining ‘output Five Selectable Output Port Types for O-, Pe, and RePorts with task Option Standard open-drain Standard pullup High-current open-drain High-current pullup 12¥-taterface open-drain (P-Port only) + On-chip Mask Programable PLA (Programmable Logic Array) for Data Conversion fat O-Port (HB88501N, HS88S03) bit Progranmable Tiner/Counter with Two Clock Hodes © Internal clock (Timer) 0 External cleck (Counter) + Serial 1/0 with Serial Buftert ft 4=bie, 1 Software 5 ‘+ Taree Programmable Clock Mod (o Internal clock © External clock © Softvare clock + On-chip Glock Generator with 2 Mask Options: 0 External crystal/eeramic resonator or axternal clock drive (© External RO-network or external clock drive + Mask-option Divide-by-tve Glock saler for Expanding Clock Range + Single Level Four Prior Source Maskable Interrupt: fo External 0 Clock ‘9 Tiner/counter overflow © Serial buffer full/eapty j-nesting Levels for Subroutine Calls 2274FUJITSU MICROELECTRONICS 23E D MM 3749762 0012363 2 mm T49-19-4y ‘MBS8S00H SERIES FUSTTSU FEATURES (Continued) Instruction Set: Upward compatible the 4368500 series instruction fo Nusher of instructions! 76 © Instruction length/oycle: 1 byte/1 cycle (82%), 2 bytes/2 cycles (17%), 2 byee/3 exele (2%) © Execution tine 1.5 us ain, using 8 Wis clock with prascaler a On-chip Pover-on Reset Gircute Mask~option Standby Function oNo standby function © Software~initiation standby function ‘Two aask-option Output States During Standby: © Hold © High impedance ‘Two Softuas o Tale © Stop Selectable OseiIlator sta During Standby Mask-option Standby-off Reset Mask-option Wateh-dog Timer Function Low Power Diss{pation: @ 12 what Vog = 5.5 V at fe = 2 Miz max. (Active node) © 10 uA at Voq = 6.0 V at fc = 0 Mis max. (Standby mode) Single Pover Supply: © Standard version: 4.5 V to 5.5 V (Active mode) 3:5 V to 6.0 V (Standby node) © A-varsion 2315 V to 6.0 V (Active wode) 315 V to 6.0 V (Standby moda) Wide Operation Teaperature Rangs © Standard version: Ty= ~60 °C to © Avveraion 2 Ths =30 °C to +70 °C Silicon Gate CHOS Technology pin plastic, © 42-pin plastic 0 4a-pin plastic flat package: Suffix Powerful Davelopeont Support: © CP/H-86, PC-008, or Intellac series TIT HDS eros (07413 012 /stncona%-4010/840S215-A010) © GP/Y-86 oF PC-DOS host enulator software for monitoring evaluation board and ayu~ bolic debugging (sH07415~c022/sen0n0x-0020) © HB2115 series evaluation toard (01, ~02, 06 and, ~StA) for software debugging © HBB8508H CHOS piggyback EPROM evaluation devices jeabler 2278FUJITSU MICROELECTRONICS @88500H SERIES Fig. 1: PIN ASSIGNMENT Suftix -P and -PSH Gop view) m Gi 2B op md: Sip Stier Re 3 408 a3 y de 3B ke ie qs ep et m de a7B fo mod? seb Fs mide 30 ee mds MB mt niadio S38 0 preci 2B or ro'diz SIE 06 Hodis Sof os mde 3B ob Is 288 03 fg iP oz Fa asp oF 18 23B 00 Fa EB so 20 3p sr a zap 80/0 sattix -PF (rep View) lay ge 33 guide Sere Bl. (is 37 ° oe 36} 96, o7 Po PL Bm Ps 0 EEABOABOR mi m0 89 23€ D M@ 3749762 0012364 4 mm TEE FUSTTS une TH49-A-UgFUJITSU MICROELECTRONICS 236 D mE 3749762 0012365 b mm T49-19-Yey. en tsesoon SERIES FOSITSU Se Fig. 2: HBSGSOL AND IsASOSH LOGIC STIL w ¥ 4 x so 3-0} Input only clock a pore. (K-Port) x Ps -PO Output only * pore. (P-Port} Device [ REET 03-00] Gutput only control ‘ PLA pore START woseso1r or -o4 J” (o-Pert) teassose | 4 i > aa -20 “ Control | TE <> are | 1/0 ports port 3 ‘ @e-Pert) eo eine st 3 50 A> mime 2217236 D Mm™@ 3749762 0012366 8 mm FUJITSU MICROELECTRONICS TH49-19-4Y. AUTH FOSITSO ‘gsasoon SERIES Fig. 31 MB80501R AND MBASOSE BLOCK DIAGRAM (204-10) (2206-0) (see) out 3/4) ‘essa iehoeg fensseael tear eet (800) Lancs frou) ies (ot vou eu'tozoto yoga gous vin aes og'tg tac vig ey freien i Wr eounty curse CaeFUJITSU MICROELECTRONICS 23£ D M™ 3749762 0012367 T mm 49-19-44 EN vmsesoog sexes FUITTSU sunt Fig. 6 HBOOSOSH TOGTG STABOE t q ‘ we ——f ks xo Input only clock port (K-Fort) x< P3-P0 Output only fi post (PoPort) Device ‘ESET 03 ~00 ‘Output only conteel * post (O-Port} stage or -06 moseson [6 xm — K—+—> RS -RO : contrat | FE_ —— > Rr 8 1/0 ports port s/t <——) 4 (R-Port) > nia x — 3 » —— A> mena 2-279236 D MM 37497b2 0012368 1 mm FUJITSU MICROELECTRONICS. T49419-44- ana FUITSU measoon SERIES Fig. 51 MBSQSOSK BLOCK DIAGRAM (4-0), eet a) ‘Ppp aun fnasen fanaa cae Sa luisa seas Soe ei ssnrza a 2260FUJITSU MICROELECTRONICS 23E D M™ 3745762 0012369 3 mm PIM DESCRIPTION T49-19-H4- sana ‘MBesS0OH SERIES FUJITSU eae Fig. 1 and Table 1 show the pin assignment and pin description of the 288500 series. ‘Table 1: PIN DESCRIPTION syabot | Pin No. | Type Name & Function = Fower Suppl Yoo ‘a2 —] =] 250 Be power supply pla cas) Vas 21 | >| Ground pia a2 = oleek x Té——]E-] baciifator Tapatt Taput to the Taverting auplifier thai 6) fores the on-chip oscillator. An external crystal/ coranie resonator or RO-aetvork 1s connected between ‘the EX and X pins. Either of these two oscillation types can be selected using sask option. Wien an exter nal oscillator 1s used, the EX pin receivas the exter nal oscillator signal. ‘This pin is a non-hysteresis input when the crystal/ corasic oscillator is selected, and a hysteresis input ‘when the RG-network oscillator is selected. ¥ Ti] 0] taciiTator Oatpatt output of the Taverting applifier en ‘that fores the on-chip oscillator, and input to the Anternal clock generator. Au external erystal/corantc Resonator or RC-network is connected between the EX and X pins, Either of these tvo oscillator types can be aelected using sack option. Wien an external osciliat 45 used, the X pin should be left open. aaeror i aay Wesott Tits pin Function as an external reset input oF power-on reset output. External reset input: A reset input to the internal reset circuit, A lov level on the RESET pin forcedely ‘the HOU's operation, and initializes its internal ‘After the RESET pin returns high, the HCU rz Starts execution of program froa address #0. The RESET pulse aust be lov for at least two instruction cycles While the oscillator ts stably running after pover-on. This pin 1s a hysteresis input with an internal pullup zesitor. An external capaciter from the RESET pin to ‘the VSS pin (and the internal pull-up resistor), whose tine constant should be greater than the reet tine required (12 clock periods) composes the external re ‘cdreule.FUJITSU MICROELECTRONICS 23E D MM 3749742 0012370 T mm EF voeasoon seames FUTTS ‘Table 1; PIN DESCRIPTION (Continued) 9. gnu tyatel [Fin No. | ed Nase & Function Device. Gonecol_Goneined). ae Soar ant SER cent GR i Tis SEG 38) reset control circuit. Norsally this output is high during the active operation except the reset mode. The ising of the VOC voltage after pover on outputs a lov Level. on the HESET pin, and then autozatically returns Clock periods after the oscillator stares by This pin is a hysteresis input vith an internal pullup resistor. EMRE | —|T-] Bearer 0 standby releaae input to the Taveraal standby ae control and status registers that control and wonitor the on-chip standby control circuit. A high level on fhe START pis during the scandy sede cots the stendby lease flag (STF) in the standby status athe atandby enable flag (S73) in vhs scandy control register, and triggers the standby reli sequence to return the HOU to the active sods. Zefore the START pulse is applied, the VCC voltage must retard to the-active operation range vhon the battery backup is used. Also, the START pia must be lov before the standby odo is initiated. 8 (logical level) is reflected in the dnput (START) flag (STIF) in the stand by status register, regardless of during the standby node of active coda, and besides even vhen the standby function 18 not mpieseated using gask option. There fore, the START pin state can be sensed by roading the standby statue register using IN instruction (with 8). ‘This pin is « hysteresis input with an internal pull- dom resister. TRd | 19] 1] interrupt Maquasts A waskable external interrupt Tapue 9) to the on-chip interrupt control elrcult. The falling fedge of the TR pulse sets the external interrupt Fequest flag (IRF) in the intecrupt flag register ro gardlogs of enabling or disebling the external inter Fupt. If the external interrupt is enabled in advance by EN {astruction, the interrupt sequence starts at once. Otherwise, the IRF fleg is internally held Unterrupt source. Also, the IRQ pin state (logical level), which is reflected in the external interrupt Anput flag (IF) regardless of enabling or disabling thq external interrupt, 18 testable using TST instruction | (nen IR =, IF 2 1; othervise IF = 0.) ‘This pin is a hysteresis input with an internal pullup resistor. 2282FUJITSU MICROELECTRONICS 23£ D m™ 3749762 0012371 1 mm FYI ‘xo sasoon SERIES FUSTTSU ania ‘Table 1: PIN DESCRIPTION (Continued) Symbol Pin Nov "13P Nene & Function TO=Pore, ‘(Goatian ay Te | Tiner/Coumtert Ga external count clock Taput to tha oe chip S-bit tiner/counter. The falling edge of tho TE pulse incresests the tiser/counter by one bit, when the external count clock (counter) Instruction programing the tis ‘Select register using QUT instruction (with Y= 8). Also, the TC pin state (logical level), hich is reflected in the timer/counter input flag (TCIF) in t ‘Eimer/counter prescaler select register regardlacs of enabling or disabling the external count clock (counter node, is testable by reading the prescaler select register using IN instruction (vith Y= 3). (When TC = L, TOIF = ly othorvise TCIF = 0.) This pin is inactive 2 count clock input when the external count clock ode is not selected or tha timer/counter A disabled by DIS tnstruction or reset. is input with an internal pullup ey 170 | SHIGE Giock/Fiaing Outputr_One of the ohife clock Tapa (G0), shige clock output (SC), or synchronous timing output (T0) de enabled using EN instruction. 1 | 3g: 1) shiet clock input to the on-chip serial port! When the external ahict clock ode 1s enabled for the serial port, the falling adgo of the external &C clock shifts the contents of the Serial buffer one bit right (from HSB ‘This input ie inactive hen the exter: nal clock node is not selected or the serial port disabled by DIS instruction or pin 4s a hysteresis input. 2) Shigt clock output from the When the incernel shite elock aode ta enabled 3. Tn this mode, jected is output tho internal tining signal onto the &¢ pin for synchronization, 0 | 7%; synchronous timing output: When the timing output As enabled, the internal tining signal (which is generated by the on-chip state counter outputs, #1 nd 42) {s output onto the 70 pin, By DIS instruc~ tion or reset, the TO pin 1s disabled and stops Assuing the timing output. ‘This pin 4s 4 hysteresis input with an internal pullup resistor 2-203FUJITSU MICROELECTRONICS 23£ D mm 3749762 0012372 3 mm ‘Table 44-19-44 ‘ps8500R SERIES FUJITSU ‘ga 1 PIN DESORPTION (Continued) ‘Symbol ae id Naoe & Function Continued) o-Fort Tr as) Garlal Bata Tupac? Data apie to the oncahip serial port, The rising edge of the external (6) or internal shifts the data bit on the SI pin into the HSB of the Serial buffor register when the serial port is enabled by IN instruction. Also, the ST pin state (logical Tevel) 4s reflected in the serial data input flag (SIF) im the serial pore proscaler select register regerdlesy of enabling or disabling the serial port. Therefore, the ST pin can be sensed by reading the prascaler register using IN instruction (with Y= A). a (48) Serial Data Outputs Data outpue with Taek of theo chip serial poct. The falling edge of the external (50) or internal shift clock shifts the LSB data of the Serial buefer register to the serial port output latch, regardless of enabling or disabling to serial port. Th content of the output latch directly appears on the 50 pin, This pin ts a CMOS pullup output, and ds set high by reset. Tr] (35-32) Keforts A U-5IE parallel non-Tatched Taput oly port KO ds LSB. 4-bit data on K-Port is input into the accuaulator by INK {nstruction. ‘These pins are internally pullup. PFO 3] o ao 7) Poort! A G-bIE parallel latehed output oaly port. FO da LSB, S-bit data in the accumilator is output £0 PePort by OUTP instruction. Refer to Table 5 User mask options for available ‘aking option, T=, 07-00 wo 1,40, 41) 32-39 (3) ‘O-Fort! Aa G-BIE parallel latched output only port will ‘the on-chip mask programable PLA (Programmable Logic Array) for output data conversion, Depending on user's PLA pattern, this port functions as a dual s-bie parallel output or an S-bit parallel PLA output, Dual 4-bit parallel output: By QUTO instruction, 4-bit data in the accumulator e output, without conversion, ‘onto the lover nibble (03-00) or upper nibble (07-04) 9f,0-Port, depending on vhether the carry flag (CF) is oreaecesE 2204FUJITSU MICROELECTRONICS 23£ D MM@ 3749762 0012373 5 mm T-49-19 Gy USES saeco seams ay Table 1: PIN DESCRIPTION (Continued) ai [fin [ed Taos Rast Looe eae 03-00, | 28-25, | 0 | 8-bit parallel PLA output(HBOes0IH, HB6OSOSM): By OUTO] Gaité] ° Yieserbtion, elt Set isthe nevirianey ol flo Gye] | SEEN an bitte chaebetd ie aca crac | im | | tetera GE Seay acttte Pout dns sop co GES” | | SSE Sterter n't Belated se SoET daa Saran te panier fot tuples SOLAS Ta tae te Ea ols fetar to Table # User aut epione for avatleie sia Se 1 ET 0 Ra Pa TE TTT GstgS |” | Eee ede Ste pala) apa Coe ieti ops arom, CEI] | BR oe gh Badin er Gor tanta eval} | | SSSR ati; aa, gtcuie soos Gow es chat} | | peattx 10; auch tie end oie pore ts sane tte cna [EoD | [FON EE nth Roe litt ae (31,29, RePort #3 (R14-R12), and is indirectly addressed by the ae] etiter’c egister (Port output to an addr fnstruction. b= is (adtvidually se¢/reset by SETR/RSTR instruction, and ‘especially each line of R-Port #0 (R3-R0) is directly ‘Set/reset by SETD/RSTD instruction. The addressed line ig Individually testable by TSTR instruction, and each Line of R-Port 2 (RIi-R8) 4s directly testable in particular by TSTD instruction. (Before the TSTR and TTSTD fgstructiona, the Line to be addressed must be up to "i" (input node).) Refer to Table $ User aask options for available ‘aking option. Note: Parenthesis munber is applied to suffix -PF 2-285FUJITSU MICROELECTRONICS 236 D mm 3749762 0012374 7 mm Te 49-19 -¥Y RIGA mmessoon SERIES FUSTTSU men DIFFERENCES BETVEEN MB80500 SERIES AND MBSSSOOH SERIES Table 2: DIFFERENCES BEIVEEN M8501 AND MBaSSOLH/imsaS03H ee 168501 B86501H HB88503H ROW size | ORS 8 Bie THER Thies THRE Ores aise [ae os See Tastee bits ‘Oscillator | Crystal Coraale OSC || ~ Crystal Coraaie OSC |~ Crysval/Ceranie OSC Type oF external clock of external cleck | or external clock aeive aztve aetva + Ro-neework 080 or || + RO-network 080 or | + RO-network OSC or ‘external clock drive|| external clock drive external clock dri {Haske option) sk eption) (Waste option) Winiaun [77.86 ps use 6.19 Wa 71.3 us use 6.0 Hi Instruction | vith proscaler with’ prescaler Execution Thos [Pca > Tie : tt (task option) Feria Ta bie a Towvoltage is Reset, (10% to 470%) Function _| (Mask optton:STD version] Tastruction| 73 TE No. (Reset instruction Hoabors | ~ WOSSSOI-B/-PR/-PF_|| > ubaaSOUi-F/~PS Arvorsion are avail] Avversion are avail fable for each part || able for each part | able for each part above. above. above. 2FUJITSU MICROELECTRONICS 23€ D M™ 374972 OOL2375 9 mm 49-19-44 : ‘INNER Ms8500H SERIES FUJITSU emia ‘Table 3: DIFFERENCES BETVEEN MB98505/4588507 AND ¥588SOSH Teo i] __tmsasos 1388507 nsasosit ROM atze | EX 8 Bite TIRES bits TWEET bits EN size | eee oie TEE bite Tae xT ite isciilator |» Crystal /Cerenia OSC | ~ Crystal Ceramic OSC || - Crystal Coraale OSC ‘Type or external cleck | or external clock or external clock deive aeive detve + HO-network 08¢ or | + RC-netuork Osc or || + RC-netvork OSC or Gxternal clock deive external clock drivd| external clock dris (task option) (Waste option) {(asie opeion) Winisum [72.0 pa tee 6.0 WHE 71s us use 8.0 ME [1.5 us use 8.0 Wie Instruction | with prescaler wien pe with’ presealer Execution ie TE +8 BLE (Boftvare jectable) We 7 75 Anstruetion) 7 HESRSOS-E/-PEH/-FE_| ~ HUGSSOT=F/=PSRY=PF[[~ HbBasOsli-P/-PSH/—PF A-version axe avail} Acversion are avail4| Acversion are avail: ble for each part | able for each part || able for each part above. ‘above, above. 2-287FUJITSU MICROELECTRONICS 236 D MM 3749762 OO1237b O mm ‘ra Yosesoon seems EUITSU {INPUT/OUTRUT CIRCUITS TY9-19- Uy. ALL input only pins are internally pulled up, and all output only and input/output Po, and R-Ports have push-pull output buffer (standard pullup)- forts can have push-pull (standard or high-current pullup) or open-dzain (standard, high-curront, or 12V-interface) buffer using mask option. ‘Table 4: INPUT/OUTPUT CIRCUITS Pia Cireutt Note 7 Cayaeal Coraaie OSC of Eutarnal | > Nom-hyatereata inverter EK, x, Clock Feedback resistor: Approx. 2 HM typ. x r—> | Ge vogesv) sow Ed cctertea eet eal ese ¥ 3 THEAWatvark O80 or Bitaraal Clock [> * Without feedback resistor x feel Suaater testis x G-—_ drive is used, we recom + Tapat Oaly Far trend RC-network OSC. Tapat pollmop Feelstor m, (reek. te.) appron. 300 5, ‘typ. (at Voc=s¥) = oi fort * mystaresta toverter for It iq, To Tap POT TEE ‘START o> | Giteh. te.) sappron, 300K Ty Sap. at Cigget) RTE FEE TRE PANT FSET EET,» elon Gan oe f0/to= BESET: Approx. 300% exp. Betert EE/T0: Approx 10K type Ge veces) Systellets tnvecter for Hiatt, 80/70 + Output port options for Ores, and RePores statdard pullup: Pulls feristor Grech Tr.) Tape ay Fin Ipprons 1040 typ. ee Yt {te (ae tege3) Sy HigieSicrene puttop: O-Bore iP eels with pullup resistor Standard/high-current/ 12V interface open- drain; Without Poh. pallup resistorFUJITSU MICROELECTRONICS USER MASK OPTIONS 23e D mi 37497b2 0012377 2 mm Te49-19-4Y. NaH wuaesoon SERIES FUJITSU ‘The MB60500K sories has the folloving mask options, which must be specified by the customer on the attached data re ‘Table 5: USER MASK OPTIONS form when devices are ordered. Optional] Syabel ‘Opeton ‘Option Wore Feature No. Teck ok Wo 0) Ree Wi to 6 Be Yes Tage His to 8 Hier Daciilator | OSC | Cryatal/coraate OS —O—[¥ When only external olock Type or external clock* deive 1s used, vo recoamend Ro-netvork oscillator. We-network OE T [We reccauend no clock of external clock* presealer. Datput FLA SFLA | G-bit parallel 0 eaees0sH ie fix, Data output (888501) B-bit parallel T | customer's output FLA data output is neoded. ‘Datput Fort | PORT | Standard E [output port eiveult option a ‘Type open-drain selected sust be the sane fo% Standard WH] ali 0-, P-, and R-Ports. pull-up High-current ¥ open-drain High-current F pull-up Tiv-interface oF Part scaly open-drain Beandby SHY No 7 Function Yes (Gottvare T initiation) Catpat Fort |) STATE Wold 0 | Output port state option State During selected aust be the sane f Standby Wgz T| ll O-, P-, and R-Ports. Seandby OFF —| SOF We 7 Reset Function Yea T ‘Gatpat Fort | RSF High 0 FFort only Level Duri renet Taw T Watchdog | WOE TS 7 ‘Timer Funct Yes T 2-289FUJITSU MICROELECTRONICS 23E D m™ 3749762 0012375 4 mm Cy FUITTSU ‘oa NOTES ON OPERATION 749-19 -uy + Prevention Lateh-up Lateh-up may occur in CHS devices when a voltage higher than Vog or lover than Vgg {5 applied.to any input or output pin, or when a voltage exceeding the absolute saxinum ratings is applied between Vcg and Vgg pins. If latch-up cccurs, the supply current increases greatly, and the device ‘thernally destroyed. Therefore, applied voltages should not exceed the maximun ratings. ¥388500H SERIES + Trostaent of Unused Pina Unused input pina should be pulled up or dom with external resistors or they aay cause sone salfunctfon. (lovever, the X pin should be open vben an external clock oscillator 1s used.) ‘# Special Function of 00 Pin ‘The 00 pin has another function as a tost terminal, in addition to ite norael function O-Port, If the 00 pin is forced low while the RESET pin is low, the HOU 1s placed in the test ede. Thorefore, the O pin should not be forced low while the RESET pin is low (vhen all output ports are initialized). Eepecially vhen the open-drain is selected for the output port option, the 00 pin should he externally pulled up because such open-drain outputs are subject fo noise disturbance if left floating. ‘be Least 2 inst low after reles suction eyels required to change 00 pin from high to ng reset (RESET: Low + igh) ESET 00 " [More than 2 instruction cycles + External Capacitors for Crystal Osct1lation Fig, 9 gives an aim of an area vhere the on-chip oscillator has stable oscil tor characteristics and short oscillation stab{iization time when an average crystal resonator 1s used. The external capacitor should be adjusted to individual crystal resonators when precise oscillation frequency is required. Tt {s recommended to use exystal with a frequency higher than required oscillation frequency, together with the on-chip divided-by-two prescaler, because crystal resonators with lover oscillation frequency generally tends to have longer stabilization tine and wider characteristics variatior + Supply Voltage Hatfusction say occur even vithin the recommended 0 the eupply voltage changes Fegulated as voll as possible Eas powee feprly G5 Hg sspple. (posk-to-peak value) at consezeial fraquency (S0li to 6Olis): Late than 10% of typteal Yoo valu. (2) Veg transient change rat Gh 1g at eeltching of pover supply): I woe ora supply idly. Therefore, the supply voltage should be ‘The folloving conditions are recosmended forFUJITSU MICROELECTRONICS 23£ D MM 3749762 0012379 & mm r Iga Z veesoor suazes FUSTTSU anll INSTRUCTION SET DESCRIPTION ‘The WH2050OH seriex instruction set includas 76 instructions, 83% of vhich are Single-byte and single-cycle, 19% two-byte two-cycle, 1% two byte three-cycle, and 3% three-byta and three-cycle. The MB8BS00H series instruction set 1 exactly the ene aa the HSBSS0OH series instruction set, and is divided into ten functional groupe: * Rogister~to-register transfer 4 Hagister-to-sesory ta Constant transfer ‘+ Arithmetic and logical operations + Bie manipulation Control. Input/Output. ‘Tables 6 and 7 sunsarize the MASSSOOH series instruction set. ‘Table 6: INSTRUCTION SET SUMMARY Trenoniq Coda | Flag/Stanaa tyra) operand (Hex. )/ ZF 1 CF [ST] cyel Operation Woglater= [tank P05 | |= [> [aa | BCT tom mam fos [+ [+ |- [asi | muecacy Register [tas for |. |: |: [aa | saccacy ‘teanstor [tay [oe | | | aa | yecacy Tsk [IT Pat Po bie wade? BOTS S-biz soda: AGr(SBL), Ke(SBq) +6 ma fis |e + fags [Acta ma [ie |t + |i | aceem) ipegeere steer + Lit [cere és ea Register | oF T/L Ace, YT tor Is. wetted diy | spencer) Menory [ST D Tit [HC Y) CACY Teansfor |stoc | 14 fe} asr | HcxXxde(A0), YeCrr—1 strc | on wel asr | HcXrde(acy, YeCx) +1 sts__|2a__|t aa_| worxe(sa)) x cans TA] Ga, YT xo | so-sod te 1/1 | (AG)afuCO,0)}; Deo eo 3 (x60, YD) xo__| 500579 a/_| i afuco;py}; ped co 7 (x00, Yep) Toartant [CLA [90 | |>]> i” | ated Cinoluded im LI instruction) Teanafer [LT ox] 90-9742 |- |- | 1/1 | Acetens tmme0 to 15 tat ie sens t [+ |. [iyi | x3+0, 22 to Xoriom; dmme0 to 7 ux | s090-| + |+ |+ | 272 | xetom; don=0 to 15 ‘SDF* taxa toot 3020-|- | + | | 2/3 | x «(monte TY a, a27—4' S03 Ace(RoH(CEam TR TY] }a, d=9-0 dened to 31 tyr_tod soma t |. |. lays |v etmn; taaeo eo 15 eteimatia aoe POE] |] WY] T/A] AGH CACY TCE DDT HCCED S Logical | aX toa s0so-|t | + | 10] 1/1 | aceCAc)eseas ten=0 to 15 Operation 308F ao jor |e wlan | acecacynwce.y} < 26a aya, FTCA or tos o-ard t | t | iz) 1/1 | smn-CAc); Amaro to 15 ovt_ioa aomard «|. [izlin 2-291 (2) j imae0 to 15FUJITSU MICROELECTRONICS @3£ D M™ 3749762 0012360 2 mm T49-19-Y. ae wana om Ra ‘ehie 61 DOTWOCTIN fEF some (Cosine LLU +Operand (Hex.)[ ZF | CF | ST | Cycle Operation FEE ee Tee TT a RETEST apes oF CHT Tiasajae |i |: [i [iS He [aeteiete te ube ten Sperteicn| ata [ater |i |# | 2/272 |Aeccchess Clactodes Se Ar daueruee Be PBT YE TE Pig | seecateas tes ass pee Lea [ae EOR ar = Ta [A /t [ACH THCY) JOCAC) Fee ae ase is aE a Tem 09 tye Pic past | aC, ry+ (Mex, ¥) Jot tion) ta Sue |! |: fig] 2 [ES lee 1s Lie [econ Wf eae ‘OR iF FT ace tex YOU a rt—“C™rC—C—SSC we fie fe fe fala Te . ee ee een He ‘REIT bp | 34-374 - [= [= [U/l [{HCX,¥) }bped; bp=d to > Meccpute- [eoer wo [soctad «|. [ [ue | te lbert tee ee ¢ TP RE Se ae a 2 bp ait | deveon 5 wat tos To aT aa TS Bir Elin ase aE the operand byte (2nd byte) ue sad woe | [= | fava | HBsecterane ire Cant bre) pay ~~ pox (350 | | L. [aye | eeceeetbaie ns ep ee ety iad Koad #3 wis ne —_laz_ dele |. fae [A BR ar ETT Goes eis coro fox | |o |. Var | SPU se, Hee gens oo eA aes Se Scar arco aE FOE EY Bala: |: |. (i fo tis tue fama [aeoots |: |: [He $0 3 Ge Pe tore 40) --. foe is Ge eo tet ote ie Reo je [elie tots i Gus ce one taest to a, S120, Not Subroutine Call. 2-292FUJITSU MICROELECTRONICS 23£ D MM 3749762 0012382 4 mm TH44~-14-Gy ‘aan wmensooH SERIES FUSTTSU aaa ‘Table J INSTRUCTION SET SUGARY (Continued) Taeaoald ods [Flag] Seed Byes +0pezand (Hex. )[ FF GF ST | Opel Tanck SHE aady COmP * Operation T/L | TF SIS, Branch to addry alE=0 to 6: ‘S10, No Branch. sexx aa s000-]- |. | + | rz sour samt aay 00-]- | + |- | 2/2 | te stat, aeanch to add; Ieee fdazeo £0 8095, s1~0, No Branch. SE atin roe tneerrape Routine ms__|2c_|- |< |* |i [Return Froe subroutine Fag ses apo tarfpote- [sero [ax | [+ |< [ia Loree re ee we fa |: |: [aia |G, ce met, oe es | |: |: [iia | Gea So gv fas |: |: [igi | Gaya veo wot |: |: [dia | Gat Tee a a te Not ‘Lr OF ds aot or reset depending on contents of AC after instruction execution. 42: UF 4s got or reset depending on contents of Y after instruction execution. 43: Each bit of the operand (the second byte) functions as follows: 2nd (458) rs) 2 eR rer reer | L—— fntble/Discble exeernel inteczept. CHRQ) |_——— fitble/Disable clock inearrupe | Stact/Stop' synchronous tioing output (TO) Reset proscaterclock/No_ operation feace/Seop satel ore SEE | ——— Seaie/stop thner/counter’ 4: MBSOSOIH and MBBSSOSH: Ace(SB), ZF affected Nasssosit ACe(SBL}, X+(SBH), ZF not affected 2-293FUJITSU MICROELECTRONICS Syubols and Abreviations ‘menory (RAM) location indirectly addres 236 D mm 3749762 OOl2382 b 49-19-44 NET wmsasoog SERIES FUSTISU ea (OF reset) by operation results ‘carry (not carry flag) 8 rial buffer full/oapty flag F/counter overflow flag zero (not Zero £108) ‘usp Bit pointer (that is part of the instruction code) Direct Line nusber (that {s part of the instruction code) Data senory (RAM) location directly addressed by "D" bits in the RIL-RB, 93: RIS-R12) ecified by Yeregister (¥#0'to 3) ‘Yerogiatar (Y=0 to 15) 'a" bits in the instruction code Sabot Yes . Yo transferred to . Is exchanged with : Azithnetie. plus - Aritheetic sinus @ Topical exclusive or 8 Logical OR vo Togical AND (Overtine) Negation Q) Contents of parenthesis + Set to "1" always + Bet to "0" + Affected (5 io ‘to 70" due to ior 0 "0" due to carry flag aE ‘to "0" due to interrupt £1 ise 0 "0" due to Ww 0 "0" due to ei i £0 "0" dua to ae £9 "0" dua to zero flag : affected Meaning 730 ‘Accumulator dar addr bp ¢ Carzy o Carry flag 4 1 Interrupt flag fea Tmsediate dat 1 Interrupt requ x K-Port. (K3 to FO) isp Toast significant bit HK) (i> and Tregisters) (0,0) Anstruction code, in page #0 (X-0) 83 Most significant bit ° O-Port. (07-00) PLA Progranaable Logic Array R HePort (00: RI-RO, H1: RIARS, & Ys Yen RePort da HoPort bit n specttied by (Bas don RePort bit m specified by * 3B Serial butter register sr Serial buffer full/eopty flag sr Status flag Tm Tiser/oounter high byte ™ Tiser/eounter low byte w Tiser/eouneer overflow flag x Xerogister (that indicates page ¥ in date Xa The arth bit Hrogister Y Yoregister 2 ero Ey Zoro flag 2204EE FUJITSU MICROELECTRONICS 23£ D M™ 3749762 0012383 8 mm Te 49-19-44 eT sasoou SERIES FUSTTSU rn ‘Table 7: INSTRUCTION COMES suMARY Oil el] 01/4) 54) 0 ee kOe) | olla |e H © | woe | ourd ourg ovr | ray | tard tary tas | rev | rox] strq x | Ron) x | ane | am a | ova} oas | sux] av | rea | rr rma tsa | pox | now | stad xx | ror | st | sac | or 2 | sam send ror nerd tem rend te org neve tend ers] as | rs [ee | zon 3 Serr Rot ‘Tart nor | exr| ax | prs be bp be. seo] tam, 4 seTD TD 1s Ta fi 4 4 bp 5 » x uxt D D ies : oa a addr 7 mL ade J 8 ut foo 9 cua! a i ion 4 ovr ion 3 or ce D jee oP dae g F Nore: snstruction + A-byte/I-eyele instruction OJ 1 Bobytes/2-cyel % See the next page 2-285FUJITSU MICROELECTRONICS ‘Table 7: INSTRUCTION CODES SUMARY (Continued) sd instruction 236 D MM 3749762 0012364 T mm T 49-19-44 USER Msasoom SERIES FUITTSU Se 3 olilz}s]elslel7lel>lalelelolelr P 0 wert ae 1 2 mm i= 2 ‘ vor vseo 3 a vor vse 7 a] koa) a {02a : i 9 wap ie a sa mA vor usin | tox) esr] vor sen Ba 3 vor usep ° vor use > J t ? vox: [J 3 byte/3 cycle instruction 2-208FUJITSU MICROELECTRONICS 23£ D MM 3749762 0012385 1 mm 49-19-44 ARH usas0oK SERIES FUSITSU Wat [PRODUCT LINE-UP AND DEVELOPMENT TOOLS ‘The MBSBS0OK series consists of the MBSSSOIH, MBSSSOSH and MBSESOSH. The WB88508H aro available as piggyback EPROM avaiustion davices for MBGESOIN and MBEBSOSH. MBGOSOGU de for the MBSBSOSH. Refer to Table 8. ‘Table 8: MBSSSOOK SERIES PRODUCT LINE-UP & DEVELOPMENT TOOLS. THESESOIN-F7 ] HEGSEOSU-R] | MBSOSOSH-PT | HBBSSOBTAC] RBSESOSU-C; apsny-pe | -Psi/-PF | -Psu/-F | -cF-101/102 -cF-101/10 RH Size Tex obits pie x 8 bls | OK x 8 bite aK x § bits (archip | (On-chip | (On-chip (External EPROM) ‘mask HOH) |nask ox | mask ROH) TH Size 256 «4 bite (Bizectly address: @-7) ed locations) 1/0 Pore: Total 36 ines “Input only port 7 Toutpue only: port 2 1/0 port 3 “Control port, 5 (Including serial 1/0) Output Port TyRe TaD P/U TaD Parior + sm 0/0 + sD 0/:102, + Wye P/U + we 0/9 + 12V interface 0/D (P-Port) (Mask option) ‘Gatput FLA Pattord 35 pattoras ‘Dual -bie paraliet | + Dual S-bid + Dual d-bit output parallel parallel + S-biE PEA output feutput, feutput (32 patterns) Stack Dapeh Wists (esting Level) "Tier /Counter! Ye Buffer size 8 bits =Clock source i 1 Terial 1/0: Te Yor Buffer eize 4 bite a bite “Clock source Internal External Internal/ External Output latch, Yos Yos Tlock Generator? a “Osedilator type + Grystal/External (Eixed) “Clock Frequency 2 Wes tots a 4] a With prescaler) (& tten8 Mts) 4 tend tt 1 eaten Clock Prescaler Yea/No Yer (Diviacby-evo) (Qtask option) (Bix0d) Taterrupt Functiow Ye Nesting Level Single Level xinterrupt sources source 2.297FUJITSU MICROELECTRONICS 23E D MM 3749762 0012386 3 mm ‘MBSBSOOH SERIES ‘PRODUCT: LINE-UP AND DEVELOPMENT TOOLS Table F-49419 -44- coment i MBSBSOOH SERIES PRODUCT LINE-UP & DEVELOPMENT TOOLS (Countinued) TESBSOLN-P/ | MBSBSOSH-P/ | MBOSOSH-P/ =psi/-pP | ~Psu/-PP | ~PsH/-PP TEBESOSE-C | MBSBSOGU-C oF =a OFP=46P Standby Functi "Yes/iio ask option) 7 Yes. (Fixed) “Initiation sathod * Software + Software “Osciliator sta + Tale/Stop + Tdle/Stop dicing standby (Software selectable) | (Software solectable) Output state * Hold/igh2 Holds102/Migh-2:101 during standby ‘option) Standby off re ° function (ask option) Watch Dog Teer = Ne Function (bea) (task option) Taber of 7 78 7 Tnsteuctions [instruction Ti, Ey oF aS Wi, i, 23, 8 375 | tengen/yete Wine InstructTon Taye ae 6 i Tos at Execution Tee ith pee in Chie prescaler] Paver Sippy Single 757 Tiagle 75 “Standard varsion} mackie “standby ~hevorsii wactive “standby Operating Tea. Range: “Standard version ~to°e to 405% 40°C to 405°C mAcversion 730°C to 470°C = Process [aU Package DG Ir SH-DIP-A2P NQrP-68P Davelopaent Tool Herdvas MB2115-01 + ORT unit (Common) MB2115-02 : Honitor hoard with keyboard (Common) MB2115-04 | EPROM weiter (Common) MB2IL5-31A: DUE board Softwa 'SHO5215-A010: Intollec sMO7A1S-AO12: sipgoor-1000%: SHO7415-0022: CP/N-86 host omulator SYOOOORK-I00K: FO-DOS host onulator Note STD: Standard H/C: High-current P/U: Pull-up 0/0: Open-drain 2-298FUJITSU MICROELECTRONICS 23E D MM 3749762 0012387 5 mm 49-19-44 ‘oo vosesoon SERIES FUNTESU sc HLECTRICAL, CHARACTERISTICS + ABSOTUTE MAMAN RATINGS (Standard and A-version)t Tae Paraseter sretet_ [ag ae Renerks Supply Voltage | veo | Yss0-3 Vase? Ves v is Tio aot waste Taput Voltage vn | ves-0.3 veet7.0| v | Yooto3¥- Should aot wren Output Voltage Vout | vs5-0.3 vgs+7.0] v_| Voct0.3¥. Ty EE Yos-0.3 wgstt5.q v | (2V dacertace openndeein) Se 20 | aw ‘Total ORR Fr = Low Current ad ea a tower Dissipation | Fp oa a Operating Aablent a a Tesuocatare Tm! a0 al ‘c OFA Tore |_-35 vaso |e ited to the conditions detailed in the operational sections of this data shest. Exposure to ‘abeolute saxinun rating conditions for extended periods aay affect device zeldability.FUJITSU MICROELECTRONICS 23£ D MM 37497b2 0012388 7 mm =e (nen ionesoon SERIES FUJITSU MELE ‘+ RECOMMENDED OPERATING CONDITIONS (Standard versica) Parazeter | Syabol |p ee atoms supply a Sc] 0] detive operation eange Voltage a SO —|V_| Standby operation range Tes 7 T Tape HGR | ig POET GUS, Tea, SF Voltage Vero | |B START 56/0, td, TE, REET Tape Taw | Van | Vaso TT Ver Voltage Vans [Vaso TIVE [ Sperating aabient | T% | 40 +85 Teaperaturd, OPERATING CONDITIONS (A-version) ras SS a Cad en CC CC 35 TOT Seay operation Fangs Te 3 [input tg | Vin) 0-75 Va Veeos] V | Kort, ot voltage Tess] | ar —— 3/70, 1kG, Te, RESET Tae Ta | | Wass Tae V Yiekort, St voltage vas eos TEVes| VET —— 50/10, 13d, TS, RESET DpareTae Motes | | | -30 wo |e ‘Fesparsturd 2-300FUJITSU MICROELECTRONICS 23— D M@@ 3749762 0012389 9 T49-9- UY ER (sasoon SERIES FUSITSU gE ‘+ Dc CHARACTERISTICS (Standard and A-version) (Roccemended operating conditions unless othervise noted.) Parazeter | Sysbol] Pia/Port Condition Daepae High | Vox [Om Fe, Fores | Vega 30 Voltage (Standard/High- | Toye-200u4 ‘current pull~ sp), 56/10, 80 [Voges Togo v Daepat Tad [Vor O=, Fo, IeForts | Voges aT Voltage (ada ouput | Yopet. dea ody cepetons), 3/0, 80, RESE Vog=t 57 i Tapes 6a og v Tae | SRE EE vies 50 co} as Toput Leakage | Tyy_| EeFore Standard) current Highecurrent aA pullcup), 86/5 BK, Rtore, Sf, [Vooes 50 Ea RESET, TR, Te | vyp-o.0v ~60| va ropea-Dratn —| Tina | O, Pos BeFores | Vere SV Oueput Leaks (Standacd/tteh | Voye=s 5 Current current/12V. | Output in high-z ot] 10| na faterface open drain) [Feral 170 — [Wiz PAL pins oncope | Voges SVSeanaEy) Teakase You Yess BX and Ue to 6.00, oles stron Tat nt state (itghez) = = Supply currant Tog] Veo TessS-OVE. Ds 5.5V(tax.) 4 faz [aa sentiin(Active) ALL outputs opea Tec | Yep icgns OV (Glen standby | t6°0(Standby), 20 us function) | ALL outputs open Tapa Tin [ALI pins excopE | felts Capacitance Veo and Vs 10 | 20 | pF 2-301FUJITSU MICROELECTRONICS 23 D MM 3749762 0012390 5 mu asa vmsesoon sexes FWITSU ‘AC CHARACTERISTICS (Standard and A~vex ) Lae . se ston) crocs rm T-49-19-44. Gleconseaded operating conditions unless otherwise note Pavaneter [Syabot [Pin | condivion Mut Tune| __Renecka Taek 7 Te eRe a Te Titian prescaln Feesuency 3” [or gornetwore Osc or extersal vais clock driver | 4 | 8 Figs, ¢ ana? Teak GIS tape | Bless 7 ee x 0.24 0.5| ue Tapat Clock | Fuca External cTGE | 399 Without prescala Pulse wiaes | Pex’ [ax | arivaceteh & = y Teh RTT Tapae CIE] torr Eetecael cIocE Reveal | ec¢) [ax |étimcaent | 5 [100] ne Tse pen): Sigs, 6 ond 7 Fig, Gr GSE NE aay i” ee (without Peescates) a ay ee (teh Prescalee) 0.2¥¢¢ Fig. Te GK CGT TOOTING (1) ceyseat/cerante (2) Ro-Netvork (2) External Clock Gscklietor Osetliacert Brive xx mk mx == ae $ 1 ss a open 4 eon the Ro-natvork oscillator 1s used, the folloving conditions must be ett i) the prescelor is not ured. 2) Vogssvi10% 3) Tg#-40°C to +85°C(Standard version), Ty*-30°C to +70°C(A-version) 3) ete oot encoot ial (ug clock Efequaney 1a about SSc‘tas at Woes and TetS°C.) 2302FUJITSU MICROELECTRONICS 23E D mm 374972 001239) 7 mw ‘M@essooH SERIES FUJITSU not raion 20 Veeas.ov. Oscillation Frequency (itz) 66 10TH HD External Capacitor ¢ (9F) Note: When tho RO-aotvork oscillator is used, the folloving conditions 1) The prascaler is not used. 2) Vo = $V 10% 3) Ts 40 95 °C (Standard Version) TAs ~30 °C to +70 °C (A-varsion) 4) £8 dos not exceed 3.2 Ile. Fig. 9¢ CRYSTAL OSCILLATOR CHARACTERISTICS (EXAMPLE) ex x External Capacitor Ct, 62 (oF) z or a) Crystal Osefllécion Frequency (itz) ict frequency 1s needed, capacitor determined, adjusted to individual crystal resonator characteristics. 2) Generally speaking, crystal resonators with lover oscillation frequency tend to have longer stabilization tine and vider characteriatic variations uhich affect on-chip oscillator characteristics. So, we recommend a high-frequency, crystal resonator with on-chip 1/2 prescaier, 2308 ig: 6 ROAETORR ceommanon Gunaornrorcs Gams) 7 F9-19 -44FUJITSU MICROELECTRONICS 23E D mm 3749762 0012392 9 mm (ovat wsesoou SERIES | FUSTTSU (ARE OUTPUT TIMING (Standard and A-version) (Reconsended operating conditions unless othervise noted.) Tatas Pin/Port ac = tat O-Fare 1000 Bort | Fig. 10 as RePort * 30 Gertal Fort | tap] 5 730 Delay Tice Fig. 10 aa ton 30 10K9 pull-up {s coquired when open-drain output is us 2) ALL the output loading values axe S0pF + 1TTL. Sea figure below. sv oa, i Sop ig. 10: OUTPUT TRING + Parallel Port ay 0.09 O-, Po, Reports 24 + Serial Port ot oi bd [Basie seq [finpue so son 80K 2-304FUJITSU MICROELECTRONICS a3e D INPUT TIMING (Standard and A-version) (Roccnmended operating conditions unles otherwise nota: mm 3749762 0012393 0 mm 49-19-44 RRL sovesoor sams ang Parenater Conditions| nse Tapa Data Setup Tine nput Date Hold Tine Fig Tr ST Tapue Setup Tine ST Tague Te Tr Es Fig rv Hold Tine (Synchronous node) [Device Control is Figs ir ising Tapae Setup Tice (synchronous ‘zode) al Fig. rs Tsing Tapat Hold Tine ‘zoda) Fig i ‘zode) [Control Signat Low Level Tse eI ig rs (synchronous fl fal ia | ‘sode) Tonerol Signat High Level Tied (at (al Fig (@syachronous al E 5 us Tanerel Signal Rise and Fall Bi (ai & ial Fig. Should be lees than 200n8 2-908FUJITSU MICROELECTRONICS 23€ D mm 3749762 0012394 2 mm TH49-19-HY MONEE vmossoon senmes UTED ASE Fig. UL: INPUT TONG / [Szgetsonoue [edtee + Parallel Data Taput K-Port, RoPort tone, + Device Control Input 4 Eis, ‘START + TE rapa, = + Serial Data Input 30/15 petee cheeky {Iaput st 2-208FUJITSU MICROELECTRONICS 23 D ‘+ POWER-ON RESET (Standard and A-version) 3749762 0012395 4 mm 49-19-44 UES Tina 80500H SERIES Tondi= [Value Feraneter | Synboll eons [Win [Ha Ua Renarke Pover Supply |e; | Fig. 12] 0.08] 50 Rise Tine Waquired for operation oF ‘the povercon reset clreule Power Supply | tage | Fig 12] T Shutwoff Time Required for accurate circu operation repeatability Fig. 1 Note: Powor supply should be raised smccthly. ‘PONER-ON RESET TTAING 2-907FUJITSU MICROELECTRONICS 23£ D MM 3749762 001239b & mm (nS FOSTTSU (ee 44-19-44 ‘MB88500K SERIES PACKAGE DISGNSIONS + NBesSo1i-2/S03K-P/S0SH-P: 42-PIN PLASTIC STANDARD DIP “@LEAD PLASTIC OUAL MELINE PACKAGE Tease na eacruat) wee ‘+ veeso1n-PS1/S03K-PSH/SOSH-PSH’: 42-PIN PLASTIC SHRINK DIP saueno mgm oUat ne ackae aeFUJITSU MICROELECTRONICS. 236 D ‘mpenso0H SERIES PACKAGE DIMENSIONS (Continues) 4+ NB89501H-PF/S03H-PE/SOSH-PF: 48-PIN PLASTIC FLAT PACKAGE mm 37497b2 0012397 6 mm 49-14-44 ‘SUISSE USTs TeASE Nas FPrehucDh eos £7 I Le aa m 2-309FUJITSU MICROELECTRONICS 23€ D m™ 3749762 0022398 T mm cu oesoon smies | FWTISU Hae PACKAGE DRENSIONS (Continues) 4-19-44 + Mp99S08H-C/MB8BSOBU-C: 42-PIN CERAMIC HODULE, "LEAD GUAL WALI PACKAGE WOOULE (east nos moeaaceas [S555 SS0OSOO0OS, eseer a [gan0dS 0000009) 2am LA es — ier ae ‘+ MB08SOBH-CF/HB8SS0BU-CF: 48-PIN CERAMIC MODULE “e-Leno quan meine ruar paceace MODULE *stgouce Hos woessaray) on au Eran