Real-Time Laboratory (FPGA)

(4th Class)

Computer and Information Engineering Department

College of Electronics Engineering
Ninevah University
2021-2022

Copyright © EECIE Department 2020. All rights reserved.

 Lab #4: ALU with Register File

OBJECTIVE
The objective of this lab is to gain experience designing ALU circuit using VHDL, you
will be learning how to model and implement a simple ALU circuit that reads from and
writes to a register file. The Xilinx Nexys4 FPGA board is used to help students
understanding the basics of the FPGAs and how they can physically implement and
configure their projects (VHDL code) on an FPGA platform.

Learning Outcomes
After completing this lab, you should be able to:
- Design an ALU circuit using a combination of structural VHDL for the state
memory and concurrent signal assignments to store the next state output logic in
the register file.
- Instantiate a pre-designed VHDL circuit/sub-system into a top module to
construct and implement a larger system (instantiating pre-designed components
or modules into the main project to configure the required or desired system).

ALU with Register File

In this lab, use the combinational and sequential HDL structure to design and implement
an ALU circuit that reads from and writes to a register file (R1—R4). The design will be
implemented on the Xilinx FPGA board where the output is displayed on the LEDs.

Procedure
Part I: The purpose of this part is to learn how to design and implement a simple ALU
circuit. Note that the design here is totally combinational, so you do not need to
use the process statement for this part.

1) Write a complete VHDL code to build an ALU circuit, shown in Figure 1. Assume
that the Instruction Set Architecture (ISA) for the ALU is as listed in Table I.
n n
A (7:0)
B (7:0) A B
2
F (7:0)
FS
ALU
C
C FS (1) F
FS (1:0) n
Figure 1: Circuit diagram for the desired ALU circuit.
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 Table I: ISA of the desired ALU circuit.

FS Operation Unit

00 F <= A+B
Arithmetic
01 F <= A-1

10 F <= A AND B
Logical
11 F <= A OR B

Part II: The purpose of this part is to learn how to design and implement a register file
(R1—R4).

1) Write a complete VHDL code to construct the register file circuit shown in Figure 2.
The coming data is written inside one of the registers based on the values of Q signals
with the rising edge of the clock (clk) and when the write enable (WR) signal is high
(‘1’). Consider the input data ( D ) as a constant value stored inside the design, and
assume n is 8-bit.

Figure 2: Diagram of the desired register file circuit.

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Part III:
The purpose of this part is to learn how to employ the ALU circuit and a register file,
designed in the previous steps, as components via instantiating them into the top module.
Thus, the top module (main project) will be a simple co-processor that consists of an
ALU circuit that reads from and writes to a register file (R1—R4).

1) Use component instantiation structure (discussed and implemented in the previous

labs) to instantiate the pre-designed ALU and the register file circuits into your main
project (top module). Write a complete VHDL code to construct the ALU circuit with
the register file as shown in Figure 3. Consider n is an 8-bit and the data are stored
inside the internal registers, initial values of the registers are listed in the last column
of Table II.

Figure 3: Architecture of the desired ALU circuit and register file.

2) Implement the design and configure it on the Xilinx Nexys4 FPGA board, demonstrate
the correct functionality of your design by testing the instructions listed in Table II
and observe the output on the LEDs.

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 Table II: The instructions to be tested and initial values of the registers.

Arithmetic Logical Initial Values

A = R2 ; B = R3 A = R1 ; B = R2 R0 = x"01";

R1 ß R2 + R3 R2 ß R1 OR R2 R1 = x"02";
A = R1 A = R0 ; B = R3
R2 = x"03";
R3 ß R1 - 1 R3 ß R0 AND R3
R3 = x"05";

Note: To test the functionality of your design, connect the followings:

• AA0 – AA1 à SW0 – SW1

• BA0 – BA1 à SW2 – SW3
• FS0 – FS1 à SW4 – SW5
• DA0 – DA1 à SW14 – SW15
• WR à DIP (push button in the center)
• F0 – F7 à LED0 – LED7

The data address bus (DA0 – DA1) is used with the write signal (WR) as control signals
to store the coming data from the ALU inside one of the internal registers (R0, R1, R2,
and R3) of the register file. Thus, setting WR='1' (Active for write access operation) by
connecting it to one of the push button switches and display the result (F) on the LEDs.

SW15 SW14 … SW5 SW4 SW3 SW2 SW1 SW0

…..

DA1 DA0 … FS1 FS0 BA1 BA0 AA1 AA0

Input configurations

LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0

F7 F7 F5 F4 F3 F2 F1 F0
Output configurations
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Report and Discussion
Q1. Write a complete VHDL code to construct the circuit shown in the figure below,
where the size of the memory is limited by the size of the registers; with n-bit
registers, the size of the RAM is 2n x n bits. Consider n=8-bit.

FS Operation Unit

000 F <= A

001 F <= A+1

Arithmetic
010 F<= A+B

011 F <= A-1

100 F <= A AND B

101 F <= A OR B
Logical
110 F <= A XOR B

111 F <= NOT A

Q2. Based on the previous question, if the design executes the following series of
register transfer instructions:

R3← M[R0]

R3← R3+1

M[R0] ← R3

What is the value of control and address signals for each component (Register File,
RAM, and ALU circuit)? Use the table above to determine the value of FS.

Note: There is no way for the ALU circuit to directly access the memory—RAM values must go through
the register file first.