Presentation

On
programmable keyboard display controller

Md. Rasheduzzaman
Id: 16CSE027
Session: 2016-17
 programmable keyboard display controller

programmable keyboard display controller is designed by Intel that interfaces a

keyboard with the CPU. It is named intel 8279

The keyboard first scans the keyboard and identifies if any key has been
pressed. It then sends their relative response of the pressed key to the
CPU and vice-a-versa.
Block diagram of 8279 based system
A3-A0
D7-D0
16-character
B3-B0 Display
RD

WR BD
8279

8085 IRQ SL0

CLK SL1 Decoder

A0 RL3-RL0
SL2
SL3
16-Key
Keyboard
Matrix
Control
Keyboard
 Features
 It is designed by Intel.
 It is support 64 contact key matrix with two more keys
“CONTROL” and “SHIFT”

 It has inbuilt debounce key

 It provides 16 byte display RAM to display 16 digits and
interfacing 16 digits.
 It provides two output modes:
1. Left entry (Typewriter type).
2. Right entry (Calculator type).
 Architecture and Description

It consists 4 main section:

1.CPU interface and control section.
2.Scan section
3.Keyboard Section
4.Display section.
 CPU interface and control section
CPU It consists of 8
Interface
Section bidirectional data
lines (DB0-DB7),
IRQ line, RD line,
WR line, CS line,
RESET line, Buffer
address line (A0)
 Scan section
• Consists of

– Scan Counter

– Four scan lines (SL0-

SL3)

• It is used by keyboard
and display section for
proper functioning
 Keyboard Section
• Consists of
– 8 lines (RL0-RL7) that can be
connected to eight columns of
a matrix keyboard
– Shift and CNTL/STB
(Control/Strobe)
– 8-byte FIFO RAM
• Keys are automatically debounced
 Display section
• Consists of
– 8 output lines (A0-A3)
and (B0-B3)
– 16 byte display RAM
– Display address registers
holds the addresses of the
word currently
read/written by the CPU
to/from the display RAM.
8279 − Pin Description
Data Bus Lines, DB  - DB (12-19)
0 7

These are 8 bidirectional data bus lines used to transfer the

data to/from the CPU.

CLK(3)
The clock input is used to generate internal timings required

by the microprocessor.

IRQ(4)
This interrupt output line goes high when there is data in the
FIFO sensor RAM to generate an interrupt to the CPU.
RL0 − RL7 (38,39,1,2,5,6,7,8)

These are the Return Lines which are connected to

one terminal of keys, while the other terminal of the
keys is connected to the decoded scan lines. These
lines are set to 0 when any key is pressed.

RESET(9)
As the name suggests this pin is used to reset
the microprocessor
RD, WR(10,11)
This Read/Write pin enables the data buffer to
send/receive data over the data bus.

Vss, Vcc (20,40)

These are the ground and power supply lines of
the microprocessor.
A0(21)
This pin indicates the transfer of
command/status information. When it is low, it
indicates the transfer of data.

CS Chip Select(22)
When this pin is set to low, it allows read/write
operations,

else this pin should be set to high.

SL  − SL (32-35)
0 3

These are the scan lines used to scan the keyboard matrix and
display the digits.

RL  − RL
0 7

Return lines are inputs used to sense key depression in the

keyboard matrix.

SHIFT (36)
Shift connects to Shift key on keyboard.
BD (23)
It stands for blank display. It is used to blank the display during
digit switching.

OUTA  – OUTA  and OUTB  – OUTB3 (24-31)

0 3 0

The data from these lines is synchronized with the scan lines to
scan the display and the keyboard.
Connecting a 7-segment display with 8279
SL0

SL1
4-to-16 decoder
O0 O1 O15
SL2
VCC
SL3 VCC

8279
a a
A0

A1 f b f b
g g
A2
c c
e e
A3

B0 d h d h

B1
Connecting a 64-key Keyboard with 8279
SL0

SL1
4-to-16 decoder
O0 O7 O8 O9 O10 O11 O12 O13 O14 O15
SL2

SL3
Multiplexed
7-Segment Display
8279
RL0

RL1

RL2

RL3

RL4
Thank you

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