CS301Y22 - Chapter 3 - Gate-Level Minimization

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OUTLINE OF CHAPTER 3
The Map Four – Variable Product of Don’t Care

Method K-Map Sums Conditions
Simplification
NAND and NOR Other Two Exclusive-OR Hardware

Implementations Level Function Description
Implementations Language
November, 2022 LOGIC DESIGN
3.1 THE MAP
METHOD
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THE MAP METHOD

• Gate-level minimization refers to the design task of finding an
optimal gate-level implementation of Boolean functions
describing a digital circuit.

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THE MAP METHOD

• The complexity of the digital logic gates
– The complexity of the algebraic expression
• Logic minimization
– Algebraic approaches: lack of specific rules
– The Karnaugh map

• A simple straight forward procedure
• A pictorial form of a truth table
• Applicable if the # of variables < 7

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THE MAP METHOD

• A diagram made up of squares
– Each square represents one minterm
• The simplified expression produced by the map are always in

one of the two standard forms:
– Sum of products
– Product of sums

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THE MAP METHOD

• Boolean function
– Sum of minterms
– Sum of products (or product of sum) in the simplest form
– A minimum number of terms
– A minimum number of literals
– The simplified expression may not be unique

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THE MAP METHOD

y
• A two-variable map x 0 1
– Four minterms 0 m0 m1
– x' = row 0; x = row 1 1 m2 m3
– y' = column 0; y = column 1

y y
– A truth table in square x 0 1
diagram 0 x’y’ x’y
– xy x 1 xy’ xy
Figure 3.1 Two-variable Map

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THE MAP METHOD

y y
• Fig. 3.2(a): x 0 1
– xy = m3 0
• Fig. 3.2(b): x 1 1
– x+y = x'y+xy' +xy = m1+m2+m3 (a) xy

y y
x 0 1
0 1
x 1 1 1
(b) x+y
Figure 3.2 Two-variable Map
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THE MAP METHOD

y y
• Three-variable map: X 00 01 11 10
– For 3 binary variables. 0 m0 m1 m3 m2
– 2n = 8 minterms.
x 1 m4 m5 m7 m6
– Map consists of 8 squares.
yz y
– Minterms are not arranged in
x 00 01 11 10
a binary sequence.
0 x’y’z’ x’y’z x’yz x’yz’
– Only one bit changes in value
from one adjacent column to x 1 xy’z’ xy’z xyz xyz’
the next.
z

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THE MAP METHOD

y y
• Any two adjacent squares in X 00 01 11 10
the map differ by only one 0 m0 m1 m3 m2
variable
x 1 m4 m5 m7 m6
– Primed in one square and
unprimed in the other yz y
x 00 01 11 10
– e.g., m5 and m7 can be
0 x’y’z’ x’y’z x’yz x’yz’
simplified
– m5+ m7 = xy'z + xyz = xz (y'+y) = x 1 xy’z’ xy’z xyz xyz’
xz
z

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THE MAP METHOD

y y
– m0 and m2 (m4 and m6) are X 00 01 11 10
adjacent 0 m0 m1 m3 m2
– m0+ m2 = x'y'z' + x'yz' = x'z'

x 1 m4 m5 m7 m6
(y'+y) = x'z'
yz y
– m4+ m6 = xy'z' + xyz' = xz' (y'+y) x 00 01 11 10
= xz' 0 x’y’z’ x’y’z x’yz x’yz’
x 1 xy’z’ xy’z xyz xyz’

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THE MAP METHOD

• Example 3.1: Simplify the Boolean function F(x, y, z) = S(2, 3, 4, 5)
yz y
x F = x’y + xy’
00 01 11 10
m0 m1 m3 m2
0
1 1
m4 m5 m7 m6
x 1
1 1

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THE MAP METHOD

• Example 3.2: Simplify the Boolean function F(x, y, z) = S(3, 4, 6, 7)
yz y
x F = yz + xz’
00 01 11 10
m0 m1 m3 m2
0
1
m4 m5 m7 m6
x 1
1 1 1

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THE MAP METHOD

• Consider four adjacent squares in the three-variable map.
• Any such combination represents the logical sum of four minterms and
results in an expression of only one literal.
• The number of adjacent squares that may be combined

– power of two
– 1,2,4 and 8.
• Larger number of adjacent squares

– Product term with fewer literal

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THE MAP METHOD

• m0+m2+m4+m6 = x‘ y‘ z‘ + x‘ y z‘ + x y‘ z‘ + x y z'
= x'z'(y'+y) +xz'(y'+y) = x‘ z' + x z‘ = z'
• m1+m3+m5+m7 = x‘ y‘ z + x‘ y z + x y‘ z + x y z
=x‘ z (y‘ + y) + x z (y‘ + y) = x‘ z + x z = z
yz y
x 00 01 11 10
m0 m1 m3 m2
0
x’y’z’ x’y’z x’yz x’yz’
m4 m5 m7 m6
x 1
xy’z’ xy’z xyz xyz’
z
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THE MAP METHOD

• 1 square represents 1 minterm
– A Term of 3 literals.
• 2 adjacent squares
– A term of 2 literals.
– A term of 1 literal.
– Entire map
– Function F = 1

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THE MAP METHOD

• Example 3.2: Simplify the Boolean function F(x, y, z) = S(0, 2, 4, 5, 6)
yz y
x F = z’ + xy’
00 01 11 10
m0 m1 m3 m2
0
1 1
m4 m5 m7 m6
x 1
1 1 1

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THE MAP METHOD

• If a funtion is not expressed in sum of minterms
– Use the map to obtain the minterms
– Simplify the function and find the minimum number of terms.
– Make sure that the algebraic expression is in sum of products form.

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THE MAP METHOD

• Example 3.2: Simplify the Boolean function F = A’ C + A’ B + A B’ C + B C.
a. Express it in sum of minterms
b. And find the minimal sum of products expression.
BC B F = C + A’B
A 00 01 11 10
m0 m1 m3 m2
0
1 1 1
m4 m5 m7 m6
A 1
1 1

3.2 FOUR – VARIABLE
K-MAP
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F O U R - VA R I A B L E M A P
• 16 minterms
• Combinations of 2, 4, 8, and 16 adjacent squares
yz y yz y
wx 00 01 11 10 wx 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 00
w’x’y’z’ w’x’y’z w’x’yz w’x’yz’
m4 m5 m7 m6 m4 m5 m7 m6
01 01
w’xy’z’ w’xy’z w’xyz w’xyz’
x x
m12 m13 m15 m14 m12 m13 m15 m14
11 11
wxy’z’ wxy’z wxyz wxyz’
w w
m8 m9 m11 m10 m8 m9 m11 m10
10 10
wx’y’z’ wx’y’z wx’yz wxyz’
z z

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• Minimization of four-variable • 2 adjacent squares
Boolean function is similar to – A term of 3 literals.
three-variable functions. • 4 adjacent squares
• Adjacent squares are defined to – A term of 2 literal.
be squares next to each other. • 8 adjacent squares

– Ex: m0 and m2, m3 and m11. – A term of 1 literal.
• 1 square represents 1 minterm • 16 adjacent squares

– Entire map
– A Term of 4 literals.
– Function F = 1

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• Example 3.5: simplify F(w, x, y, z) = S(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)
yz y
wx 00 01 11 10 F = y’ + w’z’ + xz’
m0 m1 m3 m2
00
1 1 1
m4 m5 m7 m6
01
1 1 1
x
m12 m13 m15 m14
11
1 1
w
m8 m9 m11 m10
10
1 1

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• Example 3-6: simplify F = A B C + B C D + A B C D + A B C
CD C
AB 00 01 11 10 F = B’ C’ + A’CD’ + B’D’
m0 m1 m3 m2
00
1 1 1
m4 m5 m7 m6
01
1
B
m12 m13 m15 m14
11
A
m8 m9 m11 m10
10
1 1 1

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• Prime implicant is a product term obtained by combining the
maximum possible number of adjacent squares in the map.
• If a minterm in a square is covered by only one prime implicant, that

prime implicant is said to be essential.

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• Simplify F (A, B, C, D) = (0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
CD C CD D
AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 00
1 1 1 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 01
1 1 1 1
B B
m12 m13 m15 m14 m12 m13 m15 m14
11 11
1 1 1 1
A A
m8 m9 m11 m10 m8 m9 m11 m10
10 10
1 1 1 1 1 1 1 1
D D
Essential prime implicants BD and B’D’ Prime implicants CD, B’C, AD and AB’
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• Essential prime implicants BD and B’D’.
• Prime implicants CD, B’C, AD and AB’.
• Logical sum of two essential prime implicants and any two prime
implicants. There are four possible ways that the function can be
expressed with four product terms of two literals each:
– F = BD + B’D’ + CD + AD
= BD + B’D’ + CD + AB’
= BD + B’D’ + B’C + AD
= BD + B’D’ + B’C + AB’

3.3 FIVE – VARIABLE
K-MAP
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F I V E - VA R I A B L E M A P
• Maps for more than four variables becomes complicated.
• A five-variable map needs 32 squares and a six-variable map needs 64

squares.
• When the number of variables becomes large,
• The number of squares becomes excessively large,
• The geometry for combining adjacent squares becomes more involved.
• Five-variable map: two four-variable map (one on the top of the other).

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A=0 A=1
DE D DE D
BC 00 01 11 10 BC 00 01 11 10
m0 m1 m3 m2 m16 m17 m19 m18
00 00
m4 m5 m7 m6 m20 m21 m23 M22

01 01
C C
m12 m13 m15 m14 m28 m29 m31 m30
11 11
B B
m8 m9 m11 m10 m24 m25 m27 m26
10 10
E E
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• Each four-variable map retains the previously defined adjacency when
taken separately.
• Each square in the A = 0 map is a adjacent to the corresponding square

in the A = 1.
– Ex: m4 is adjacent to m20 and m15 to m31.
• For six-variable map 4 x four-variable maps needed to obtain the required 64

squares.
• Variables > 6 need to many squares and are impractical to use.

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Number
of Number of Literals in a Term in an n-variable
Adjacent Map
Squares
K 2k n=2 n=3 n=4 n=5
0 1 2 3 4 5
1 2 1 2 3 4
2 4 0 1 2 3
3 8 0 1 2
4 16 0 1
5 32 0
Table 3.1 shows the relationship between the number of adjacent squares and the number of literals in
the term.

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• Example 3.7: simplify F = S(0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)
A=0 A=1
DE D DE D
BC 00 01 11 10 BC 00 01 11 10
m0 m1 m3 m2 m16 m17 m19 m18
00 00
1 1
m4 m5 m7 m6 m20 m21 m23 M22
01 01
1 1 1 1
C C
m12 m13 m15 m14 m28 m29 m31 m30
11 11
1 1 1
B B
m8 m9 m11 m10 m24 m25 m27 m26
10 10
1 1
E F = A’B’E’ + BD’E + ACE E

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3.4 PRODUCT OF
SUMS
SIMPLIFICATION
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P R O D U C T O F S U M S S I M P L I F I C AT I O N
• The 1’s placed in the squares of the map represent the
minterms of the function.
• The minterms not included in the function denote the

complement of the function.
• Mark the empty squares by 0’s
• Combine them into valid adjacent squares
• Obtain simplified expression of the complement function F’.

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• Simplify the following function in (a) sum of product and (b) product of
sums:F (A, B, C, D) = (0,1, 2, 5, 8, 9, 10)
CD C
AB 00 01 11 10 F = B’D’ + B’C’ + A’C’D
m0 m1 m3 m2
00
1 1 0 1 F’ = AB + CD + BD’
m4 m5 m7 m6
01
0 1 0 0
Apply DeMorgan’s
B theorem
m12 m13 m15 m14
11
0 0 0 0
A (F’ = (AB + CD + BD’))’
m8 m9 m11 m10
10
1 1 0 1 F = (A’ + B’) (C’ + D’) (B’ + D)

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B’ A’
D’ B’
C’
F F
C’ D’
A’
D D
F = B’D’ + B’C’ + A’C’D F = (A’ + B’) (C’ + D’) (B’ + D)
Sum of Products Products of Sum

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• Consider the function defined in x y z F
Table 3.2. 0 0 0 0
• Sum of minterms: 0 0 1 1
– F (x, y, z) = (1, 3, 4, 6)
0 1 0 0
• Product of maxterms:
– F (x, y, z) = (0,2,5,7) 0 1 1 1
BC B 1 0 0 1
A 00 01 11 10
1 0 1 0
m0 m1 m3 m2
0
0 1 1 0 1 1 0 1
m4 m5 m7 m6
A 1 1 1 1 0
1 0 0 1

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yz y
• Sum of minterms:
x 00 01 11 10
– F (x, y, z) = (1, 3, 4, 6) m0 m1 m3 m2
0
– Sum of products: x’z + xz’ 0 1 1 0
m4 m5 m7 m6
• Product of maxterms: x 1
1 0 0 1
– F (x, y, z) = (0, 2, 5, 7)
– Product of sums: (x’+z’) (x+z)
z

3.5 DON’T CARE
CONDITIONS
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D O N ’ T C A R E CO N D I T I O N S
• The value of a function is not specified for certain combinations of
variables
– BCD; 1010-1111: don't care
• These don’t care conditions can be used on a map to provide further

simplification of the Boolean expression.
• Don’t care minterm is a combination of variables whole logical value is

not specified.

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• It cannot be marked with a 1 in the map
– It would require that the function always be a 1 for such combination.
• It cannot be marked with a 0 in the map

– It would require that the function always be a 0 for such combination.
• For don’t care conditions an X is used.
• For adjacent squares in the map to simplify the function

– The don’t care minterms may be assumed to be either 0 or 1.

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• Simplify the Boolean function F (w, x, y, z) = (1, 3, 7, 11, 15)
– Don’t care conditions d(w, x, y, z) = (0, 2, 5).
yz y yz y
wx 00 01 11 10 wx 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 00
X 1 1 X X 1 1 X
m4 m5 m7 m6 m4 m5 m7 m6
01 01
0 X 1 0 0 X 1 0
x x
m12 m13 m15 m14 m12 m13 m15 m14
11 11
0 0 1 0 0 0 1 0
w w
m8 m9 m11 m10 m8 m9 m11 m10
10 10
0 0 1 0 0 0 1 0
F = yz + w’x’ F = yz + w’z
z z
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• Don’t care minterms in the map are initially marked with X’s.
• The choice between 0 and 1 is made depending on the way the incompletely
specified function is simplified.
• Once the choice is made,
– the simplified function obtained will consist of a sum of minterms
– including those minterms that were initially marked with X’s and
– have been chosen to be included with 1’s.
• F(w, x, y, z) = yz + w’x’ = (0, 1, 2, 3, 7, 11, 15)

• F(w, x, y, z) = yz + w’z = (0, 1, 3, 5, 7, 11, 15)

3.6 NAND AND NOR
IMPLEMENTATIONS
48
N A N D A N D N O R I M P L E M E N TAT I O N S
NAND Circuits:
Inverter x x’
• The NAND gate is a universal
gate.
– Can implement any digital
system. x
AND xy
– Complement operation is y
obtained from one-input NAND
gate.
– AND operation requires two
NAND gates x
– OR operation is achieved
through NAND gate with OR (x’y’)’ = x + y
additional inverters in each
input y

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NAND Circuits:
• Two graphic symbols for NAND gate
x x
y (xyz)’ y (x’ + y’ + z’) = (xyz)’
z z
(a) AND-invert (b) Invert-OR

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• The implementation of Boolean functions with NAND gates
– Require that the function be in sum of products form.
– F = A.B + C.D
A A A
B B B
F F F
C C C
D D D
(a) (b) (c)
(a) F = A.B +C.D (b) F = ((A.B)’)’ + ((C.D)’)’ (c) F = ((A.B)’ (C.D)’)’

= (A+B)’ + (C+D)’ = ((A+B) (C + D))’
= A.B + C.D = A.B + C.D
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• Implement the following Boolean function F = (x ,y, z) = (1, 2, 3, 4, 5, 7).
– Simplify the function in sum of products using K-map.
yz y
x F = z + xy’+ x’y
00 01 11 10
m0 m1 m3 m2
0
1 1 1
m4 m5 m7 m6
x 1
1 1 1

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yz y
x 00 01 11 10 F = z + xy’+ x’y
m0 m1 m3 m2
0
1 1 1
m4 m5 m7 m6
x 1
1 1 1
z
x x x
y’ y y’
x’ x’ x
F F F
y y y
z z z’
(a) (b) (c)

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• The procedure
– Simplify in the form of sum of products;
– Draw a NAND gate for each product term;

 The inputs to each NAND gate are the literals of the term (the first level);
– A single NAND gate for the second sum term (the second level);
– A term with a single literal requires an inverter in the first level if the
single literal is not complemented. Otherwise it can be connected
directly.

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• General procedure for converting multilevel AND-OR diagram into all
NAND diagram:
– Convert all AND gates to NAND gates with AND-invert graphic symbol.
– Convert all OR gates to NAND gates with invert-OR graphic symbol.
– Check all the bubbles in the diagram.

• For every bubble that is not compensated by another small circle along the
same line,
• insert an inverter (one-input NAND gate) or
• complement the input literal

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• F = A (CD + B) + BC’
C
B F
C’
(a) AND-OR gates
B F
C’
(b) NAND gates

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• F = (AB’ + A’B) (C + D’)
A
B’
A’
B F
D’
(a) AND-OR gates
B’
A’
B F
C’
(b) NAND gates

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• NOR function is the dual of
Inverter x x’
NAND function.
• The NOR gate is also x

OR x+y
y
universal.
AND (x’ + y’)’ = x y

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NAND Circuits:
• Two graphic symbols for NAND gate
x x
y (x+y+z)’ y (x’ y’ z’) = (x + y + z)’
z z
(a) OR-invert (b) Invert-AND

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• Example: Implementing F = (A + B) (C + D) E
A
B’
F
E’
• Example: Implementing F = (A B’ + A’ B) (C + D’)

A’
F
A
B’
D’

3.7 OTHER TWO
LEVEL
IMPLEMENTATIONS
61
OT H E R T WO L E V E L I M P L E M E N TAT I O N S
• NAND and NOR gates most often found in integrated circuits.
• NAND and NOR are the most important gates from a practical point of
view.
• Some NAND or NOR gates allow the possibility of a wire connection
between the outputs of two gates to provide a specific logic function.
• This type of logic is called wired logic.
• Example:
– Open-collector TTL NAND gates when tied together performs wired-AND
logic.

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• Example:
– Open-collector TTL NAND gates when tied together performs wired-AND
logic.
– The wired – AND gate is not a physical gate, but only a symbol to designated
the function obtained from the indicated wired connection.
– F = (AB)’ ∙ (CD)’ = (AB + CD)’

A A
B B
F=(AB + CD)’ F=[(A+B) (C+D)]’
C C
D D
(a) Wired-AND in open collector TTL (b) Wired-OR in ECL gates

NAND gates OR-AND-INVERT
AND-OR-INVERT

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Nondegenerate Forms
• Consider four types of gate: AND, OR, NAND and NOR.
• Assign one type of gate for the first level and one type of gate for the
second level.
• There are 16 possible combination of two-level forms.
– Eight of them: degenerate forms = a single operation

• AND-AND, AND-NAND, OR-OR, OR-NOR, NAND-OR, NAND-NOR, NOR-
AND, NOR-NAND.

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degenerate forms = a single operation
Logic Operation Circuit Diagram
A A.B
AND-AND
F=A.B.C.D
D C.D
A A.B
AND-NAND
F=(A.B.C.D)’
=A+B+C+D
C
D C.D

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A A+B
OR-OR F=A+B+C+D
D C+D
A A+B
OR-NOR
F=(A+B+C+D)’
=A.B.C.D
C
D C+D

66
A (A.B)’
NAND-OR F=(A.B)’+(C.D)’
=A+B+C+D
C
D (C.D)’
A (A.B)’
NAND-NOR
F=((A.B)’+(C.D)’)’
=A.B.C.D
C
D (C.D)’

67
A (A+B)’
NOR-AND F=(A+B)’.(C+D)’
=A.B.C.D
C
D (C+D)’
A (A+B)’
NOR-NAND
F=((A+B)’.(C+D)’)’
=A+B+C+D
C
D (C+D)’

68
– The eight non-degenerate forms
• AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR, NAND-AND, OR-
NAND, AND-NOR.
• AND-OR and NAND-NAND = sum of products.
• OR-AND and NOR-NOR = product of sums.
• NOR-OR, NAND-AND, OR-NAND, AND-NOR = ?

69
AND – OR – INVERT Implementation
• The two forms NAND – AND = AND – NOR
• Both perform the AND – OR – INVERT function.
• F = (AB + CD + E)’
• F’ = AB + CD + E (sum of product)
A A.B A A.B A A.B
B B B
C.D C.D C.D
F F F
C C C
D D D
E E E
(a) AND-NOR (b) AND-NOR (c) NAND-AND

70
OR – AND – INVERT Implementation
• The two forms OR – NAND = NOR – OR
• Both perform the OR – AND – INVERT function.
• F = [(A+B) (C+D) E]’
• F’ = (A+B) (C+D) E (product of sum)

A A+B A A+B A (A+B)’
B B B
C+D C+D (C+D)’
F F F
C C C
D D D
E E E
(a) OR-NAND (b) OR-NAND (c) NOR-OR

71
Equivalent Implements the Simplify To get
Nondegenerate Function F’ an output
Form in of
(a) (b)*
AND- NAND-AND AND-OR-INVERT Sum of products F
NOR by combining 0’s
in the map
OR- NOR-OR OR-AND-INVERT Product of sums F
NAND by combining 1’s
in the map and
then
complementing
*Form (b) requires and inverter for a single literal term.
72
yz y
• Example 3-11: F' = x'y+xy'+z x 00 01 11 10
(F': sum of products) m0 m1 m3 m2
0
1 0 0 0
– Step1: x’y (z + z’) = x’yz + x’yz’
m4 m5 m7 m6
x 1
– Step2: xy’(z + z’) = xy’z + xy’z’ 0 0 0 1
– Step3: z (x + x’) = xz + x’z

z
– Step4: xz+x’z (y+y’) = xyz + x’yz
F’ = z + xy’ + x’y
+ xy’z + x’y’z
– Step5: x’yz + x’yz’ + xy’z + xy’z’+
xyz + x’y’z

73
• Example 3-11: F' = x'y+xy'+z (F': sum of products)
x’ x’
y y
F F
x x
y’ y’
z z
AND-NOR NAND-NAND
• AND-OR-INVERT

74
yz y
• AND-OR-INVERT form require a
x 00 01 11 10
simplified expression of the m0 m1 m3 m2
0
1 0 0 0
complement of the function in
m4 m5 m7 m6
product of sums. x 1
0 0 0 1
– Combine the 1’s in the map

z
• F = x’y’z’ + xyz’ x x
y y
z z
– Take the complement F F
x’ x’
• F’ = (x+y+z) (x’+y’+z) y’
z y’
z
• F = [(x+y+z) (x’+y’+z)]’
(a) OR-NAND (c) NOR-OR

75
• Summary
– F' = x'y+xy'+z (F': sum of products)
– F = (x'y+xy'+z)' (F: AOI implementation)
– F = x'y'z' + xyz' (F: sum of products)
– F' = (x+y+z)(x'+y'+z) (F': product of sums)
– F = ((x+y+z)(x'+y'+z))' (F: OAI)

3.8 EXCLUSIVE-OR
FUNCTION
77
E XC LU S I V E - O R F U N C T I O N
• Exclusive-OR (XOR)
– x  y = x y‘ + x‘ y
– F = 1, if only x = 1 or y = 1, but not when x and y = 1.
• Exclusive-NOR (XNOR) (equivalence)

– (x  y)' = x y + x‘ y‘
– F = 1, if both x and y = 1 or both = 0.
– (x  y)’ = (x y’ + x’ y)’ = (x’ + y) (x + y’) = x’x + x’y’ + xy = xy + x’y’

78
• Some identities • Commutative and associative
– x0=x – AB=BA
– x  1 = x' – (A  B)  C = A  (B  C)
– xx=0 =ABC
– x  x' = 1
– x  y' = (x  y)'
– x‘  y = x’  y = (x  y)'

79
x
• Implementations
x⊕y
– (x‘ + y') x + (x‘ + y') y

y
= x y‘ + x‘ y = x  y (a) with AND – OR – NOT gates
x⊕y
(b) with NAND gates

80
• The XOR operation with three or more variables can be converted into
an ordinary Boolean function by replacing  symbol with its equivalent
Boolean expression.
– ABC = (AB'+A'B)C' + (AB+A'B')C
= AB'C'+A'BC'+ABC+A'B'C
= S(1, 2, 4, 7)
– XOR is a odd function → an odd number of 1's, then F = 1.
– XNOR is a even function → an even number of 1's, then F = 1.

81
yz y yz y
x 00 01 11 10 x 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
0 0
1 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6
x 1 x 1
1 1 1 1
z z
(a) Odd Function (b) Even Function
F=AC F = (A  B  C)’
A A
B x⊕y B (x ⊕ y)’
C C
(a) 3-input odd function (b) 3-input even function

82
• Four-variable Exclusive-OR function
– ABCD = (AB'+A'B)(CD'+C'D) = (AB'+A'B)(CD+C'D')+(AB+A'B')(CD'+C'D)
yz y yz y
wx 00 01 11 10 wx 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 00
1 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 01
1 1 1
x x
m12 m13 m15 m14 m12 m13 m15 m14
11 11
1 1 1 1
w w
m8 m9 m11 m10 m8 m9 m11 m10
10 10
1 1 1 1
z z
F = ABCD F = (ABCD)’
83
• Parity Generation and Checking
– A parity bit: P = x  y  z
– Parity check: C = x  y  z  P
• C=1: one bit error or an odd number of data bit error
• C=0: correct or an even # of data bit error
x x
y P y C
z
z
P
(a) 3-input odd function (b) 3-input even function

84
Three-Bit Message Parity Bit
x y Z P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

85
Three-Bit Message Parity Error Check
x y Z P C
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

3.9 HARDWARE
DESCRIPTION
LANGUAGE
87
H A R DWA R E D E S C R I P T I O N L A N G UAG E
• Describe the design of digital systems in a textual form
– Hardware structure
– Function/behavior
– Timing
• VHDL and Verilog HDL

88
Specification
RTL design and Simulation
Logic Synthesis Gate Level Simulation
FPGA
ASIC Layout
Implementation
LOGIC DESIGN
89
• Documentation language
• HDL is used to represent and document digital systems in a form

that can be read by both humans and computers
• Examples of keywords:
– module, end-module, input, output, wire, and, or, and not

90
A
g1 w1
B g3 x
C g2 y
//Description of Simple circuit

module smpl_circuit (A, B, C, x, y);
input A, B, C;
output x, y;
wire w1;
and g1 (e, A, B);
not g2 (y, C);
or g3 (x, e, y);
endmodule

91
• Boolean expressions are specified in Verilog HDL with a
– continuous assignment statement consisting of the keyword assign
followed by a Boolean expression.
• To distinguish the arithmetic plus from logical OR, Verilog HDL

uses the symbols
– (&) for AND,
– (|) for OR,
– (~) for NOT

92
A //Description of Simple circuit

g1 w1
B g3 x module smpl_circuit (A, B, C, x, y);
input A, B, C;
output x, y;
C g2 y assign x = (A & B) | ~C
assing y = ~C
endmodule
• Boolean expression:
– x = A.B + C’
– y = C’

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2

The Map Four – Variable Product of Don’t Care

NAND and NOR Other Two Exclusive-OR Hardware

THE MAP METHOD

November, 2022 LOGIC DESIGN

THE MAP METHOD

– The Karnaugh map

• A pictorial form of a truth table

• Applicable if the # of variables < 7

November, 2022 LOGIC DESIGN

THE MAP METHOD

• The simplified expression produced by the map are always in

November, 2022 LOGIC DESIGN

THE MAP METHOD

– Sum of products (or product of sum) in the simplest form

– A minimum number of terms

– A minimum number of literals

– The simplified expression may not be unique

November, 2022 LOGIC DESIGN

THE MAP METHOD

– x' = row 0; x = row 1 1 m2 m3

– y' = column 0; y = column 1

diagram 0 x’y’ x’y

Figure 3.1 Two-variable Map

November, 2022 LOGIC DESIGN

THE MAP METHOD

– x+y = x'y+xy' +xy = m1+m2+m3 (a) xy

THE MAP METHOD

November, 2022 LOGIC DESIGN

THE MAP METHOD

November, 2022 LOGIC DESIGN

THE MAP METHOD

– m0+ m2 = x'y'z' + x'yz' = x'z'

x 1 xy’z’ xy’z xyz xyz’

November, 2022 LOGIC DESIGN

THE MAP METHOD

November, 2022 LOGIC DESIGN

THE MAP METHOD

November, 2022 LOGIC DESIGN

THE MAP METHOD

• The number of adjacent squares that may be combined

• Larger number of adjacent squares

November, 2022 LOGIC DESIGN

THE MAP METHOD

THE MAP METHOD

November, 2022 LOGIC DESIGN

THE MAP METHOD

November, 2022 LOGIC DESIGN

THE MAP METHOD

– Simplify the function and find the minimum number of terms.

– Make sure that the algebraic expression is in sum of products form.

November, 2022 LOGIC DESIGN

THE MAP METHOD

November, 2022 LOGIC DESIGN

November, 2022 LOGIC DESIGN

be squares next to each other. • 8 adjacent squares

• 1 square represents 1 minterm • 16 adjacent squares

November, 2022 LOGIC DESIGN

November, 2022 LOGIC DESIGN

November, 2022 LOGIC DESIGN

• If a minterm in a square is covered by only one prime implicant, that

November, 2022 LOGIC DESIGN

November, 2022 LOGIC DESIGN