8 BIT FULL ADDER – Verilog

Verilog Code:

module b8fa(a,b,cin,sum,cout);
input [7:0] a;
input [7:0] b;
input cin;
output reg [7:0] sum;
output reg cout;
always@(a,b,cin)
{cout,sum}=a+b+cin;
endmodule
Test Bench Code:

module b8fa_tb;
reg [7:0]tba;
reg [7:0]tbb;
reg tbcin;
wire [7:0]tbsum;
wire tbcout;
b8fa
utt(.a(tba),.b(tbb),.cin(tbcin),.sum(tbsum),.c
out(tbcout));
initial begin
tba=1'b0;
tbb=1'b0;
tbcin=1'b0;
#100;
tba=8'b00110111;
tbb=8'b00000101;
tbcin=1'b0;
#100;
tba=8'b00110000;
tbb=8'b00000110;
tbcin=1'b0;
#100;
tba=8'b01011110;
tbb=8'b00000100;
tbcin=1'b0;
#100;
tba=8'b01101110;
tbb=8'b00000011;
tbcin=1'b0;
#100;
tba=8'b01101111;
tbb=8'b00000111;
tbcin=1'b0;
#100;
tba=8'b01110000;
tbb=8'b00001000;
tbcin=1'b0;
#100;
tba=8'b11111111;
tbb=8'b00000000;
tbcin=1'b1;
end
endmodule