4.1 INTRODUCTION So far, we have studied the analysis and design of combinational circuits, whose outputs ‘at any instant of time ate entirely dependent upon the inputs present at that time. It constitutes 3 Sia part of digital stems. There are many applications in wbich digital outputs are required Lf be generated in accordance with the present inputs end previous state of the circuit This reapirement cannot be stisfied using a combinational logic system. These applications require + culputs to be generated that are not only dependent on che present input conditions, but hey Bao depend upon the past history of these inputs, The past history is provided by feedback fom the outpule back io the input These cieuits include the memory elements and ate called 2s “sequential cir “The block diagram of a sequential circuit is shown in Fig. 4.1. It consists of a combinational circuit fo which memory elements are connected to form a feedback path. Outputs Inputs Combinational | Feedback path [Memon lement Fig. 4.1 Block diagram of a seqtential circuit, ‘The memory elements are devices capable of storing binary information within them. The tinay information stored in the memory elements at any given time defines the “sale” of the Zguenial cau, The sequential cra receives the birary information from exiemal inputs ‘These inputs and the present state of memory element determine the binary value of the cua ofthe creut. They also determine the condition for changing the state in the memory dlements, Thus, the next sate ofthe memory elements i also a function ofthe extemal inputs. {>and the present state. A sequential circuit is specified by a time sequence of ts, Outputs and intemal states. The sequential circuits can be dassfed in two ways depending on the timing of their signals They are «29i . e BASIC DIGITAL ELectRoy, 490 ss sequential circuits 1. Synchronou ial circuits 2. Asynchronous sequen ae behaviour con be defined from te ledge of ce jgnals can affect the memes ‘sats any wf ose HS I tre ako called as “clocked “sequential whos Tn asynchronous sequential circuits, change in. input signals con affect_memony element at any indant of fine; Le, the behaviour of an asynchrore suential circuit depends upon the Fn input signals change and can be affected # OS instant of time. These are oer ac uncloked sequental cats. The memory Alene ‘used in both cases are fip- ae coh ate capable of soring Lit binary information, Tipflop circuit has two outputs, fons whey Ocal value and othe f the complement valve ot the bit stored in it, Before ers to study the operation and 'ypes of fip-lops it's Nate to introduce the comparison Fe a patna a sequerdl| vou ee) Tobe] and COND between eNonous and agnchzoncus sequential crus (ee Table 4 2) Table 4.1 j Gircuits.” Sequential circuits ‘Sl.No Combinational crus [Rac whe ouput dependent only [ 1 A clout whose oxi Tepends not only on] Sc eter va coer (cl iTa] [a ome ec the past history) on the Int tanta ony marcy | of the inpus (on) A cit hat conning a Jeast one memory element Ea Combinational [774 % ercut Jy Feedback foal! eae present | 2. Output = f (present input, presen tts) New stoie = f (resent input, present state) 3, Sequential circuits re comperatively harder to design bat require less hardware 2. |Combinationa creut output tps) (No memory elements so no sas) 3, | Combinational eruits are easy to design but require more hardware. 4, | Combinational cei are fasterin speed, because, delay between inputand output i dueto propagation delay of gates. 5, |More expensive circuit. 6, |Designer has less flexibility since the output depends only on the present inpus. Exemple = Parallel adder The behaviour is defined by the set of | 8- output functions only. 4. Sequential circuits are slower than the combinetional circuits because of memory tlements (or) delay elements. 5, Cheaper circuit 16. Designer has more flexibility because, thel ‘output depends on both present input and pas history of input: functions and next state functions“Asynchrorous saquentil circus FE whose behaviour is defined from the Kouedge of is signals at discrete instants fof time, ’e, the input signals can affect the memory elements upon the activation of # the dock pulse. Here the memory elements are clocked fip- flops. ‘Sunehronizaion is employed by the help of clock pulses. : ‘The maximum operating speed of clock depends on time delays involved 2. FLIP-FLOPS We know that a sequential Bie of the circuit. This information must Mombinasional, according fits, ROM has no memory. (The memory idficions relationship between A fipflop isa circuit that Jagnal to suitch states. Therefore Fe ready to use i, The bask Faith two stable states Le., output is eith maintains its output state It always stores 1-bit information. “4.2.1 Basic Building Block Now we wall I obtained by cross-coupling ‘The circuit may be in y = 0G For it may be in y = When y = 0 (assume) then A gate y becomes 0. needs at least one memory element to store # ‘oe stored at least one clock signal period (in case of Be focked sequential circuit) or untl the input signals Sica). As toon as we said memory device wh n the output vari ‘The behaviour of asynchronous sequential circuit depends upon the order in which the inputs change. and the sfate of the circuits can be affected, at any instant of time, ie, the change in the input signals can affect memory element at any instant of time “The memory ements are either unclocked ip- ops (or) time delay elements Here no syrchronisation, hence it 8 8 combinational cieult wth feedback. Because of absence of clock, asynchronous CGreils can operate faster than synchronous More dificult o desin present ‘change (in case of unclocked sequential hat we wil get info mind is ROM. But ROM is atthe above discussion of storage element needed in sequential ‘of a ROM refers the fact that i les and the input variables) nntain the binary state indefinitely unt directed by en i the storage device must relain te stored in a acini for this storage is 2 flipsiop (abbreviated as FF). Its a device rer to OV (logic 0) or + 5 V de (log (Gther 0 or 1) untl directed by an input signal to change is state $0 it is also called L-bit memory unit. ‘memoraes” the ut 1). A flip-top seo 0 storage device capable of string bit. The basc digital memory circuit ‘of two NOT gates Nj and Np as shown in Fig. 42. ) sate called sate yy 1 (p = 0), called Y’ sate, These states stable and consistant withthe inferconnecions. 1, because through NOT B 5 Ne Fig. 4.2 Basic bullding blockBASIC DIGITAL &, mR (oT gate 5 g = is then B = 0, os pastes A Ba FP eratochad bn a Jong time. Since this in ate These cue Lat menawy ee! Tt strage el: The output es tod ed to the input ofthe ober, and this Feedback combination i ae Tab ‘onnetion. Since the "lp hes two sates, it sao caled 6 binary (ot) Bi erersit (latch) does not provide any mechanism to wite data into it Hen : necessity to modify the basic building block i a rehere are many types of fips. The major diferences OH various types of flip-! ac he uber of inal they process and the manner in ‘which the inputs affect their output ‘sate, The types of flipflops are a (2) RSelipflop (2) JKfip op (3) D-fip flop (4) Tip flop. 4.2.2 RS-Flip flop “The simplest type of fip-fop is the Reset Set fp op (RS). It can be constructed from either two NAND gates or two NOR gates. RS-flip flop using NOR gates. The Fig. 4.3 shows the RS fipfop using two NOR gates. The two NOR R (Rese!) gates are cross coupled so that output of NOR gate 1 Q i connected to one of the inputs of NOR gate 2 and vice-versa. The flip flop, has two outputs Q and G, and ‘wo inputs, set and reset - ‘As we know that, logic 1 at any input of aNoR (Se . : gate forces its output to a logic 0. Let us see the operation fof this circuit for various input possiblities. ‘ Case (i) R = 0 and S = Fig. 4.3 RSFF using NOR gates, ‘L In this caso, S input of NOR gate 2 is at logic 1, hence its tet eee 0 ws tes ta bath inal oFNOR aut Tae tee | Hroupal Tis at loge 1, as shown in Fg @Siol, {tone 0 So Pal J 1 (es) =1 0 1 Q } 0 Q ° oe 18 gpei-o Lo Fig, 4.310) Fig. 4.30) eS Case (i R = Land $ = 0.1n the NOR, x ol ate 1 is at logic ww capa i wingic 0: Ths ince ese of ao ce cones) tao pus as shown inFig. 43 (b]> Land Q = 0. With @ =INTRODUCTION TO SEQUENTIAL CIRCUITS - noe po Case 5.1 and S = 1. Wh ot and § = 1, nen tnt et og hoya Os eae Be nero Le, = Sond 0. ieee no m2 1 Na oo ernd Gi ts complement, ten Q = for ay codon Sane a archon (ratte co mide ts cro aT normal operation, this concition must be avolded. This i shown Fig. 43 (d) : s-1—— Fig. 4.316) Fis. 4.314) hula cf BS Sip 5 vow in Fg. 4 (a) en wu le shown in Fig 4.4(b) q — wslo 9 | Sue rR J+a my No cena ‘ fF | ot Set all | 08 10 Reset é a : a4 Indeterminate | F Fig, 4.410) Symbst Fe. 4.806) Th le : NC-No change summary 1. When both inputs oe tus the otra Ss ot change and fiplop remains Ech ine as ate This state a0 Caled 25 19 change o inactive sate DLL 1 (Set state) Bo nen R= 1, S = 0, the outs of fon 9 (Reset state) wt When R and inputs both are high, output unpredictable, This state is called B “indeterminate state” Bs flip-flop using NAND sates. We can construct the RS flip-flop using NAND gotes as shown in Fig. 45: Re— s : Fig, 4.5(e) Basic crcl. Fig, 4.5(b) With bubbled AND gotebed INTRODUCTION TO SEQUENTIAL CIRCUITS 433 pow Cose ia). 5 1 and S = 1. When both inputs ere at Joo 1, they force the outputs of both NEB gates fo losic 0! ie, Q = Cand Q = 0 nee ot iknow that Q is a logic binary oe and @ is ts complement, then Q » for any condition ‘So we call this condition (or) state 2 an “i normal operation, this condition must be avoid ndeterminate state OF Jed. This is shown in Fig. 43 ( Fig. 4.314) Fig. 4.3(€) ‘The symbol of RS flipsfop is shown in Fg, 44 fe) and its tuth table is shown in Fig 4. — rhe es Sa 5 BST RENC | No chnge FF ° a. ‘Set | — 3 10/5 1] ret. | —_ 11 | «_x_| tndetermine Fig, 4.440) Sol fig 4.40) Toth be 'NC-No change az ave lou, the output doesnot change ane Mop ramen? Summary 1. When both input E chen in is last state. This sale a0 ‘eifed as “no change of inactive sa og a 1, The Q output of Tipsop at loi? (Get state) « at logic 1 (Reset state) the © output of fipsep predictable. This state is called tooth are high, output 1 unt 4, When Rand S inputs ‘indeterminate state" se We can eonsuct the RS fipslop using NAND gees 9 RS flip-flop using NAND sate shown in Fig. 45. R ne ce s 8 Fig, 4.5(b) With bubbled AND gote 1a, 4.5(a) Basic ccaBASICDIGMAL peas R Q Q Q 5 : Fig, 4.5(e) Changing bubble Fig. 4.5(d) RS flip-flop with NAND oes \ Fra, 46 shows the loge symbol and truth table of He RS fip-op. (R[s[o]o ” Se = Pe pte TEEPE] eae cE s 7a ofr} o] 2 Reset ojo] i 1_| Undeterminate : Fig. 4.6(b) Truth table. Fig 4.610) Le obo Operation : We know that a fw on any input to a NAND gate forces it output high (FS = 1, R= 0, t ils the RS fipflop te, Q= 1 and.Q = 0. iy WS = 0, B= 1,1 wil seat the FS fipsfop i2, Q = O and Q = 1 (uw) 1S = = 1, the fipsiop wil remain in ts previous state (iu) IS = R =O, the fipfop output is unpredictable |) Bxaniple 4.1. The fllsing waveforms ore gppied othe Inputs of RS ft termine + output waveform. Assume initialy Q = 1 (see Fig. 4.7). ee Solution. See Fig. 4.7 Fig. 47 Example 4.2. Obtain the output wave: form, when the following waveforms are applied § tothe RS flpflop. (Assume intially Q = 1) (see Fig. 47 (al) Solution. See Fig. 4.7(0)= BASIC DIGITAL, ot R Q R Q a 1) 5 s Jp with NAND gees ig. 4.56) Changing babble fig. 4.5(d) RS fio vedic symbol and trth table of the FS flip-flop. Fig. 4.6 shows the fe[s| o| 2 a i. NC ig chonse | : - Y Set 5 a ° Reset 1 1 |undeterminat Loge ome Fa 4.64) Th tbl pune ht ow os pt = RAND gt oe 1 bs MEN | 0, it wil eet the RS fipflop Le, @Q = band. = 0. | 1 BE fip-top ie, Q= O and Q = 1 Fa i eet te fp wil remain is prevous state 0, the fipflop output is unpreditabe | jones ore apie to the inputs of RS flip-flop. Deter corso pre RS fipsop. Determine Woy HS = RB / Example 4.1, The oliowina a ‘output waveform. Assume intially Q Solution. See Fig. 4.7 Example 4.2. Obtain the output wave. orm, when the following waveforms are applied to the RS flip-flop, (Assume intially Q = 1) (see Fig. 47 (a}) Solution. See Fig. 47(c) Undetermined states 4 Fig. 4.7 (0)4.2.3 Clocked RS-Flip-Flop The basic RS fipfop is an asynchronous transparent sequential circuit This means that ny change in the input of or immediatly to the output at Q and @ ccording to the truth table. The operation of the basi fplep can be modified by providing {an additional control input that determines when the sate of fhe celts to be changed. This additional contol input is called ‘clock’ or “clock pulse". With this clock, the flip-flop is called Bij 9. smchtanous~device. The term synchrénous indicates that the output changes its state only ata aint according io an input, ie, the changes in the output occu in synchronous With the clock. By adding gales to the input of the basic crt the fi-fop can be made to respond to input levels during the occurrence of a cock pulte * An RS-flip-flop with a clock pulse is shown in Fig. 480, It consists of basic NOR fiplop Greuit and two AND gates at the input. The AND gates remain at 0" as long as the dlck pulse {CP) is ‘0, regardless of the R and S inputs. When the cock pulse goes to 1, information frm Rand S inputs is allowed to reach the basic fipslop. The lbgie symbol and truth table for = docked RS-fip-lop are shown in Fig, 4.8 (b) and 4.8 (c) respectively — y cP (Clock, | ‘Ses Ly Lon se Fig. 4.80) [elatstotol sae] [OP OTOTNCP NC] Re charae [0 [o[a|Nc| nc | Nochanse 0 | 2 [o|Ne| Ne | Nochange z @ B |i] |Ne| Ne | Nochange i F 1 | 0/0] Nc| Nc | Nochange fe ac Pfolt]r|'o | “se r]tfof ofa | pe 1 LAPT] & | x | indeterminate Fig, 4.8(b) Losic symbol ‘An example of input and output Aig. 4.8(c) Truth table sevdcae a pton we own’ TTL ae afl : Ee s . fe Fig. 4.80)INTRODUCTION To SEQUENTIAL CIRCUITS 4.2.3 Clocked RS-Flip-Flop | __ The basic RS fipflop is an asynchronous transparent sequential circuit, This means that any change in the input of R or § is tansmited immediatly to the output ot Q and Q Ee according to the truth table, The operation of the basic fipslop can be modified by providing San additional control input that determines when the state of the circuit isto be changed. This additional control input is called “clock” or “clock pulse". Wits this clock, the fipslop is called 4 ‘sunchronous-device."The term synchronous indicates thatthe output changes is state only "die specified point according to an Input, fa, The changes inthe output occur in synchronous ‘fith the clock. By adding gaies to the input of the basic cc the fip‘fop can be made to BF i Pa. 41te) Loge nmol A120) Tuo, Pa 418 Sut ra dg 4.2.5 D Flip-Flop By seeing the truth table of RS fipfop, we can realize that when both Inputs are same, the ouput ether does not change ori 's unpredictable (If inputs are 00, no change and inputsa INTRODUCTION To SEQUENTIAL CIRCUITS 439 fe ch cles Toles input conitons can be evoked by making them complement of Sette, The modified cocked SR fip-op is known as Dfipfop, The Fg, 410) sow the D fipop, The D fip-ep has only two inputs D and CP and two outputs Q and Q. The "put goes directly to the S input, and its complement is applied to the R-input. oT} y Q — Qi dD [ar+y cet 4 apoyo oneal p-—2 a 1}o] o {5 ata L Fig. 4.19(2) Loic dingo Fig, 4.1916) Characteristic tbe D 2 ° 1 ioute—[D 1 if | Outputs Clock qe Gs Qt+n=0 Fig. 4.13(c) Characteristic equation. » Fig. 4.13(d) Logic symbol. Operation : 1. When clock pulse is 0, The outputs of gate 3 and gate 4 are atlogie 1 level and the eieut eannct change stale regardless ofthe value of D. 2, When CP = 1. (0) If D = 1. The output of gate 3 is at logic O and gate 4 is af logic 1. With this, the output of gate 1 is at logic 1 and gate 2 is at logic 0, te, Q = 1 {b) If D = 0. The output of gate 3is at logic 1 and gste 4 is at loge 0. With this, the output of gate 1s at logic O and gote 2 is at logc 1, Le, Q = 0. ‘The D-fip flop receives the destination from its ability to hold “data” into its intemal storage: This type of fp flop is sometimes called a “gated Diatch”. The CP input enables the Guted latch to make possible data entry ino the cicut. The binary information present at the Sele input of the D fiptop is transfered to the Q output when the CP input is enabled. The Sutput folows the data input as long as the clock pulse is in 1 state with just delay equal to Getee propagation time. Because of ths, this flip-flop is called “delay fipslop’ When the clock pulse goes to 0, the binary information that wos present atthe data input at the time the pulse transiion occured is retained at the Q output unt the pulse input is tnabled agein. The characteristic table forthe D flop is shown in Fig. 4.13(b). From the fable, we condude that the next state ofthe fipflop is independent of the present state and. is equal to the input D.i INTRODUCTION TO SEQUENTIAL CIRCUITS 439 1, unpredicta ph se ele iiese input conditions can be avoided by making them complement of the D thor Tne’ clocked SR fip flop is known as D fipfop. The Fig 4.13) shows Dear tor The D flipslop has only two inputs D and CP and two outputs Q and G. The put goes directly to the S input, and its complement is applied to the R-input. pe ?) Q — QD [aren ceo aot e ofi] a D 2) a ajo] o {5 aja 1 Fig. 4.13(@) Logie dogrem. Fig, 4.13(6) Characteristic table. D Owe ° L input IQ j Outputs : ‘ Clock —4 Qt+ = Fig. 4.18(c) Characteristic equation Fig, 4.18(@) Logie symbol Operation : 1. When clock pulse is 0. The outputs of gate 3 and gate 4 are at logic 1 level and the circuit eannot change state regardless ofthe value of D 2. When CP = 1. (c) If D = 1. The output of gate 3 is at logic O and gate 4 is at logic 1. With this, the output of gate 1 is at logic 1 and gate 2 is at logic 0, Le, Q= 1 (6) If D = 0. The output of gate 3 is at logic 1 and gate 4 is at logic 0. With this, the output of gate 1 is at logic 0 and gate 2 is at logic 1, Le,, Q = 0. ‘The D-ip flop receives the destination from its abiliy to hold “data” into is intemal storage This fype of Tip lop is sometimes called a “gated D:lach”. The CP input enables the uted latch to make possible data enty into the creut. The binary information present at the sete input of the D fiplop is transfered to the Q output when the CP input is enabled. The tutput folows the data input as long as the clock pulse is in 1 state with just delay equal to Gates propagation time. Because of ths, this fip-lop is called “delay fipslop”. When the clock pulse goes fo 0, the binary information that was present at the data input at the fime the pulse transition occurred is retained at the Q output until the pulse input is ‘enabled again, The characteristic table for the D fip-op is shown in Fig. 4.13(b). From the fable, we condude that the next state of the fipflop is independent of the present state and is equal to the input D.¥ BASIC DIGITAL ELECTION, 4 : fon is tained fom FB 413 {e) and the srephic symbol leis, 413 (a) gare) noun 9 8 é re outpak wavs Tee is shown in Fig. 413 (2) rg, 4.13) Ing ond oueut woven of 0 flipslop : te sate dageam af the D fips i shown Fig. 413 W. Gps = . W pig ais & example 43. Design 0 duide-by ~ 2 dreut We D fip-lops Solution, ID fipsion has is Q. cule connected to ts D input, the circuit will deve ty na the signal ppd 1 is dk neu Te creer coanecion is shown in Fig. 4.244@) eae an Ot ee eee eae 0) ee eee Q-00=D=1 Tresecond dock pulse (=1) wil cause the dc f9 quitch 19 Q = 1, @ =D =Oand soon Fre eit waveforms ae sven in Fi. 4.18 0) ‘wtich itis clear tht the output pulse eee fat a equency of ne bal that of he input waveform. vane ot TUUUL pas aq PE pe gt LT Fig. 4.1410) Fig. 4.1406) (6) Seine as for intially Q 4.2.6 YK Flip-Flop se J mp-p iiretineent ofthe RS ip, IP fip-lop, the indeterminate state FT Mtoe hr dained, The inputs J and K behave 5 inputs $ and R to set and eset a on, mapecivey, When both inputs and K are equal 10 1, the fipslop, switches 10 —e0 se characte 0807, ig ostained fom Fi: 43 (0 i gered) sow 8 FS 4:3 (¢) ‘The input and cutput ‘waveforms relation & © 7 Gon LIL 8 asic DIGITAL BLECTE ) and the graphic svmbo eae soe ig, 4.18(e) Input and ost woul of tye state diagram of the D fip-top shown in Fig. 4.13 flipsop O. p-9 Det a 6! ag arson © Example 43. Design 2 duide-by = 2 Solution. If D fip-fop has ty ste signal appt 10 ook SP {e) Suppose initially Q=2 and a= “The fist clock pulse “The second clock pulse (=1) wil “The circuit wavetorms are sven suave as frequen of one bal IL Fig. 4.1410) {by Ssine a for inally Q = 0-296 a 4.2.6 JK Flip-Flop “The JK flip-flop is a refinement of in the RS fipsop is defines an op respectively. When both inputs J ‘will cause the eixcut "The necessary connection is s 0-0. in Fig, 4:14 (8) from whic it 5 Fig, =D=1 to switch to Q ‘cause the circuit to switch 9 Q ‘of the input waveform. in JK fips ‘The inputs J and K behave Uk by ~ 2 are wan D Jip-lops. ] output connected to its D input, the eivuit will devide Jnown in Fig. 4.1410), a Del Q=D dear thatthe output pulse and so on. 4.140) 1p, the indeterminate ste "S and R to set and reset | Tip-flop, suitehes ©INTRODUCTION To SEQUENTIAL CIRCUITS aa its complement state, that is, if it swit i compeme Q = 0, it switches to Q= 1, and vice-versa. This condition can Qe = Qn lod Qt +) = GH where Q, a1 =next state = QU + 1) Q,, = present'state = Q (1). Here, the indeterminate state in the RS flip-flop can be eliminated by using the feedback technique, A clocked JK flip-flop can be constructed with two cross-coupled NOR gates and two AND gates as shown in Fig. 4.15 (a). The logic diagram of it is shown in Fig. 4.15 (b). Fig. 4.15 (¢) shows the logié’ symbol for clocked JK flip-flop and its truth table is shown in Fig. 4.15 (a), Q Q a 4.15(a) Clocked JK flip-flop. Fig. 4.15(b) Logic diagram. Qt s [Tk Toren a o}oji 0 JT KI Quai ofifo} 4 opol 9, ofifa} 4 afi! 0 yf) | ae rfal oa ifo}i} o rlo| @ rt etfslo) ae rfifi}o Fig. 4.15(d) Characteristic tableftruth table of JK flip-top. oo ol i 30 qo] okita Derk Qt +) = dQ + QK Qt +1) =J0 + OR 4 Fig. 4.15(e) Characteristic equationINTRODUCTION To SEQUENTIAL CIRCUITS = its complement state, that is, if Q = 0, it suitches to Q= ie farditer cas. is, if Q = 0, it switches to Q= 1, end vice-versa, This condition can Q.1=d, Qh H=Q Q, . 1 =next sate = QU + D Q, = present‘state = Q Here, the indeterminate state in the RS flip-flop can be eliminated by using the feedback technique where ‘A clocked JK flip-flop can be constructed with two cross-coupled NOR gates and two AND gates as shown in Fig. 4.15 (a). The logic diagram of itis shown in Fig. 4.15 (6). Fig. 4.15 () shows the logic’ symbol for clocked JK flip-lop and its truth table is shown in Fig. 4.15 (d), | a 3 co-— 8 a | = Fig. 4.15(a) Clocked JK flipop. Fig. 4.1518) Logie diogrom q]s [Koren d;opoy 0 ofoli} o ST KT Ga ofifo} 2 apoyo ofija] 1 f=fofal o rfojo] 2 ral a afo}i} o tho o rfafo} a rfifa] o Fig. 4.15(c) Logic symbol. Fig, 4.15(d) Characters tabietruth table of JK pop Xo oa u_1 Jofokitay Qt = 1+ K Qit+1)=04+ OK Fig. 4.15(e) Characteristic equation,"A BASIC DIGITAL ELECt« a0 «The output Q is ANDed with K and CP inputs 50 that the fipflep is cleared ing del pls only was previous a gpaery the cut Gf ANDed wi J eed CP inputs 5 a dock pulse only when @ wos previously 1 : When both J and K are 1, the input pulse is transmitted through one AND get on the one wioxe input is connecad tothe fipsop, Output hat is previously equal. to 1 Operation 1 As Tong asthe CP inputs at LOW lev Oe data inputs have no effect on the Cops, Fence, the ouput holds the previous data, Ths sale © called “no change state 2, When CP is HIGH level (a) If data inputs J = K = 0. The fp remains in no change oF hold” state, in which data jpputs have n0 efect on the outputs Le, Q(t + 1) = @ rey When the data inputs J = 0 and K = 1. The output Q is in reset or lees 0. nce mati. the ouput Q is ANDed with K and CP inputs so that the fipvop is cleared daring clock pulse only # Q was previously 1 {@) When J = 1 and K = 0, The output Q is setto 1 and G = 0. | Jo that the Mip-flop is set wi, {@) When 3 = K = 1. In this condition, the repeated clock pulses cause the output fs tumoffenoffon... and 50 on, This condition is known as “toggling” operation. a Wien @ 21, The ouput of input AND gee 1 and Jingu 9 me at AND gate is 0. Ths | Wee Ge 0. The ouput of Kinput AND gle ane J input AND Q= land Q 2 nine a | ‘Thus, when J = K = 1 in either case, the output sate (next tate] Q(¢ +1) = J. | Note» (1) The JK fipop has he fests ofall other fip-ops, hence Ms ako ced as “ i nes called as “universal” 12) produces an ouput for each and every input combinaton, Le, there is no-ndterminate st “The JK fip-lop can be constructed using NAND gates as shown in Fig. 4.16. ae Ke—S a oP i i Q Fig. 4.16 JK fipflop using NAND gates ony The relation between input and output waveforms for clockes i 3 ae pt and output waveforms for clocked JK fipslop is shown it 7BASIC DIGITAL ELects, 42 @ is ANDed with K and CP inpuls = that the fip‘lop is cleared dun, dock pube only iQ was previous 1 - vecay the ouput Q is ANDed wth J and CP inputs so tha a dock pulse only when Q was previously 2 semen bath J and K are 1, the input pulse is Wwansmited through one AND gate oni, she thee input connected tothe fipflop. Output that is previously equal to 1 Operation : 1. Along asthe CP inputs at LOW leva, the date inputs have no effect on the cuputs, Hence, the ouput holds the previous data, This sate ‘called “no change state” {b) When the data inputs 3 = 0 and K = 1. The output Q is in reset or cleared to | 0. In other words, the output Q is ANDed with K and CP inputs so that the flip-flop is cleared Q=1and Q = 0. a ue) |i Note « 1) The JK fip-lop has the feturs of all ther Mipsops, hence it is aso called as “ Z Fito. (2) produces an ouput foreach and every input combinaon, Le, there i no-ndeerm + The output the flip-flop is set wit flip remains in ‘no change or hold” state, in which ‘The JK fipflop ean be constructed using NAND gates as shown in Fig. 4.16. we Fig. 4.16 JK slip-Nop using NANC gates ony “The relation between input and output waveforms for clock ipslop Is 3 AS sput and output shed JK flip-flop is shown inNote @ and b are togale condition output, Fig. 4.17(0) input and out Put waveforms of clockee JK fp Nop. ‘The state diagram of the JK fipsop is shown in Fig. 4.17 ') Jat edCY “ODE, = Fig. 4.17(b) State dlagram of JK fipsfop 4.2.7 T Flip-Flop et ee sieerne ee G Itis a modification of JK fip-lop. The Tfip-dop is to) Inde fom aK Bier mca yea ee Dye and K terminals together. This means that at all ines = K The clocked T flip-flop is shou in Fig. 418, CP ox 1. When CP = 0. The outputs of both AND Ly Sys ses are O inespective ofthe value of The ouput LS) — ii ofthe circuit is same as the previous output, Therefore (ae Oe aoe Fig, 4.18 Clocked T tip-top 2. When CP = 1. (a) If T = 0. Both AND gates are disatled and hence The is no change in output, be, Q(t +) = Qi) (0) If T = 1. (Le, J = K = 1) The outputs of both AND gates depend on the previous output and finaly the output toggles, ie, Q + 1) = G (The lege msl chante ble and character enon wre oun the Fi, 419. Pecend SIC, pet SH tT Q TQ mr ° =[oy a, p 1 Ea | LI Quek Fig, 4.19(e) Losie symbol Fig, 4.19(b) Truth ttle The state diagram of T fipop is shown in Fig. 4.19(¢) 0 1 CERO) Fig. 4.19(¢) Stote diagram of Tfip-Nop. aNote @ and b are toggle condition ouput Fla, 4.17(@) input and output waveforms of docked JK tip-top. ‘The state diagram of the JK fipslop is shown in Fig. 4.17 (). Fig, 4.1718) State agra of J ti fop 4.2.7 T Flip-Flop The T flip-flop is also known as “toggle fip-op’ Sal and K terminals together This meas that stall umes QC J = K The clocked T flip-flop is shown in Fig. 4.18, CP4 oe Epona torn eee Ser Qt+y Q tt. pele sea Fig, 4.18, Clocked T fip-fop 0. Both AND gates are Sisabed and hence these is no Qu 2B) ET = 1. (he, J = K = 1) The outputs of both AND gates depend on the previous © output and finally the output toggles, ie, Q(t + 1) = @ (). The logic symbol, characters | Sid chorea epnton sho be Pa 423. . _pecient SHC. pel SI : irl Q[t] a : T Q Gets mpeg [ : a ofi] 1 |=fora oe B= fafo} a ite ifi] o [an Fig. 4.19(6) Logie symbol. Fig, 4.19(6) Toth table The state diagram of T fipop is shown in Fig. 4.19%¢) CEO) Fig. 4.19(c) State diagram of T lipfop——— = * \ BASIC Dict ae AL tay \ 4.3 TRIGGERING OF FLIP-FLOPS table devices, in which the output changes the stae put called the ‘clock (CP]’. The changes in the outpure, ‘Thus, in a synchronous fip-flop, for change of ste, ecessary, Basically there are two types of triggered 3, Flplops are synchronous bis «a speaed point on a triggering im in synchronisation with the clock extemal synchronising clock pulse is flops, they are (a) Badge-tiggered fiplops (b) Level tiggered flipflops. 4.3.1 Edge-Triggered Flip-Flops “The term ‘edge-tiggering’ means that the fip-lop is changing the state during the positve edge (rising edge) or at-the negative edge (Falling edge) of the clock pulse. This indicates that the output is sensitive to its inputs oniy at the transition of the clock pulse. Fig. 4.20 shows the postive and negative edges of a clock pulse. The upward arrow at the rising edge and down ‘ward arrow at the falling edge indicate the positive and negative edge triggering respectively | {Positive pulse (6) Negative pulse Fig. 4.20 | 3 Ql ar) sl | co —t ow — q a) Kee. i (c) Positive edge tugged flip-lop _(b) Negative edge tugged flip-flop Fig. 4.21 Ege triggered Mip-ops eg tiggeed fip lop ambols are shown in Fig, 421°) and out pube input is recognized in the diogram from the aerow Fa ere ise symba of imac indator and denotes tht the plop ane re she edge trnston ofthe dock (Fig. 4.21 (a). The presence ofa smal eee Cee an i dynam ndcator designates 2 negalve-edge ransin for tigering ca i ta bal CP is asd forthe dock input when the Bp op responds f pulze transition. ‘There are 2 ways to make the flip-flop respond only to @ negative edges). They are The positive and negative Fig. 4.21 (b) respectively. The al pulee transition (posiive orBASIC DIGITAL ELECTRON a FLOPS 2 Oe : devices, in vihich the output changes the state only a at caled "he ‘clock (CP). The changes in the output occur Thus, in a synchronous flip-flop, for change of state, an sccary, Basically there are two types of triggered flip. Fipslops are synchronous bi int on a triggering i Siheston wih he cock ‘extermal synchronising clock pulse is necessary flops, they are (a) Edgestiggered flipflops (b) Level triggered flip-flops. 4.3.1 Edge-Triggered Flip-Flops ‘The term ‘edge-tiggering’ means that the fliplop is changing the state during the positive ce (rising edge) or atthe negative edge (falling edge) of the clock pulse. This indicates that the output is sensitive to its inputs only at the transition of the clock pulse. Fig. 4.20 shows the postive and negative edges of a clock pulse. The upward arrow at the rising edge and down werd arrow at the fling edge indicate the positive and negative edge triggering respectively, etl eee 7 — a Es a es Pe i (a) Positive pulse (b) Negative pulse Fig. 4.20 | f a o— ces 4 i «8 K 3 ll 2 a (9 Pose eos aod op) Nese ee ped py Fig. 4.21 Edge triggered flip-flops ° i be i a i 2 i f i i There are 2 way a 8 to make the fy one eda) They ang "MME the fe respond only to a pulse LL transition (positive orBASIC DIGITAL BLECTROW on 4.3 TRIGGERING OF FLIP-FLOPS Jyronous bistable devices, in which the output changes the state only a 7 a specifed point on a triggering input called the ‘lock (CP) The changes in the output occu in synchronisation with the clock. Thus, in a synchronous flip-flop, for change of state, an wr amet cgnchronising dock pulse is necessary, Basically there are {wo types of triggered flip Mos, they ace ; (a) Edge-iggered fipslops (b) Level tigger fip-ops 4.3.1 Edge-Triggered Flip-Flops “The term ‘edge-trggering’ means that the fi means that the fipsfop is changing the state during cage arg dp or che sepove eg elie ge) othe soc poe Ths dearer het the output is sensitive to its inputs only a the transition of th rarer 3¢ dock pulse, Fig. 4.20 shows the Positive and negative edges of a clock pulse. The upward arrow at the rising edge and down ” ward arrow at the falling e iegative edge triggering respectivel the foling edge indicate the postive and negative edge triggering respectively ively. Fip-lops are synch Negative ga Positive edge (8) Negative pulse Fig. 4.20 (a) Positive edge tu stage firop_ 8) Noanive edge tugged re Fig. 4.21 Edge triggered ‘flip-flops, Tee eae : a Pa nd mean ee gee htc etch The dock ae at waco rh Fs. 421 ae real Ti a sel ofa hmamic hens yt 2 fom the aero tor’ and denotes the ory wd dents th a "he preser ‘et “pe mest states cae ge transition for triggering ive-eda tere tec 3 shown in Fig. The RC values are seh io ; sich ht th eet hos 9 he te aa a too es Ase ie ene an Ce ‘edge emerges in a negative spike. Because of ~ IT: .” a” J [AND gates, the circuit does not respond to the ¢ ore CK negative edges and it responds only to positive Fig. 4.21 Positive edge triggered edges and hence itis a positive edge triggered Tip-lop ciceuit. (b) Pulse transition detector. The purpose ofthis crcl is $0 produce a very shot duran caine on the postive going transon of the dock pulse. In Fig. 423, there is 2 smal qetsy gn one input ef NAND gate, s0 thatthe Inverted clock pulse aries at the oe SFE! delay on one i the tue doch ple. This produces an ouput spike with a duration teiy atew nanoseconds. To obtain the negative gong trasion of the ows Em, He Nave or ce overt the clock pulse (or) remove the inverter atthe output of NAND gate aes a, Es we a axe pp Fig, 4.23 Logic cucuit ofa pubs traniion detector “thus the edge tagering cn be given tothe fipslep and depending on he sl! He FC} gps’ the operation of the fipllop can be determined, i. 4.24 shows {he nel ‘and output reeetorms for positive and negative edge triagered JK fip-op etL LU SLA cK E a. 4.24 lput and outpt wavetors for postive and negate ge tisnered 2K MrlePINTRODUCTION To SEQUENTIAL CIRCUITS (0) Use of capacitive coupling (b) Pulse transition detector. : (a) Capacitiv fe coupling. In this coni- guration, an RC (Regitor capactor) cut inserted in the dock input of the fp-op, a8 shown in Fig. 4.22. The RC val. = 4 e values are selected Ke— Se ets eee eas thus converting rectangular clock pulses into. CPe—9}—4 CLK Se ee Seer | 1 ge emerges in a nemave spe, Because of [AND getes, the euit doer nt respond to the negative edges and it responds only to postive Fig. 4.22 Positive edge trigsered fedges and hence it is a positive edge biggered flip-top. rcuit {b) Pulse transition detector. The purpose of this citcull i to Eromuce SS short arate) caine on the postive-ging varson ofthe dock pub, In Fi. 42, fs small aay on one inpat of NAND gate, so thatthe invested clock pus Ss =) the gate input & ay on eae ater the tue ck ple. This produces an ouput sp 0) ‘duration of te atte nanoseconde. To obtain the negaive going taniion oN clock pulse, we have ony eve the lock pulse (or) remove the vere at the output of NAND gate thus the edge triggering can be given tothe fipflop and depending one Slt of the. inputs the operation ofthe fipiop can be determines: a "4.24 shows the input and output inp efor positive and negative edge triggered JK fip-foP eft y i ae i Q (Negative edge) rg. 4.24 input and ontil wavefoms for posive and negnve edoe Were IK fips.ITAL BLECTRONICS pasic DIG! 46 wn as ‘level siagerng ee fip- ‘of the flip-flop ct anges the stat gate ive levels are shown “postive 4.3.2 Level Tri ‘The postive and net flop responds to LOW or is postive in Fig. 425 I the fio Shera te dk 5 level op" and i the fip-slop changes rn ‘el gad BES ped nie ase! PCP Negative | Texel Fig, 4.25 -the main douback of vel tiggrng i that as tong as the cock peas, negative, the fey changes is sate more tan ence of mary ies (% the change in inputs. Ifthe | wn ete made sable forthe ente cock duration, then te Pe changes only once. On inpuis or, the frequency of input change is higher than fhe Pet clock frequency, the thee fe ip-fop undergoes mulpe changes, when the clocks PORN OF negative. When aon era anaserted, the utpt of the fip-fop remairs in the last nie [Note : The level triggering can not be wed for T and JK fi flops 4.3.3 Race Around Condition iis teportant to note that n JK Tipp, the output is fedbeck tothe input nd eselore | ena BSS resus change inthe Input, the inputs |= K = 1 end Q = Sthon » eleck puise with a with‘ 0s shown in Fig. 426 (0) is applied, the output will change from 0 to 1 after the time interval At i Where ‘At = propogation delay of two level NAND gates | t, = pulse with, om afer we have J ='K = Land Q = 1 andar anather 8, ouput Q wil become | 0. Hoses the cup wil oxclete back and forth between 0 and 1 in the duration tp of the \ Glock pe wid. So, at the end ofthe clock pulse, the value of Q is ambiguous. This Situation is known as 2 “race-arround condition” | "The race around condition can be avoided when f, < At as shown in Fig. 4.26 (b). This condition can be obtained by two ways p ae (1) fy is reduced (2) I At is increased. Felucion of 1, means, we have fo use 8 ule generator fo produce les pulse waveform, but it is difficult to get such type of circuit f se “Te anlue of A ean be Inceased by sing the lumpa delay nes in sre feedback connection, which is worthless. 4 i x adasic DIGITAL ELECTRONICS ‘le * a voce Triggered FPTHIOP um as eel ageing TREN Ae tp or HIGH level of the seme otput of te Tipsy ner suns el ial end negative Levels are shown Tevet according to the input values “The positive level end nes: vt es “positive so Peck spo, is ee ine A ean hen the dock on the cock negave (he “tea hinged lipfor seed if the Spon changes its state On ‘when clock = LOW), itis terme Se ecvpegave level tiggered fip-oP Necatve ,| Positive cca level Fig. 4.25, ‘The main drawback of level triggering that as fong as the dock positive or negative, the AeAcy change ts ste more than once ot many fmes (Whe tchange in inputs. If the spe Jeoare mide able forthe ene clock duration, then the PA! changes only once. On InP oe the Requency of input change is higher than the IAP clock frequency, the tn ote the Npsflop undergoes mlple changes, when the dock Postar negative. When ca ee unexserted, the output of the fip-op remas in the let state "Note : The level triggering can not be wed fr T and JK fp-ops 4.3.5 Race Around Condition >< eae tt te ote hatin IK fip-fop, he ono i fac to the ip nd! therefore a Rea rele change the np the aps J = K = Land Q = 0 ane ue with a wh ‘yas shoun in Fig. 426 (} & applied, the out will change fom 01 | afer the tine intel Where ihr = propagation daly of two level NAND gates 1, = pube with Now ater ve have J ='K = Land Q = 1 and afer aroter at, output Q wl become 0 ate a i aclte ack and forth beween O end 1 inthe duration t, of the tlowk puke wid. So, atthe end of the clock pulse, the value of Qis ambiguous. This Situation feinoun as a “ecearound condition’ re ne around condition ean be avoided when f, < At as shown in Fig. 4.26 (b). This condiion can be chained by two vay °, cern (0) I is reduced (2) Ais incenced Reduction off, means, we have fo use a pube generar fo produce Jes Be etabonaiath one facil ES re “The ale of can be increased by wing the humped delay lines In sr feedback connection, which is worthless. pene gel aad toga on the negative clock edge. (a) IF J = K = 0, this input cordon does not produce ary change. Thus mastersave fiplop operates from a complete clock pulse, and the outputs change on the negative transition, Table 4.4 shows the input and output waveforms of MSJK flip-flop. Table 4.4 Truth table for master-slave JK flip-flop a ai 7 K ¥ Qnet 0 ° ° ° 7 o °and T inputs called “control inputs”, ae flop changes its state in ust be used synchronization slong with a clock to ti th addition to the above synchroners inpats, most of the cond flipflops have one or or fleet onthe fip-lop OP ‘dependent ofthe synchronous To Sed to st the fip op 10 the 1 state, oF ‘at the other inputs. more ra dock input. Agncheoncus ME ean dear the wpe Ostate at any time, resardless cof the condition puts”, These inputs are -canected directly into the latch its and the clock. ‘Frese inputs are also caled as “nec ; rae ak any fipop #9 that wey vere De ‘effect of synchrone Fig. 4.29 shows @ clocked J K fipflon sets direct eet inputs. These ae active LOM et ep Tan ctve LOW level on the cen {AP will SET ae octvated by 0.0 lee 28 inated be ‘mall bubble on the flip levee be kept HIGH for synchronous operation ig. 4.29 Logie symbol fr JK pop wth active LOW preset and lar input ot input | ‘Table 4.5 shows how these inputs operate, Note + LOW lees on pst end clear should not be appted simul | ambiguous consiton. Juaneously, since it lends to an | Table 4.5. Truth table Tapas Guipais | Paton ForbiddenAL CIRCUITS The logic di as" iagram for an e fijs shown in Fig, 430 sige tiggered JK fip-lop with pres PR and dear CLR st PA and clear CER inputs mR a aR fig. 4.80 Logic diagram fr base TP ap wits neve LOW pret and car nh From Fig, 430, it dear that «ig applied to the BR (reset MPA Aip-op “jarpat YO) wl become 1 Temes fa oe lth er cpt STAR 8 logic LOW (0) Sat the CLR (clea) input holds the Q output cof the flipsiap 7 the HIGH state, ie, Q = at te Synchronous mpuss ce" PE sad to hold the fip-op 19 & tier state for any desired interval of time: some fipslons nave SSITEh puts that ore ected BY ICS 1 (active HIGH) apa on he preset an 3A neat is nt shown for ese Aip-ops Input and output 4 tusks the operation of Pes and cleat ig. 431. Sarge ae es toadsASIC DIGITAL ELECTRON 450 pirect INPUTS e paar ait een sedate Pe giplop changes its state in Pol inputs rust be used 4.4. ASYNCHRONOUS OR For the fip-fiops discussed 0 fF oe enone Fe pus, i Seronation wath the cock TPA sal. $e, the synchronous are a dock to ter @ change the fipflop. 3 anon to the above snetencus nus of “st Oe on elon eer cient fe sono rete ane dock input. Asyncons Imps op ond to et the fpsfon to the 1 Se reer the fipiop to the O-tate at any fines mn res of tke condion at the Oe inputs ee an cad aa “recip. Tare es sconected directly into the latch Featen of any Ripstop so that they ovede the aes anchronous inputs end the clock 1 PRESET (P2) and CLEAR (CLR) or “direct roms, An active LOW level at the preset the docked fip-ops have one ot Fig, 429 shous a clocked J K fip-lop wit et! Ui "divet reset” inputs. These are active LO} sa ful SET the fipslop, and an active LOW level the clear input will RESET it, These srPchronous inpuls are acivated by 2.0 level m8 interval of time. ome flops have asynchronous nas We 2 Oy The small bubble on the preset and rather than by logic 08 afip-oPs Input and In this Fig rated by logic 1 (active HIGH) ar input i not sh {he operation of preset and deat 1 ihustate fpfop's outpat toes own in Fig. 43 tt logic 1 Ths i output waveforms sh fe sssumed ral, J and K inputs Apt ian te Preset Cer iogle 4 Sal and Gear inputs , een he Bop on ee ta 4.81 Operation of pe Asyrropuct s ION TO SEQUENTIAL CIRCUITS 231 The logic di ie diagram for an et je shown in Pig. 4.20 rige triggered JK fipslop wi e jop with preset PR and clear CLR inputs 1 pop with active LOW prea nnd ea INP «applied to the PE. (preset) iu, the Bete Sem, 3 tie LO HIGH sate, 'e, Q =O. ate for any desied Fig. 4.30 Logie diagram for 9 basic 2 om Fig, 4.30, it is lear that i 9 loc 0 * But (0) val become 1 regrces ofthe sais of 8 ther inputs. fat the CLR (deer) input holds of the fips in the seus, asynchronous inputs €3P fe fipfiop in a particular © interval of time. Some flipflops havs Wy logic O's. The smal bub the @ output ‘be used to hold the togie 1 (active HIGH) ed by for these that ore actval wt isnt shown re asynchronous inputs ft and deat in je on the pres of preset and deat the operation ops output to3sles «shown in Fig. 431 illustrate “Thus Bip vps are assumed at lo 2 eel te Preset nO Fai as Set 1 and preset = 0 nd 4, clear = 0 ‘togsle operation put. oping the fipsop ping a ‘and pres occur because‘BASIC DIGITAL E 332 5 FLIP-FLOP CONVERSIONS : i é oC eile to implement one fiP-TOF cireait using any other fle- with ome a the one nection for such reaialon © ‘shown in Fig. 432 ‘The general block diagr gates. fg, 4.32 Block dagam t0 wate fips Sn flip-flop v. o ealise a fip-op (X) wing an other fig fop () I tip-fop (¥) along with a combination} eouk aed "NEXT STATE DECODER used, Wh fnctions like a flip-flop (X)- For this cre galzed, for each set of inputs of fipflop ON) he and B and present state (Q,) we T cause the flip-flop (Y) to make 1 ott the npus to the fipsop(Y) .e C 2 De that will rave ato the proper next ate (2, 1) ofthe fife {X), These inputs to the flip-flop () tanstion men state code”. The design procedure fOr eich realisation can be summarised in the following steps (1) Obtain the clear stat {2} Obtain a present state-ne? {G) Using the excitation table (or) application tabs eg fate code or the excitation input values t0 (a) Using Kemaps, simply the lonle expressions for excitation inputs of flip-flop (Y) and design the next state decoder Logie {5) Draw a circuit forthe deste ip-lop (X) using nes Sie decoder logic and the chosen fipflop {Y) as shown in the Fig 432 few conversions among flip-flops. tement description of the desired fip‘op (X). vt sate (PS-NS) table for the desired fipflop (X) ‘of the chosen flipflop (¥), append the above present state-next-state table. Let us see 4.5.1 Realisation of Delay (D) Flip-Flop using SR Flop “Conair the reatzaion of Dfip-top using SR fipflop, Here the desires flop (K) is aa ee hen pon) SF lp. The bse Bock Slogem 8 shown in Fig. 4.33. Next See Q D state decoder a 3 Fig, 4:33 Block diagram of D fip-lop using S-R f-fop, ‘Step 1. The precent state and net state table for D fiplop is shown in Table 46.INTRODUCTION TO si NTO SEQUENTIAL CIRCUITS 493 Tabl le 4.6. PS.NS table for D-lip-f flop in Table 4.7 Step 2. The excitation table of RS fip-lop is given i Table 4.7 Cpvoder, the simplified expressions con PP obtained by Step 3. To ‘shown in Fig. 434 sing K-maps from Fors ForR po 4 po i 7 & ae] ALS ie ACK =D pg, 4.94 Heap or Sand step 4. The ose dag ee such 8 wo ee TD end =D. He OMe ne dena in Fg 435: ‘ po i 4.5.2 Realisation of KF ore, the desced fips Hr elk diagasic DIGITAL ELECTR, ast \ " ug, 4.36 ck dagen of K mpfr SS ss sip op rt {IK fipflop is shown in Table 48 (0) E Step 2. The excitation table for IK fipflop using SR flip-top is shown in Table 4.8 (b). ‘ Table 4.8(a) Truth table Table 4.8 (b) i Step 3. The simplifed expressions for S and R are shown in Fig. 4.37 (K-maps). “a maps) For R Fig. 4.37, 7 Step 4. Realization of JK fip-fop using Fig. 438 7 1p using SR flip-flop is show nincircurts Here, the desired fip- 7 ited flip-flop (X) is T flip-flop and the cf block diagram of T flip-flop using SR flipslop is shown “Flop using SR Flip-Flop in Fig, 4.39) Ce T— state Table 4.9(a) Table 4.9(a) Truth table decoder |_| p' Fig. 4.89 Block diagram of T flip-op using SR tip-top Step 1. The present state-next state table for T flipflop (truth table) is stown in Step 2. The SR values for the above truth table are shown in Table 49 (b) Table 4.9(b) Excitation table oser fip‘lop is (Y) SRip-Nop. The Step 4. The realizt Fig. 4.40 Kmaps | 7 Excitation inp @ [DT Gn [2 Q,,, FExctaton np oy Oo] ° tee ofifa ou (omeen oan. 1|o}t ale | i{ileo} a oe ae |e step 3. Te simplified oxpus Le, itt Spf) fom the netstat decoder can bbe derived using K-maps, as shown in Fi Fors e t aye al x tion of T fipslop using SR flip-fop is shown in Fig. 4.41 Fig. 4.41 T fiptlop using’ SR flip-top——— 456 BASIC DIGITAL BLecr p-Flop using D Flip-Flop “K fip-flop and the chosen fipslop (¥) #6 @ Pipa 4.42. 4.5.4 Realization of JK Fl a the deste. Spon (X) i 2 Here the dese gallon i shown in Fig ‘The block diagram of this realisation a Fig. 4.42 Block diagram of JK flp-op using D flips . Step 1. Th present satenent sate (ruth table fr JK fipslop is shown in Table 4.104) Step 2. The D input values forthe Table 4.10() are augmented in Table 4 10(b) able 4.10(a) JK flip-flop truth table Table 4.10(b) Excitation table @[F K] Qn @ |e K] [caer 0 [fo oy 0 T Too] OT 0 0 }o 1) 0 ajoijo]} o 0 |i 0) 1 o}iofi] 1 ofr alt ofaaf a]. 2 1 {o of 3 rfoofi] i 1 Jo 1} 0 ijoifo]} o 1 {2 0} t af fiat ijirlo fe |e! on| ano Step 3. The simplified output (D) from the nex! state decoder can be obtained by using Kemap a3 shown in Fig. 4.43. aK e ou 00 of of o fa | 1) 1 1] Df o | o {a | D=Qu+K Fig. 4.43 Knap, ‘Step 4. The logic diagram for realization of JK fip-lep using D flip-flop is shown in Fig. 4.44.487 Nextt state! decoder Fig. 4.44 JK flip.top using D fip-lop 4.6 FLIP-FLOP EXCITATION TABLES ed = table Gyan fe two columns Q, and Q,,;, and a colurm for each input to show how the ‘D.and T flip-flops. tettes fF. 4.6.1 RS Flip-Flop Table 4.11(b) RS excitation table R | S| Qu (@JeaTe Ts Olas ofo}x}o aa Od Fete a04 | A lee rfofifo tL nina ififols fa) 0 -» 0 Teansition : The present sate ofthe Mi-flop 6 0 and isto remain in, nee ear Ting atthe ta ble fips, we ean undentand when a clock Pulte har when R= 0 and § = 0 {no change condition) or when R= 1 and s=0 wo, Shas to be at 0, but R can be at ihe evel (The table inne his with @ jer S and an *X' under i 6 and i to change to 1. This can heppen ‘Transition : The present state Is crane tet condition). Therefore, & has 0 be 1 and R has fo be 0 for this (Ot when § = 1 an * transition to occur {) 1 > 0 Transitios only when S = 0 and R for this transition to occur (q) 1 > 1 Transition “This can happen is Land isto change fo 80 1 ee 2 has to be 1 Js: The potent state Rene oo ). Therefore § has to be O and R ‘= 1. (Reset condition «The present sat is 1 and is remain 1. This can happen ete ee———eS— eee BASIC DIGITAL ELECTRONIC 358 5 = 0 and R = 0, (no change condition) ie oe oe 2 table, this was indicated with a ‘X’ undey: pie So be at either level. In the “Thus B has to be 0, but S can S and ‘0! under R. 4.6.2 JK Flip-Flop ‘The truth table and excitation table respectively, Let us examine each case. Table 4.12(a) Truth table for JK fip-fop are shoun in Table 4.12 (a) and 4.12 (b) Table 4.12(b) Excitation table TA] Ga @ [aa] J 1K apo Qa o}o fo |x of.) o ofi fa] x 1}o) 4 r}fo]x]a ajo} a eet. ee (c) 0 + 0 Transition : When both present tate and next state are 0, the J input must be O and the Kinput can be either 0 or 1, which is represented by X in the table. (b) 0 + 1 Transition : Here the present state is 0 and isto change to 1. This can happen when J = 1 and K = 0 (se) (or) when J = 1 and K = 1 (Toggle condition). Thus J has to be 1, but K can be either 0 oF 1. (o) 1 — 0 Transition : The present state is 1 and is to change to a 0, This can happen when J = Oand K= 1 (or) when J = K = 1. Thus K has to be 1 and J may be either ‘0° orl (d) 1 -> 1 Transition : When both present stale and rext state are 1, the K Input must be O and J input can be O or 1 Note : From the exsation abe of the JK Mp-op, we ean see that it has more don't care terms. Usually more dott care ters simply the functon. 4.6.5 D Flip-Flop “ales 4.13 (0) and (2) show the tut abe and excitation abe fr D fipfop respective by Doe, nn at hyena he Dn tinder be prs fe Terefoe D mst be 0 Gy has to be 0, an 7 cal sa eee vt es © be 0, and 1 f Q,,, has fo be I, tegarles of Table 4.13(0) Truth table Table 4.13(b) Excitation table anINTRODUCTION To SEQUENTIAL crculTs =e 4.6.4. T Flip-Flop a The Tables 4.14 (a) and (bj (a) For 0 -» 0 and 1 (b) For 0+ 1 and 1 show the th tbe and excaton * 1 transitions T = 9 and oe : > 0 transitions T must be 1 Table 4.14(a) Truth table Table 4.14(b) Excitation table 4.7 APPLICATIONS. OF FLIP-FLOPS Fiipfops find wide applications in counter circus, frequency dividers, shit registers. A wide variety of serial decoding, comparison and tinmng funchons cam be using flip-flops. Using flipflops, we can generate a variety of one chee ‘An operation that occurs very frequently in digital system is transfer of J.0n¢ fiplop or a group of fipslops to another fipslop or enother group and storage complished information from Of ip ops, 4.8 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS “ne cing behaviour of a sequential circuit can be determined fom the inputs, the outputs and the states of is fipslop. The outputs and next state are both a functon ois inpuia eal oe Bresent state, The analysis of a sequential circuit consists of obaining a table or degre ec ne lime sequence of inputs, outputs and intemal states. The succes of anabuis o deagn ot Sequential circuit depends on the aids and systematic technicues such ax sate ible eae diagrams and state equations used in these processes, 4.8.1. State Table Fig. 4.45 shows a clocked sequential circuit It has one input variable X, output variable (a and two clocked JK flipflops. The fpops are labeled as A and B, and their outputs we Inbelled as A and A, and B and B, respectively, The output Y can be determined by Benlane expression which is derived using three input AND gate. Fg. 4.45 An example of sequential crc— BASIC DIGITAL ELECTRONIC, 60 we start analysing the circuit 1 circuit. It represents the relationshig sent state, next state a sine Hera eco Pe ie “ent tt” tas teste of he Bop blr cca’ dock |i no a tt iy ten of a Eso sand up cons igo co opezentng 0 posse np Table 4.15 : Present state] Next state AB [AB AB | x i 1 00 oo | 10 or a1 | 00 | 10 11 | 10 } uu a | We can derive the state table as follows Step 1, Find the next state for all possible present states and input states, (a) If present state AB = 00. (i) IE Input X = 0 : When present state is 00, ie, A = O and B = O and X input = 0, ‘outputs of all AND gates are logic 0. Therefore, J and K inputs for both fi ‘are 0, giving the next state same as present stale, (OM Input X = 1 : When present state is 00, Le, A =O and B= OandX=1, | ‘AND gates 1 and 4 produce a logic 1 si \ i égnal at the J input and Kg input. Therefore, in the next staie A is set and B is cleared, 12, AB 1g | (b) If present state AB = 01, flops (0 If tnput X = 0 : When present state is 01, ic, A = 0 and B = the output of AND gate 2 is logic 1, making sate, A = 0 and B = unchanged ie, B= 1 ‘ i i (i) Minput X = 1 : With present state AB = O1 and X = 1, the output of AND gate 4 len 1 ming hy inp ih. Therelore, the nent sate of Anan y and B = 1. a | (4) If present state AB = 10, M input X = 0 : When present sate AB = 10,te, A = 1 i : ent date AB = 10,16, A = 1 and B = Oand X = 0, the output of AND gate 3 is loge 1 heel the next state, A remains