DS MC97F2x64 Eng

MC97F2664
ABOV SEMICONDUCTOR Co., Ltd.

8-BIT MICROCONTROLLERS
MC97F2664
Data Sheet (Ver. 1.12)
January 15, 2020 Ver. 1.13 1

MC97F2664
REVISION HISTORY
VERSION 0.0 (June 22, 2012)
VERSION 1.0 (July 24, 2012)
Change ‘±6LSB’ to “ILE” in A/D CONVERTER characteristics.
Change ‘3.0V’ to “Vdd @ 0.4-16MHz” in RECOMMENDED OPERATING condition.
Change ‘4.5/9.0mA (Typ/Max)‟ to “IDD1 @16MHz Crystal” in DC electrical characteristics.
Change ‘4.0/8.0mA (Typ/Max)‟ to “IDD1 @16MHz IRC” in DC electrical characteristics.
Change ‘1.2/2.4mA (Typ/Max)‟ to “IDD2 @16MHz IRC” in DC electrical characteristics.
Change ‘1.60/1.79V (Typ/Max)‟ to “VLVR, VLVI” in LVR and LVI characteristics.
Change Figure 10.6 Effective Timing of Interrupt
Change Figure 14.1 Block Diagram of On-Chip Debug System
Change Figure 1.1 Connection of Transmission
Remove 42 PIN DIP package
Remove INTERRUPT GROUP PRIORITY LEVEL at INTERRUPT CONTROLLER
Remove Appendix B
Add 64 PIN LQFP-1414 package
Add RUNFLAG Pull-Down Resistor(RPD) in DC electrical characteristics.
VERSION 1.1 (October 4, 2012)
Modify Figure 7.17 Recommended Circuit and Layout
Add Figure 7.18 Recommended Circuit and Layout with SMPS Power
VERSION 1.2 (January 11, 2013)
Add 0.1uF Bypass capacitor in Internal RC Oscillator characteristics
Change ‘14/24mA, 10/18mA’ to LVR/LVI current in LVR/LVI electrical characteristics.
Change ‘±5LSB’ to “ZOE” in A/D CONVERTER characteristics
Change ‘±5LSB’ to “FSE” in A/D CONVERTER characteristics
Change ‘10,000/100,000 times‘ to Endurance of Write/Erase in internal flash rom characteristics.
VERSION 1.3 (March 18, 2014)
Add 64 PIN QFN package, MC97F2664UB
AVREF range changed from 1.8V~VDD to 2.7V~VDD
Figure 10.3 modified
Add contents, “Writing “1” has no effect” in all interrupt flag bits.
Appendix 1 “DJNZ Rn,rel” instruction 3bytes 2bytes
AVREF range changed from 2.7V~VDD to 1.8V~VDD
VERSION 1.5 (July 7, 2014)
Removed “PGM Plus USB” in Development Tools.
Modify note of LVRCR in RESET, ”The LVRST, LVRVS[3:0] bits are cleared by a power-on reset but are
retained by other reset signals”.
Change “Read Protection” to “Code Read Protection” in Configure Option.
Change “Hard-Lock” to “Code Write Protection” in Configure Option.
Change “Vector Area Protection” to “Vector Area Write Protection” in Configure Option.
Change “RESETB select” to “Select RESETB pin” in Configure Option.
Change “Protection Area” to “Specific Area Write Protection” in Configure Option.
Add note of “Specific Area Write Protection” in Configure Option, “When PAEN = ‘1’, it is applied.”
Fix the typo.
VERSION 1.6 (Sep 24, 2014)
Change MAX value of VDD rising time “30V/ms” to “8V/ms” in Power-on Reset Characteristics
Modify contents of BUZZER
Modify Figure 10.3 Interrupt Sequence Flow
Fix the typo.
2 January 15, 2020 Ver. 1.13

MC97F2664
VERSION 1.7 (April 13, 2015)

Change MAX value of VDD rising time “8V/ms” to “5V/ms” in Power-on Reset Characteristics
Change a Figure 11.53 A/D Analog Input pin with Capacitor in12-Bit A/D Converter.
Add contents of Flash, “Protection for Invalid Erase/Write”.
Add condition of VDD rising time in 7.4 Power-On Reset Characteristics.
Add Flash Data Retention Time in Chapter 7.14 Internal Flash Rom Characteristics
Modify the program tips in Chapter 15. Flash Memory.
Add an appendix about “Flash Protection for invalid Erase/Write”
Change symbol name from ILE, DLE, FSE, tCON, VAN, IAN to INL, DNL, TOE, tCONV, VAIN, IAIN in
7.3 A/D Converter Characteristics
VERSION 1.10 (February 1, 2017)
Added the note on the flash memory erase and write in Chapter 15. Flash Memory.
Updated OCD dongle image and writing tool images in Chapter 1.4 Development tools.
Fixed typos of USI Status Register in Chapter 11.11 USI0/1 (UART + SPI + I2C).
Updated Package diagrams in Chapter 4. Package Diagram.
VERSION 1.12 (December 14, 2017)
Added a Figure 1.1 Device Nomenclature.
Updated 64LQFP-1010 and 64LQFP-1414 package diagrams in Chapter 4. Package Diagram.
Updated 1.4.2 emulator and debugger.
Updated Figure 1.3 E-PGM+(Single writer).
Added a chpter 1.5 MTP programming.
Updated 7.22 Recommended Circuit and Layout with SMPS Power.
VERSION 1.13 (January 15, 2020) This book
Added a description of debounce function in Chapter 9. I/O Ports.
Added a note about the Capture mode in all Timer.
Version 1.13
Published by FAE Team
2020 ABOV Semiconductor Co.,Ltd. All rights reserved.
Additional information of this manual may be served by ABOV Semiconductor offices in Korea or Distributors.
ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, ABOV
Semiconductor is in no way responsible for any violations of patents or other rights of the third party
generated by the use of this manual.
January 15, 2020 Ver. 1.13 3

MC97F2664
Table of Contents
1. Overview ............................................................................................................................................................. 7
1.1 Description ................................................................................................................................................... 7
1.2 Features ....................................................................................................................................................... 8
1.3 Ordering Information .................................................................................................................................... 9
1.4 Development Tools .................................................................................................................................... 10
1.5 MTP programming ...................................................................................................................................... 13
2. Block Diagram ................................................................................................................................................... 15
3. Pin Assignment ................................................................................................................................................. 16
4. Package Diagram.............................................................................................................................................. 20
5. Pin Description .................................................................................................................................................. 24
6. Port Structures .................................................................................................................................................. 29
6.1 General Purpose I/O Port ........................................................................................................................... 29
6.2 External Interrupt I/O Port........................................................................................................................... 30
7. Electrical Characteristics ................................................................................................................................... 31
7.1 Absolute Maximum Ratings ........................................................................................................................ 31
7.2 Recommended Operating Conditions ........................................................................................................ 31
7.3 A/D Converter Characteristics .................................................................................................................... 32
7.4 Power-On Reset Characteristics ................................................................................................................ 33
7.5 Low Voltage Reset and Low Voltage Indicator Characteristics .................................................................. 33
7.6 Internal RC Oscillator Characteristics ......................................................................................................... 34
7.7 Internal Watch-Dog Timer RC Oscillator Characteristics ............................................................................ 34
7.8 DC Characteristics ..................................................................................................................................... 35
7.9 AC Characteristics ...................................................................................................................................... 37
7.10 SPI Characteristics ................................................................................................................................... 38
7.11 UART Characteristics ............................................................................................................................... 39
7.12 I2C Characteristics ................................................................................................................................... 40
7.13 Data Retention Voltage in Stop Mode ...................................................................................................... 41
7.14 Internal Flash Rom Characteristics .......................................................................................................... 42
7.15 Input/Output Capacitance ......................................................................................................................... 42
7.16 Main Clock Oscillator Characteristics ....................................................................................................... 43
7.17 Sub Clock Oscillator Characteristics ........................................................................................................ 44
7.18 Main Oscillation Stabilization Characteristics ........................................................................................... 45
7.19 Sub Oscillation Characteristics ................................................................................................................. 45
7.20 Operating Voltage Range ......................................................................................................................... 46
7.21 Recommended Circuit and Layout ........................................................................................................... 47
7.22 Recommended Circuit and Layout with SMPS Power .............................................................................. 47
7.23 Typical Characteristics ............................................................................................................................. 48
List of Figures
Figure 1.1 Device Nomenclature .............................................................................................................. 9
Figure 1.2 Debugger(OCD2) and Pin description ................................................................................... 10
Figure 1.3 E-PGM+(Single writer) ........................................................................................................... 11
Figure 1.4 E-GANG4 and E-GANG6 (for Mass Production) ................................................................... 12
Figure 1.5 PCB design guide for on board programming ........................................................................ 14
Figure 2.1 Block Diagram ....................................................................................................................... 15
Figure 3.1 MC97F2664L 64LQFP-1010 Pin Assignment ........................................................................ 16
Figure 3.2 MC97F2664L14 64LQFP-1414 Pin Assignment .................................................................... 17
4 January 15, 2020 Ver. 1.13
MC97F2664
Figure 3.3 MC97F2664UB 64QFN Pin Assignment ................................................................................ 18

Figure 3.4 MC97F2464 44MQFP-1010 Pin Assignment ......................................................................... 19
Figure 4.1 64-Pin LQFP-1010 Package .................................................................................................. 20
Figure 4.2 64-Pin LQFP-1414 Package .................................................................................................. 21
Figure 4.3 64-Pin QFN Package ............................................................................................................. 22
Figure 4.4 44-Pin MQFP-1010 Package ................................................................................................. 23
Figure 6.1 General Purpose I/O Port ...................................................................................................... 29
Figure 6.2 External Interrupt I/O Port ...................................................................................................... 30
Figure 7.1 Input Timing for RESETB ...................................................................................................... 37
Figure 7.2 Input Timing for External Interrupts ........................................................................................ 37
Figure 7.3 Input Timing for EC0 – EC9 ................................................................................................... 37
Figure 7.4 SPI Timing ............................................................................................................................. 38
Figure 7.5 Waveform for UART Timing Characteristics .......................................................................... 39
Figure 7.6 Timing Waveform for the UART Module ................................................................................ 39
Figure 7.7 I2C Timing ............................................................................................................................. 40
Figure 7.8 Stop Mode Release Timing when Initiated by an Interrupt .................................................... 41
Figure 7.9 Stop Mode Release Timing when Initiated by RESETB ........................................................ 41
Figure 7.10 Crystal/Ceramic Oscillator ................................................................................................... 43
Figure 7.11 External Clock...................................................................................................................... 43
Figure 7.12 Crystal Oscillator.................................................................................................................. 44
Figure 7.13 External Clock...................................................................................................................... 44
Figure 7.14 Clock Timing Measurement at XIN ...................................................................................... 45
Figure 7.15 Clock Timing Measurement at SXIN .................................................................................... 45
Figure 7.16 Operating Voltage Range .................................................................................................... 46
Figure 7.17 Recommended Circuit and Layout....................................................................................... 47
Figure 7.18 Recommended Circuit and Layout with SMPS Power ......................................................... 47
Figure 7.19 RUN (IDD1) Current ............................................................................................................ 48
Figure 7.20 IDLE (IDD2) Current ............................................................................................................ 48
Figure 7.21 SUB RUN (IDD3) Current .................................................................................................... 49
Figure 7.22 SUB IDLE (IDD4) Current .................................................................................................... 49
Figure 7.23 STOP (IDD5) Current .......................................................................................................... 50
List of Tables
Table 1-1 Ordering Information of MC97F2664 ........................................................................................ 9
Table 1-2 Descriptions of pins which are used to programming/reading the Flash ................................. 13
Table 5-1 Normal Pin Description ........................................................................................................... 24
Table 7-1 Absolute Maximum Ratings .................................................................................................... 31
Table 7-2 Recommended Operating Conditions ..................................................................................... 31
Table 7-3 A/D Converter Characteristics ................................................................................................ 32
Table 7-4 Power-on Reset Characteristics ............................................................................................. 33
Table 7-5 LVR and LVI Characteristics ................................................................................................... 33
Table 7-6 High Internal RC Oscillator Characteristics ............................................................................. 34
January 15, 2020 Ver. 1.13 5

MC97F2664
Table 7-7 Internal WDTRC Oscillator Characteristics ............................................................................. 34

Table 7-8 DC Characteristics .................................................................................................................. 35
Table 7-9 AC Characteristics .................................................................................................................. 37
Table 7-10 SPI Characteristics ............................................................................................................... 38
Table 7-11 UART Characteristics ........................................................................................................... 39
Table 7-12 I2C Characteristics ............................................................................................................... 40
Table 7-13 Data Retention Voltage in Stop Mode ................................................................................... 41
Table 7-14 Internal Flash Rom Characteristics ....................................................................................... 42
Table 7-15 Input/Output Capacitance ..................................................................................................... 42
Table 7-16 Main Clock Oscillator Characteristics ................................................................................... 43
Table 7-17 Sub Clock Oscillator Characteristics ..................................................................................... 44
Table 7-18 Main Oscillation Stabilization Characteristics........................................................................ 45
Table 7-19 Sub Oscillation Stabilization Characteristics ......................................................................... 45
6 January 15, 2020 Ver. 1.13

MC97F2664
MC97F2664
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 12-BIT A/D CONVERTER
1. Overview
1.1 Description
The MC97F2664 is advanced CMOS 8-bit microcontroller with 64k bytes of FLASH. This is powerful
microcontroller which provides a highly flexible and cost effective solution to many embedded control applications.
This provides the following features : 64k bytes of FLASH, 256 bytes of IRAM, 4,096 bytes of XRAM , general
purpose I/O, basic interval timer, watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output,
watch timer, buzzer driving port, SPI, UART, I2C, 12-bit A/D converter, on-chip POR, LVR, LVI, on-chip oscillator
and clock circuitry. The MC97F2664 also supports power saving modes to reduce power consumption.
Device Name FLASH XRAM IRAM ADC I/O PORT Package
MC97F2664L 15 channel 61 64 LQFP-1010

MC97F2664L14 15 channel 61 64 LQFP-1414
64k bytes 4,096 bytes 256 bytes
MC97F2664UB 15 channel 61 64 QFN
MC97F2464Q 10 channel 41 44 MQFP-1010
January 15, 2020 Ver. 1.13 7

MC97F2664
1.2 Features
• CPU • Low Voltage Indicator

- 8 Bit CISC Core (8051 Compatible) - 13 level detect (2.00V/ 2.10V/ 2.20V/ 2.32V/
• ROM (FLASH) Capacity 2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/ 3.38V/
3.67V/ 4.00V/ 4.40V)
- 64k Bytes
• Interrupt Sources
- Flash with self read/write capability
- External Interrupts
- On chip debug and In-system programming (ISP)
(EINT0~A, EINT10~19) (21)
- Endurance : 10,000 times (Sector 0~1019)
100,000 times (Sector 1020~1023) - Timer(0/1/2/3/4/5/6/7/8/9) (14)
- Retention : 10 years - WDT (1)
• 256 Bytes IRAM - BIT (1)
• 4,096 Bytes XRAM - WT (1)

- SPI 2/3 (2)
• General Purpose I/O (GPIO)
- UART 2/3/4 (6)
- Normal I/O : 61 Ports
- USI0/1 (4)
(P0, P1,P2,P3,P4,P5,P6,P7[4:0])
- ADC (1)
• Basic Interval Timer (BIT)
- Stack OVF(1)
- 8Bit × 1ch
• Internal RC Oscillator
- Watch Dog Timer (WDT)
- Internal RC frequency:
- 8Bit × 1ch
16MHz ±1.5% (TA= 0 ~ +50°C)
- 5kHz internal RC oscillator
• Power Down Mode
• Timer/ Counter
- STOP, IDLE mode
- 8Bit × 4ch (T0/T1/T2/T3)
• Operating Voltage and Frequency
- 16Bit × 6ch (T4/T5/T6/T7/T8/T9)
- 1.8V ~ 5.5V (@32 ~ 38kHz with X-tal)
• Programmable Pulse Generation
- 1.8V ~ 5.5V (@0.4 ~ 4.2MHz with X-tal)
- 8Bit PWM (by T0/T1/T2/T3)
- 2.7V ~ 5.5V (@0.4 ~ 12.0MHz with X-tal)
- Pulse generation (by T4/T5/T6/T7/T8/T9)
- 3.0V ~ 5.5V (@0.4 ~ 16.0MHz with X-tal)
• Watch Timer (WT)
- 1.8V ~ 5.5V (@0.5 ~ 8.0MHz with Internal RC)
- 3.91ms/0.25s/0.5s/1s/1m interval at 32.768kHz
- 2.0V ~ 5.5V (@0.5 ~ 16.0MHz with Internal RC)
• Buzzer
- Voltage dropout converter included for core
- 8Bit × 1ch
• Minimum Instruction Execution Time
• SPI
- 125nS (@ 16MHz main clock)
- 8Bit × 2ch
- 61us (@t 32.768kHz sub clock)
• UART
• Operating Temperature: – 40 ~ + 85℃
- 8Bit × 3ch
• Oscillator Type
• USI (UART + SPI + I2C)
- 0.4-16MHz Crystal or Ceramic for main clock
- 8Bit UART × 2ch, 8Bit SPI × 2ch, and I2C × 2ch
- 32.768kHz Crystal for sub clock
• 12 Bit A/D Converter
• Package Type
- 15 Input channels
- 64 LQFP-1010
• Power On Reset
- 64 LQFP-1414
- Reset release level (1.4V)
- 64 QFN
• Low Voltage Reset
- 44 MQFP-1010
- 14 level detect (1.60V/ 2.00V/ 2.10V/ 2.20V/
2.32V/ 2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/ - Pb-free package
3.38V/ 3.67V/ 4.00V/ 4.40V)
8 January 15, 2020 Ver. 1.13

MC97F2664
1.3 Ordering Information
Table 1-1 Ordering Information of MC97F2664
Device name ROM size IRAM size XRAM size Package

MC97F2664L 64 LQFP-1010
MC97F2664L14 64 LQFP-1414
64k bytes FLASH 256 bytes 4,096 bytes
MC97F2664UB 64 QFN
MC97F2464Q 44 MQFP-1010
MC97F2x64 L B 14 (T)
MC97F2x64 Family Name

x=6 64 pin
x=4 44pin
Package Type
L LQFP
Q MQFP
U QFN
RoHS
B Halogen Free
Package Body Size

2
10 10 x 10 mm
2
14 14 x 14 mm
Packing
(T) Tape & Reel
Figure 1.1 Device Nomenclature
January 15, 2020 Ver. 1.13 9

MC97F2664
1.4 Development Tools
1.4.1 Compiler
We do not provide the compiler. Please contact the third parties.

The core of MC97F2664 is Mentor 8051. And, device ROM size is smaller than 64k bytes. Developer can use all
kinds of third party’s standard 8051 compiler.
1.4.2 OCD2 emulator and debugger
The OCD2 (On Chip Debug 2) emulator supports ABOV Semiconductor’s 8051 series MCU emulation.
The OCD2 interface uses two-wire interfacing between PC and MCU which is attached to user’s system. The
OCD2 can read or change the value of MCU internal memory and I/O peripherals. And the OCD2 also controls
MCU internal debugging logic, it means OCD2 controls emulation, step run, monitoring, etc.
The OCD2 is very flexible, powerful and faster than OCD1(Real time monitoring, RAM break, Emulation time
measuring…). The MC97x series is supported by only OCD2.
The OCD2 Debugger program works on all Microsoft-Windows operating system.
If you want to see more details, please refer to OCD2 debugger manual. You can download debugger S/W and
manual from our web-site.
Connection:
- DSCL (MC97F2664 P62 port)
- DSDA (MC97F2664 P63 port)
- RTIME (MC97F2664 RUNFLAG port, Option)
NOTE) MC97F2664 Use Only OCD2.
OCD2 connector diagram: Connect OCD2 with user system
1 2 User VCC
3 4 User GND
RUNFLAG 5 6 DSCL
7 8 DSDA
9 10
Figure 1.2 Debugger(OCD2) and Pin description
10 January 15, 2020 Ver. 1.13

MC97F2664
1.4.3 Programmer
Single programmer :
E-PGM+ : It programs MCU device directly.
DSDA
VDD VSS
DSCL
RUNFLAG
Figure 1.3 E-PGM+(Single writer)
January 15, 2020 Ver. 1.13 11

MC97F2664
OCD emulator : It can write code in MCU device too, because OCD debugging supports ISP (In System
Programming).
It does not require additional H/W, except developer’s target system.
Gang programmer : E-GANG4 and E-GANG6

- It can run PC controlled mode.
- It can run standalone without PC control too.
- USB interface is supported.
- Easy to connect to the handler.
Figure 1.4 E-GANG4 and E-GANG6 (for Mass Production)
12 January 15, 2020 Ver. 1.13

MC97F2664
1.5 MTP programming
1.5.1 Overview
The program memory of MC97F2664 is MTP Type. This flash is accessed by serial data format. There are five
pins(DSCL, DSDA, RUNFLAG, VDD, VSS) for programming/reading the flash.
Table 1-2 Descriptions of pins which are used to programming/reading the Flash
Main chip During programming

PIN Name
pin name I/O Description
DSCL P62 I Serial clock pin. Input only pin.
Serial data pin. Output port when reading and input port when
DSDA P63 I/O
programming. Can be assigned as input/push-pull output port.
VDD, VSS VDD, VSS - Logic power supply pin.
RUNFLAG RUNFLAG I/O On chip debugger run flag with a pull-down resistor.
1.5.2 On-Board programming
The MC97F2664 needs only five signal lines including VDD and VSS pins for programming FLASH with serial
protocol. Therefore the on-board programming is possible if the programming signal lines are considered when
the PCB of application board is designed.
January 15, 2020 Ver. 1.13 13

MC97F2664
1.5.3 Circuit Design Guide
At the FLASH programming, the programming tool needs 5 signal lines that are DSCL, DSDA, RUNFLAG, VDD
and VSS. When you design the PCB circuits, you should consider the usage of these signal lines for the on-
board programming.
Please be careful to design the related circuit of these signal pins because rising/falling timing of DSCL and
DSDA is very important for proper programming.
E-PGM+, E-GANG4/E-GANG6
VDD
R3 R4
(10kΩ) (10kΩ)
R1 (2kΩ ~ 5kΩ)
DSCL(I) To application circuit
R2 (2kΩ ~ 5kΩ)
DSDA(I/O) To application circuit
Option
RUNFLAG
VDD
VSS
NOTE) 1.In on-board programming mode, very high-speed signal will be provided to pin DSCL and DSDA.
And it will cause some damages to the application circuits connected to DSCL or DSDA port if the
application circuit is designed as high speed response such as relay control circuit. If possible,
the I/O configuration of DSDA, DSCL pins had better be set to input mode.
2. The value of R1 and R2 is recommended value. It varies with circuit of system.
3. The RUNFLAG has an internal pull-down resistor(Typ 50kΩ @ 5V).
4. The DSCL and DSDA have an internal pull-up resistor(Typ 50kΩ @ 5V) during power on or OCD
mode.
5. The option is recommended if the DSCL and DSDL is not used to application circuit. This can
increase the stability of the system.
Figure 1.5 PCB design guide for on board programming
14 January 15, 2020 Ver. 1.13

MC97F2664
2. Block Diagram
DSDA DSCL RUNFLAG
AN0-AN7/P10-P17 Low Voltage

AN8-AN14/P01-P07 12-Bit A/D Converter
AVREF/P00 Indicator
T0O/PWM0O/P50 On-Chip Debug

Buzzer BUZO/P33
EINT10/P50 8-Bit Timer 0
EC0/P54
MOSI3/P70
T1O/PWM1O/P51 MISO3/P71
SPI3
EINT11/P51 8-Bit Timer 1 SCK3/P72
EC1/P55 M8051 Core SS3/P73
T2O/PWM2O/P52 MOSI2/P34
EINT12/P52 8-Bit Timer 2 MISO2/P35
SPI2
EC2/P56 SCK2/P36
SS2/P37
T3O/PWM3O/P53
EINT13/P53 8-Bit Timer 3 64K Bytes Flash TXD4/P23
UART4
EC3/P57 RXD4/P24
T4O/PWM4O/P30 TXD3/P46
UART3
EINT14/P30 16-Bit Timer 4 RXD3/P47
EC4/P72
XRAM IRAM TXD2/P44
UART2
T5O/PWM5O/P31 RXD2/P45
(4k Bytes) (256 Bytes)
EC5/P73 TXD1/P40
UART1 RXD1/P41
T6O/PWM6O/P32 MOSI1/P40
EINT16/P32 16-Bit Timer 6 MISO1/P41
USI1 SPI1 SCK1/P42
EC6/P74/(P33)
Basic Interval Timer SS1/P43
T7O/PWM7O/P20 SDA1/P40
EINT17/P20 16-Bit Timer 7 I2C1
SCL1/P41
EC7/P35
TXD0/P63
T8O/PWM8O/P21 UART0 RXD0/P62
EINT18/P21 16-Bit Timer 8 Power On Reset
MOSI0/P63
EC8/P36 MISO0/P62
USI0 SPI0 SCK0/P61
T9O/PWM9O/P22 SS0/P60
EC9/P37 I2C0 SDA0/P63
Low Voltage Reset SCL0/P62
P00/AVREF
P0 Port P70/MOSI3
P01-P07/AN8-AN14
P71/MISO3
P7 Port P72/SCK3/EC4
P10-P17/AN0-AN7/EINT0-EINT7 P1 Port P73/SS3/EC5
P74/EC6
Watchdog Timer
P20/EINT17/T7O/PWM7O
P21/EINT18/T8O/PWM8O 5kHz INT-RC OSC P60/SS0
P22/EINT19/T9O/PWM9O P61/SCK0
P23/TXD4 P62/RXD0/SCL0/MISO0/DSCL
P2 Port P63/TXD0/SDA0/MOSI0/DSDA
P24/RXD4 P6 Port
P25/EINT8 P64/XOUT
P26/EINT9 P65/XIN
P27/EINTA INT-RC OSC P66/SXIN
16MHz P67/SXOUT
P31/EINT15/T5O/PWM5O P50/EINT10/T0O/PWM0O
P32/EINT16/T6O/PWM6O P51/EINT11/T1O/PWM1O
P33/BUZO/(EC6) P52/EINT12/T2O/PWM2O
P3 Port P53/EINT13/T3O/PWM3O
P34/MOSI2 P5 Port
P35/MISO2/EC7 Watch Timer P54/EC0
P36/SCK2/EC8 P55/EC1
P37/SS2/EC9 P56/EC2
P57/EC3/RESETB
P40/TXD1/SDA1/MOSI1
P41/RXD1/SCL1/MISO1
P42/SCK1 Voltage
P43/SS1 RESETB
P4 Port Down SXOUT
P44/TXD2 CLOCK/SYSTEM
P45/RXD2 Converter SXIN
CONTROL XIN
P46/TXD3
P47/RXD3 XOUT
VDD VSS
Figure 2.1 Block Diagram

NOTE) The P03-P07, P23-P27, P52-P56, and P7 are not in the 44-pin package.
January 15, 2020 Ver. 1.13 15

MC97F2664
3. Pin Assignment
P63/TXD0/SDA0/MOSI0/DSDA
P62/RXD0/SCL0/MISO0/DSCL
P57/EC3/RESETB
P67/SXOUT
RUNFLAG
P64/XOUT
P61/SCK0
P07/AN14
P06/AN13
P05/AN12
P04/AN11
P66/SXIN
P60/SS0
P65/XIN
VDD
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P56/EC2 1 48 P03/AN10
P55/EC1 2 47 P02/AN9
P54/EC0 3 46 P01/AN8
P53/EINT13/T3O/PWM3O 4 45 P00/AVREF
P52/EINT12/T2O/PWM2O 5 44 P17/EINT7/AN7
P47/RXD3 8 MC97F2664L 41 P14/EINT4/AN4
P46/TXD3
P45/RXD2
9
10
(64-LQFP-1010) 40
39
P13/EINT3/AN3
P12/EINT2/AN2
P44/TXD2 11 38 P11/EINT1/AN1
P43/SS1 12 37 P10/EINT0/AN0
P42/SCK1 13 36 P27/EINTA
P41/RXD1/SCL1/MISO1 14 35 P26/EINT9
P40/TXD1/SDA1/MOSI1 15 34 P25/EINT8
P70/MOSI3 16 33 P24/RXD4
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
P71/MISO3
P72/SCK3/EC4
P23/TXD4
P73/SS3/EC5
P74/EC6
P33/BUZO/(EC6)
P34/MOSI2
P35/MISO2/EC7
P36/SCK2/EC8
P37/SS2/EC9
Figure 3.1 MC97F2664L 64LQFP-1010 Pin Assignment

NOTES) 1. On On-Chip Debugging, ISP uses P6[3:2] pin as DSDA, DSCL.
2. The pin in parentheses can be configured by software control.
16 January 15, 2020 Ver. 1.13

MC97F2664
P57/EC3/RESETB
P67/SXOUT
RUNFLAG
P64/XOUT
P61/SCK0
P07/AN14
P06/AN13
P05/AN12
P04/AN11
P66/SXIN
P60/SS0
P65/XIN
VDD
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P56/EC2 1 48 P03/AN10
P55/EC1 2 47 P02/AN9
P54/EC0 3 46 P01/AN8
P47/RXD3 8 MC97F2664L14 41 P14/EINT4/AN4
P46/TXD3
P45/RXD2
9
10
(64-LQFP-1414) 40
39
P13/EINT3/AN3
P12/EINT2/AN2
P44/TXD2 11 38 P11/EINT1/AN1
P43/SS1 12 37 P10/EINT0/AN0
P70/MOSI3 16 33 P24/RXD4
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
P71/MISO3
P72/SCK3/EC4
P23/TXD4
P73/SS3/EC5
P74/EC6
P33/BUZO/(EC6)
P34/MOSI2
P35/MISO2/EC7
P36/SCK2/EC8
P37/SS2/EC9
Figure 3.2 MC97F2664L14 64LQFP-1414 Pin Assignment

January 15, 2020 Ver. 1.13 17

MC97F2664
P57/EC3/RESETB
P67/SXOUT
RUNFLAG
P64/XOUT
P61/SCK0
P07/AN14
P06/AN13
P05/AN12
P04/AN11
P66/SXIN
P60/SS0
P65/XIN
VDD
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P56/EC2 1 48 P03/AN10
P55/EC1 2 47 P02/AN9
P54/EC0 3 46 P01/AN8
P47/RXD3 8 MC97F2664UB 41 P14/EINT4/AN4
P46/TXD3
P45/RXD2
9
10
(64-QFN) 40
39
P13/EINT3/AN3
P12/EINT2/AN2
P44/TXD2 11 38 P11/EINT1/AN1
P43/SS1 12 37 P10/EINT0/AN0
P70/MOSI3 16 33 P24/RXD4
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
P71/MISO3
P72/SCK3/EC4
P23/TXD4
P73/SS3/EC5
P74/EC6
P33/BUZO/(EC6)
P34/MOSI2
P35/MISO2/EC7
P36/SCK2/EC8
P37/SS2/EC9
Figure 3.3 MC97F2664UB 64QFN Pin Assignment

18 January 15, 2020 Ver. 1.13

MC97F2664
P67/SXOUT
RUNFLAG
P64/XOUT
P61/SCK0
P66/SXIN
P60/SS0
P65/XIN
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
P57/EC3/RESETB 1 33 P02/AN9
P51/EINT11/T1O/PWM1O 2 32 P01/AN8
P47/RXD3 4 30 P17/EINT7/AN7
P46/TXD3
P45/RXD2
5
6
MC97F2464Q 29
28
P16/EINT6/AN6
P15/EINT5/AN5
P44/TXD2 7 (44-MQFP-1010) 27 P14/EINT4/AN4
P43/SS1 8 26 P13/EINT3/AN3
P42/SCK1 9 25 P12/EINT2/AN2
P41/RXD1/SCL1/MISO1 10 24 P11/EINT1/AN1
P40/TXD1/SDA1/MOSI1 11 23 P10/EINT0/AN0
12
13
14
15
16
17
18
19
20
21
22
P33/BUZO/(EC6)
P34/MOSI2
P35/MISO2/EC7
P36/SCK2/EC8
P37/SS2/EC9
Figure 3.4 MC97F2464 44MQFP-1010 Pin Assignment

2. The P03-P07, P23-P27, P52-P56, and P7 pins should be selected as a push-pull output or
an input with pull-up resistor by software control when the 44-pin package is used.
January 15, 2020 Ver. 1.13 19

MC97F2664
4. Package Diagram
Figure 4.1 64-Pin LQFP-1010 Package
20 January 15, 2020 Ver. 1.13

MC97F2664
Figure 4.2 64-Pin LQFP-1414 Package
January 15, 2020 Ver. 1.13 21

MC97F2664
Figure 4.3 64-Pin QFN Package
22 January 15, 2020 Ver. 1.13

MC97F2664
Figure 4.4 44-Pin MQFP-1010 Package
January 15, 2020 Ver. 1.13 23

MC97F2664
5. Pin Description
Table 5-1 Normal Pin Description
PIN
I/O Function @RESET Shared with
Name
P00 I/O Port 0 is a bit-programmable I/O port which can Input AVERF
P01 be configured as an input, a push-pull output, AN8
or an open-drain output.
P02 A pull-up resistor can be specified in 1-bit unit. AN9
P03 The P03-P07 are not in the 44-Pin package. AN10
P04 AN11
P05 AN12
P06 AN13
P07 AN14
P10 I/O Port 1 is a bit-programmable I/O port which can Input AN0/EINT0
P11 be configured as a schmitt-trigger input, a AN1/EINT1
push-pull output, or an open-drain output.
P12 AN2/EINT2
A pull-up resistor can be specified in 1-bit unit.
P13 AN3/EINT3
P14 AN4/EINT4
P15 AN5/EINT5
P16 AN6/EINT6
P17 AN7/EINT7
P20 I/O Port 2 is a bit-programmable I/O port which can Input EINT17/T7O/PWM7O
P21 be configured as a schmitt-trigger input, a EINT18/T8O/PWM8O
P22 A pull-up resistor can be specified in 1-bit unit. EINT19/T9O/PWM9O
P23 The P23-P27 are not in the 44-Pin package. TXD4
P24 RXD4
P25 EINT8
P26 EINT9
P27 EINTA
P30 I/O Port 3 is a bit-programmable I/O port which can Input EINT14/T4O/PWM4O
P31 be configured as a schmitt-trigger input, a EINT15/T5O/PWM5O
P32 A pull-up resistor can be specified in 1-bit unit. EINT16/T6O/PWM6O
P33 BUZO/(EC6)
P34 MOSI2
P35 MISO2/EC7
P36 SCK2/EC8
P37 SS2/EC9
P40 I/O Port 4 is a bit-programmable I/O port which can Input TXD1/SDA1/MOSI1
P41 be configured as an input, a push-pull output, RXD1/SCL1/MISO1
or an open-drain output.
P42 A pull-up resistor can be specified in 1-bit unit. SCK1
P43 SS1
P44 TXD2
P45 RXD2
P46 TXD3
P47 RXD3
24 January 15, 2020 Ver. 1.13

MC97F2664
Table 5-1 Normal Pin Description (Continued)
PIN
Name
P50 I/O Port 5 is a bit-programmable I/O port which Input EINT10/T0O/PWM0O
P51 can be configured as a schmitt-trigger input, EINT11/T1O/PWM1O
a push-pull output, or an open-drain output.
P52 A pull-up resistor can be specified in 1-bit EINT12/T2O/PWM2O
P53 unit. EINT13/T3O/PWM3O
The P52-P56 are not in the 44-Pin
P54 package. EC0
P55 EC1
P56 EC2
P57 EC3/RESETB
P60 I/O Port 6 is a bit-programmable I/O port which Input SS0
P61 can be configured as a schmitt-trigger input, SCK0
a push-pull output, or an open-drain output.
P62 RXD0/SCL0/MISO0/DSCL
A pull-up resistor can be specified in 1-bit
P63 unit. TXD0/SDA0/MOSI0/DSDA
P64 XOUT
P65 XIN
P66 SXIN
P67 SXOUT
P70 I/O Port 7 is a bit-programmable I/O port which Input MOSI3
P71 can be configured as an input, a push-pull MISO3
output, or an open-drain output.
P72 SCK3/EC4
A pull-up resistor can be specified in 1-bit
P73 unit. SS3/EC5
P74 EC6
EINT0 I/O External interrupt inputs Input P10/AN0
EINT1 P11/AN1
EINT2 P12/AN2
EINT3 P13/AN3
EINT4 P14/AN4
EINT5 P15/AN5
EINT6 P16/AN6
EINT7 P17/AN7
EINT8 P25
EINT9 P26
EINTA P27
EINT10 I/O External interrupt and Timer 0 capture input Input P50/T0O/PWM0O
January 15, 2020 Ver. 1.13 25

MC97F2664
PIN
Name
T0O I/O Timer 0 interval output Input P50/EINT0/PWM0O
PWM0O I/O Timer 0 pulse output Input P50/EINT0/T0O
EC0 I/O Timer 0 event count input Input P54
EC3 I/O Timer 3 event count input Input P57/RESETB
EC4 I/O Timer 4 event count input Input P72/SCK3
EC5 I/O Timer 5 event count input Input P73/SS3
EC7 I/O Timer 7 event count input Input P35/MISO2
EC8 I/O Timer 8 event count input Input P36/SCK2
EC9 I/O Timer 9 event count input Input P37/SS2
BUZO I/O Buzzer signal output Input P33/(EC6)
SCK0 I/O Serial 0 clock input/output Input P61
SCK1 I/O Serial 1 clock input/output Input P42
SCK2 I/O Serial 2 clock input/output Input P36/EC8
26 January 15, 2020 Ver. 1.13

MC97F2664
PIN
Name
SCK3 I/O Serial 3 clock input/output Input P72/EC4
MOSI0 I/O SPI 0 master output, slave input Input P63/TXD0/SDA0/DSDA
MOSI1 I/O SPI 1 master output, slave input Input P40/TXD1/SDA1
MOSI2 I/O SPI 2 master output, slave input Input P34
MOSI3 I/O SPI 3 master output, slave input Input P70
MISO0 I/O SPI 0 master input, slave output Input P62/RXD0/SCL0/DSCL
MISO1 I/O SPI 1 master input, slave output Input P41/RXD1/SCL1
MISO2 I/O SPI 2 master input, slave output Input P35/EC7
MISO3 I/O SPI 3 master input, slave output Input P71
SS0 I/O SPI 0 slave select input Input P60
SS1 I/O SPI 1 slave select input Input P43
SS2 I/O SPI 2 slave select input Input P37/EC9
SS3 I/O SPI 3 slave select input Input P73/EC5
TXD0 I/O UART 0 data output Input P63/SDA0/MOSI0/DSDA
TXD1 I/O UART 1 data output Input P40/SDA1/MOSI1
TXD2 I/O UART 2 data output Input P44
RXD0 I/O UART 0 data input Input P62/SCL0/MISO0/DSCL
RXD1 I/O UART 1 data input Input P41/SCL1/MISO1
RXD2 I/O UART 2 data input Input P45
SCL0 I/O I2C 0 clock input/output Input P62/RXD0/MISO0/DSCL
SCL1 I/O I2C 1 clock input/output Input P41/RXD1/MISO1
SDA0 I/O I2C 0 data input/output Input P63/TXD0/MOSI0/DSDA
SDA1 I/O I2C 1 data input/output Input P40/TXD1/MOSI1
AVREF I/O A/D converter reference voltage Input P00
AN0 I/O A/D converter analog input channels Input P10/EINT0
AN1 P11/EINT1
AN2 P12/EINT2
AN3 P13/EINT3
AN4 P14/EINT4
AN5 P15/EINT5
AN6 P16/EINT6
AN7 P17/EINT7
AN8 P01
AN9 P02
AN10 P03
AN11 P04
AN12 P05
January 15, 2020 Ver. 1.13 27

MC97F2664
PIN Name I/O Function @RESET Shared with

A13 I/O A/D converter analog input channels Input P06
A14 P07
RESETB I/O System reset pin with a pull-up resistor when it Input P57/EC3
is selected as the RESETB by CONFIGURE
OPTION
(NOTE3) P63/TXD0/SDA0/MOSI0
DSDA I/O On chip debugger data input/output Input
(NOTE3) P62/RXD0/SCL0/MISO0
DSCL I/O On chip debugger clock input Input
(NOTE3)
RUNFLAG I/O On chip debugger run flag with a pull- Input –
down resistor
XIN I/O Main oscillator pins Input P65
XOUT P64
SXIN I/O Sub oscillator pins Input P66
SXOUT P67
VDD, VSS – Power input pins – –
NOTES) 1. The P03-P07, P22-P26, P53-P57, and P7are not in the 44-Pin package.
2. The P57/EC3/RESETB pin is configured as one of the P57/EC3 and the RESETB pin by the
“CONFIGURE OPTION”.
3. If the P63/TXD0/SDA0/MOSI0/DSDA, P62/RXD0/SCL0/MISO0/DSCL, and RUNFLAG pins are
connected to an emulator, the pins are automatically configured as the debugger pins.
4. The P64/XOUT, P65/XIN, P66/SXIN, and P67/SXOUT pins are configured as a function pin by a
software control.
28 January 15, 2020 Ver. 1.13

MC97F2664
6. Port Structures
6.1 General Purpose I/O Port
Level Shift (1.8V to ExtVDD)
Level Shift (ExtVDD to 1.8V)
VDD
PULL-UP
REGISTER
VDD VDD
OPEN DRAIN
REGISTER
DATA
0
REGISTER MUX
PAD
SUB-FUNC DATA OUTPUT 1
SUB-FUNC ENABLE
SUB-FUNC DIRECTION 1
MUX
DIRECTION
0
REGISTER
CMOS or
Schmitt Level
Input
PORTx INPUT or
SUB-FUNC DATA INPUT
ANALOG CHANNEL
ENABLE
ANALOG INPUT
Figure 6.1 General Purpose I/O Port
January 15, 2020 Ver. 1.13 29

MC97F2664
6.2 External Interrupt I/O Port
Level Shift (1.8V to ExtVDD)
Level Shift (ExtVDD to 1.8V)
VDD
PULL-UP
REGISTER
VDD VDD
OPEN DRAIN
REGISTER
DATA
0
REGISTER MUX
PAD
SUB-FUNC DATA OUTPUT 1
SUB-FUNC ENABLE
SUB-FUNC DIRECTION 1
MUX
DIRECTION
0
REGISTER
VDD
EXTERNAL Q D
INTERRUPT
CP POLARITY
r REG.
INTERRUPT
ENABLE
FLAG
CLEAR CMOS or
Schmitt Level
Input
0
PORTx INPUT or
MUX
SUB-FUNC DATA INPUT
1 Q D
CP
r DEBOUNCE
CLK
DEBOUNCE
ENABLE
ANALOG CHANNEL
ENABLE
ANALOG INPUT
Figure 6.2 External Interrupt I/O Port
30 January 15, 2020 Ver. 1.13

MC97F2664
7. Electrical Characteristics
7.1 Absolute Maximum Ratings
Table 7-1 Absolute Maximum Ratings

Parameter Symbol Rating Unit Note
Supply Voltage VDD -0.3 ~ +6.5 V –
VI -0.3 ~ VDD+0.3 V
Voltage on any pin with respect to VSS
VO -0.3 ~ VDD+0.3 V
Maximum current output sourced by (IOH per
IOH -10 mA
Normal Voltage Pin I/O pin)
∑IOH -80 mA Maximum current (∑IOH)
IOL 60 mA Maximum current sunk by (IOL per I/O pin)
∑IOL 120 mA Maximum current (∑IOL)
Total Power
PT 600 mW –
Dissipation
Storage Temperature TSTG -65 ~ +150 °C –
NOTE) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at any other conditions beyond those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
Table 7-2 Recommended Operating Conditions

(TA= -40°C ~ +85°C)
Parameter Symbol Conditions MIN TYP MAX Unit
fX= 32 ~ 38kHz SX-tal 1.8 – 5.5
fX= 0.4 ~ 4.2MHz 1.8 – 5.5
fX= 0.4 ~ 12.0MHz X-tal 2.7 – 5.5
Operating Voltage VDD V
fx= 0.4 ~ 16MHz 3.0 – 5.5
fX= 0.5 ~ 8.0MHz 1.8 – 5.5
Internal RC
fX= 0.5 ~ 16.0MHz 2.0 – 5.5
Operating Temperature TOPR VDD= 1.8 ~ 5.5V -40 – 85 °C
January 15, 2020 Ver. 1.13 31

MC97F2664
7.3 A/D Converter Characteristics
Table 7-3 A/D Converter Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)
Resolution – – –- 12 – bit
Integral Non-Linear INL – – ±6
Differential Non-
DNL AVREF= 2.7V – 5.5V – – ±1
Linearity LSB
Top Offset Error TOE fx= 8MHz
– – ±5
Zero Offset Error ZOE – – ±5
Conversion Time tCONV 12bit resolution, 8MHz 20 – – us
Analog Input Voltage VAIN – VSS – AVREF
Analog Reference V
AVREF *Note 3 1.8 – VDD
Voltage
VDD18 – – – 1.8 – V
Analog Input Leakage
IAIN AVREF= 5.12V – – 2 uA
Current
Enable – 1 2 mA
ADC Operating Current IADC VDD= 5.12V
Disable – – 0.1 uA
NOTES) 1. Zero offset error is the difference between 000000000000 and the converted output for zero input
voltage (VSS).
2. Top offset error is the difference between 111111111111 and the converted output for top input
voltage (AVREF).
3. When AVREF is lower than 2.7V, the ADC resolution is worse.
32 January 15, 2020 Ver. 1.13

MC97F2664
7.4 Power-On Reset Characteristics
Table 7-4 Power-on Reset Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)
RESET Release Level VPOR – – 1.4 – V
VDD Voltage Rising Time tR 0.5V to 2.0V 0.05 – 5 V/ms
POR Current IPOR – – 0.2 – uA
7.5 Low Voltage Reset and Low Voltage Indicator Characteristics
Table 7-5 LVR and LVI Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)
– 1.60 1.79
1.85 2.00 2.15
1.95 2.10 2.25
2.05 2.20 2.35
2.17 2.32 2.47
2.29 2.44 2.59
VLVR The LVR can select all levels but 2.39 2.59 2.79
Detection Level LVI can select other levels except V
VLVI 1.60V. 2.55 2.75 2.95
2.73 2.93 3.13
2.94 3.14 3.34
3.18 3.38 3.58
3.37 3.67 3.97
3.70 4.00 4.30
4.10 4.40 4.70
Hysteresis △V – – 50 150 mV
Minimum Pulse Width tLW – 100 – – us
Enable (Both) VDD= 3V, – 14.0 24.0
LVR and LVI Current IBL Enable (One of two) RUN Mode – 10.0 18.0 uA
Disable (Both) VDD= 3V – – 0.1
January 15, 2020 Ver. 1.13 33

MC97F2664
7.6 Internal RC Oscillator Characteristics
Table 7-6 High Internal RC Oscillator Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)
Frequency fIRC VDD = 2.0 – 5.5 V – 16 – MHz
TA = 0°C to +50 °C With 0.1uF ±1.5
Tolerance – TA = -20°C to +85 °C Bypass – – ±2.5 %
TA = -40°C to +85 °C capacitor ±3.5
Clock Duty Ratio TOD – 40 50 60 %
Stabilization Time THFS – – – 100 us
Enable – 0.2 – mA
IRC Current IIRC
Disable – – 0.1 uA
NOTE) A 0.1uF bypass capacitor should be connected to VDD and VSS. Refer to the “7.21 Recommended
Circuit and Layout".
7.7 Internal Watch-Dog Timer RC Oscillator Characteristics
Table 7-7 Internal WDTRC Oscillator Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)
Frequency fWDTRC – 2 5 10 kHz
Stabilization Time tWDTS – – – 1 ms
Enable – 1 –
WDTRC Current IWDTRC uA
Disable – – 0.1
34 January 15, 2020 Ver. 1.13

MC97F2664
7.8 DC Characteristics
Table 7-8 DC Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, fXIN= 16MHz)
VIH1 P1, P2, P3, P5, P6, RESETB 0.8VDD – VDD V
Input High Voltage
VIH2 All input pins except VIH1 0.7VDD – VDD V
VIL1 P1, P2, P3, P5, P6, RESETB – – 0.2VDD V
Input Low Voltage
VIL2 All input pins except VIL1 – – 0.3VDD V
Output High VDD= 4.5V, IOH= -2mA,
VOH VDD-1.0 – – V
Voltage All output ports;
VDD=4.5V, IOL= 5mA;
VOL1 – – 1.0 V
All output ports except VOL2
Output Low Voltage
VDD= 4.5V, IOL= 15mA ;
VOL2 – – 1.0 V
P2,P3,P50-53
Input High Leakage
IIH All input ports – – 1 uA
Current
Input Low Leakage
IIL All input ports -1 – – uA
Current
VI=0V, VDD=5.0V 25 50 100
RPU1 TA= 25°C kΩ
All Input ports VDD=3.0V 50 100 200
Pull-Up Resistor
VI=0V, VDD=5.0V 150 250 400
RPU2 TA= 25°C kΩ
RESETB VDD=3.0V 300 500 700
VDD= 5.0V, TA= 25°C
Pull-Down Resistor RPD 10 20 30 kΩ
RUNFLAG
XIN= VDD, XOUT= VSS
RX1 600 1200 2000
OSC feedback TA= 25°C, VDD= 5V
kΩ
resistor SXIN=VDD, SXOUT=VSS
RX2 2500 5000 10000
TA= 25 °C ,VDD=5V
January 15, 2020 Ver. 1.13 35

MC97F2664
Table 7-9 DC Characteristics (Continued)

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, fXIN= 16MHz)
Parameter Symbol Condition MIN TYP MAX Unit
fXIN= 16MHz, VDD= 5V±10% – 4.5 9.0
IDD1
fXIN= 12MHz, VDD= 3V±10% – 3.0 6.0 mA
(RUN)
fIRC= 16MHz, VDD= 5V±10% – 4.0 8.0
fXIN= 16MHz, VDD= 5V±10% – 2.0 4.0
IDD2
fXIN= 12MHz, VDD= 3V±10% – 1.0 2.0 mA
Supply Current (IDLE)
fIRC= 16MHz, VDD= 5V±10% – 1.2 2.4
IDD3 fXIN= 32.768kHz Sub RUN – 60.0 90.0 uA

VDD= 3V±10%
IDD4 TA= 25°C Sub IDLE – 8.0 16.0 uA
IDD5 STOP, VDD= 5V±10%, TA= 25°C – 0.5 3.0 uA
NOTES) 1. Where the fXIN is an external main oscillator, the fSUB is an external sub oscillator, the fIRC is an
internal RC oscillator, and the fx is the selected system clock.
2. All supply current items don’t include the current of an internal Watch-dog timer RC (WDTRC)
oscillator and a peripheral block.
3. All supply current items include the current of the power-on reset (POR) block.
36 January 15, 2020 Ver. 1.13

MC97F2664
7.9 AC Characteristics
Table 7-9 AC Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)
RESETB input low width tRST Input, VDD= 5V 10 – – us
tIWH,
Interrupt input high, low width All interrupt, VDD= 5V 200 – –
tIWL
External Counter Input High, tECWH, ECn, VDD = 5 V
200 – – ns
Low Pulse Width tECWL (n= 0 - 9)
External Counter Transition tREC, ECn, VDD = 5 V
20 – –
Time tFEC (n= 0 - 9)
t RST
RESETB
0.2 VDD
Figure 7.1 Input Timing for RESETB
t IWL tIWH
External
Interrupt 0.8 VDD
0.2 VDD
Figure 7.2 Input Timing for External Interrupts
t ECWL t ECWH
t FEC tREC
ECn
Figure 7.3 Input Timing for EC0 – EC9
January 15, 2020 Ver. 1.13 37

MC97F2664
7.10 SPI Characteristics
Table 7-10 SPI Characteristics

(TA= -40°C – +85°C, VDD= 1.8V – 5.5V)
Output Clock Pulse Period Internal SCK source 200 – –
tSCK
Input Clock Pulse Period External SCK source 200 – –
Output Clock High, Low

Internal SCK source 70 – –
Pulse Width
tSCKH, tSCKL
Input Clock High, Low
External SCK source 70 – – ns
Pulse Width
First Output Clock Delay Internal/External SCK
tFOD 100 – –
Time source
Output Clock Delay Time tDS – – – 50
Input Setup Time tDIS – 100 – –
Input Hold Time tDIH – 150 – –
SS
(Output/Input)
tSCK
tFOD
SCK
(CPOL=0)
(Output/Input)
tSCKL tSCKH
SCK
(CPOL=1)
(Output/Input)
tDIS tDIH
MISO/MOSI MSB LSB

(Data Input)
tDS
MISO/MOSI MSB LSB

(Data Output)
Figure 7.4 SPI Timing
38 January 15, 2020 Ver. 1.13

MC97F2664
7.11 UART Characteristics
Table 7-11 UART Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, fXIN=11.1MHz)
Parameter Symbol MIN TYP MAX Unit
Serial port clock cycle time tSCK 1250 tCPU x 16 1650 ns
Output data setup to clock rising edge tS1 590 tCPU x 13 – ns
Clock rising edge to input data valid tS2 – – 590 ns
Output data hold after clock rising edge tH1 tCPU - 50 tCPU – ns
Input data hold after clock rising edge tH2 0 – – ns
Serial port clock High, Low level width tHIGH, tLOW 470 tCPU x 8 970 ns
t SCK
t HIGH t LOW
Figure 7.5 Waveform for UART Timing Characteristics
tSCK
Shift Clock
tS1
tH1
Data Out D0 D1 D2 D3 D4 D5 D6 D7
tS2
tH2
Data In Valid Valid Valid Valid Valid Valid Valid Valid
Figure 7.6 Timing Waveform for the UART Module
January 15, 2020 Ver. 1.13 39

MC97F2664
7.12 I2C Characteristics
Table 7-12 I2C Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)
Standard Mode High-Speed Mode

Parameter Symbol Unit
MIN MAX MIN MAX
Clock frequency tSCL 0 100 0 400 kHz
Clock High Pulse Width tSCLH 4.0 – 0.6 –
Clock Low Pulse Width tSCLL 4.7 – 1.3 –
Bus Free Time tBF 4.7 – 1.3 –
Start Condition Setup Time tSTSU 4.7 – 0.6 –
Start Condition Hold Time tSTHD 4.0 – 0.6 – us
Stop Condition Setup Time tSPSU 4.0 – 0.6 –
Stop Condition Hold Time tSPHD 4.0 – 0.6 –
Output Valid from Clock tVD 0 – 0 –
Data Input Hold Time tDIH 0 – 0 1.0
Data Input Setup Time tDIS 250 – 100 – ns
tSCL
tSCLH tSCLL
tSTSU tDIH tSPSU
SCL tSPHD
SDA
tBF
tSTHD tDIS
tVD
SDA
Out
tVD
Figure 7.7 I2C Timing
40 January 15, 2020 Ver. 1.13

MC97F2664
7.13 Data Retention Voltage in Stop Mode
Table 7-13 Data Retention Voltage in Stop Mode

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)
Data retention supply voltage VDDDR – 1.8 – 5.5 V
Data retention supply current IDDDR VDDR= 1.8V, – – 1 uA

(TA= 25°C), Stop mode
IDLE Mode
(Watchdog Timer Active)
Stop Mode
~
~
Normal
Operating Mode
Data Retention
V DD
~
~
V DDDR
Execution of
STOP Instruction
VIH
INT Request
t WAIT
NOTE: tWAIT is the same as (the selected bit overflow of BIT) X 1/(BIT Clock)
Figure 7.8 Stop Mode Release Timing when Initiated by an Interrupt
RESET
Occurs
Oscillation
Stop Mode
~
~
Stabillization Time
Normal
Data Retention Operating Mode
VDD
~
~
V DDDR
Execution of
STOP Instruction
RESETB
0.8 VDD
0.2 VDD
TWAIT
NOTE : tWAIT is the same as (4096 X 4 X 16/fIRC) = (16.4 ms at fx=1MHz).
Figure 7.9 Stop Mode Release Timing when Initiated by RESETB
January 15, 2020 Ver. 1.13 41

MC97F2664
7.14 Internal Flash Rom Characteristics
Table 7-14 Internal Flash Rom Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)
Sector Write Time tFSW – – 2.5 2.7
Sector Erase Time tFSE – – 2.5 2.7 ms
Code Write Protection Time tFHL – – 2.5 2.7
Page Buffer Reset Time tFBR – – – 5 us
Flash Programming Frequency fPGM – 0.4 – – MHz
Endurance of Write/Erase
10,000
(Sector 0~1019)
NFWE – – – Times
Endurance of Write/Erase
100,000
(Sector 1020~1023)
Flash Data Retention Time tRT – 10 – – Years
NOTE) During a flash operation, SCLK[1:0] of SCCR must be set to “00” or “01” (INT-RC OSC or Main X-TAL for
system clock).
7.15 Input/Output Capacitance
Table 7-15 Input/Output Capacitance

(TA= -40°C ~ +85°C, VDD= 0V)
Input Capacitance CIN fx= 1MHz
Output Capacitance COUT Unmeasured pins are – – 10 pF
I/O Capacitance CIO connected to VSS
42 January 15, 2020 Ver. 1.13

MC97F2664
7.16 Main Clock Oscillator Characteristics
Table 7-16 Main Clock Oscillator Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)
Oscillator Parameter Condition MIN TYP MAX Unit
1.8V – 5.5V 0.4 – 4.2
Crystal Main oscillation frequency 2.7V – 5.5V 0.4 – 12.0 MHz
3.0V – 5.5V 0.4 – 16.0
1.8V – 5.5V 0.4 – 4.2
Ceramic Oscillator Main oscillation frequency 2.7V – 5.5V 0.4 – 12.0 MHz
3.0V – 5.5V 0.4 – 16.0
1.8V – 5.5V 0.4 – 4.2
External Clock XIN input frequency 2.7V – 5.5V 0.4 – 12.0 MHz
3.0 V –5.5V 0.4 – 16.0
XIN XOUT
C1 C2
Figure 7.10 Crystal/Ceramic Oscillator
XIN XOUT
External Open
Clock
Source
Figure 7.11 External Clock
January 15, 2020 Ver. 1.13 43

MC97F2664
7.17 Sub Clock Oscillator Characteristics
Table 7-17 Sub Clock Oscillator Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)
Oscillator Parameter Condition MIN TYP MAX Unit
Crystal Sub oscillation frequency 32 32.768 38 kHz
1.8V – 5.5V
External Clock SXIN input frequency 32 – 100 kHz
SXIN SXOUT
C1 C2
Figure 7.12 Crystal Oscillator
SXIN SXOUT
External Open
Clock
Source
Figure 7.13 External Clock
44 January 15, 2020 Ver. 1.13

MC97F2664
7.18 Main Oscillation Stabilization Characteristics
Table 7-18 Main Oscillation Stabilization Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)
Oscillator Parameter MIN TYP MAX Unit
Crystal fx > 1MHz – – 60 ms

Oscillation stabilization occurs when VDD
is equal to the minimum oscillator voltage
Ceramic range. – – 10 ms
External Clock fXIN = 0.4 to 16MHz 31 – 1250 ns

XIN input high and low width (tXH, tXL)
1/fXIN
tXL tXH
XIN 0.8VDD
0.2VDD
Figure 7.14 Clock Timing Measurement at XIN
7.19 Sub Oscillation Characteristics
Table 7-19 Sub Oscillation Stabilization Characteristics

(TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)
Oscillator Parameter MIN TYP MAX Unit
Crystal – – – 10 s
External Clock SXIN input high and low width (tXH, tXL) 5 – 15 us
1/fSUB
tXL tXH
SXIN 0.8VDD
0.2VDD
Figure 7.15 Clock Timing Measurement at SXIN
January 15, 2020 Ver. 1.13 45

MC97F2664
7.20 Operating Voltage Range
(fXIN=0.4 to 16MHz) (fSUB=32 to 38kHz)
16.0MHz
32.768kHz
12.0MHz
4.2MHz
0.4MHz
1.8 2.7 3.0 5.5 1.8 5.5
Supply voltage (V) Supply voltage (V)
Figure 7.16 Operating Voltage Range
46 January 15, 2020 Ver. 1.13

MC97F2664
7.21 Recommended Circuit and Layout
{ This 0.1uF capacitor should be within

1cm from the VDD pin of MCU on the
PCB layout. } VDD VCC
VDD +
0.1uF
0.1uF DC Power
VSS
VCC
The MCU power line (VDD and VSS)
High-Current Part { should be separated from the high-

current part at a DC power node on
the PCB layout.
}
MC97F2664
Infrared LED,
{ FND(7-Segment),
,,,,,
etc
}
I/O
0.01uF
{ This 0.01uF capacitor is alternatively

for noise immunity. }
X-tal
XIN The main and sub crystal should be within 1cm from the pins of MCU on the PCB layout.
XOUT
C1 The load capacitors of the sub clock
SXIN - C1, C2: CL x 2 ± 15%
- CL = (C1 x C2)/(C1 + C2) - Cstray
C2 - CL: the specific capacitor value of crystal
SXOUT - Cstray: the parasitic capacitor of a PCB (1pF – 1.5pF)
32.768kHz
Figure 7.17 Recommended Circuit and Layout
7.22 Recommended Circuit and Layout with SMPS Power
SMPS Side MCU Side

VCC VDD
SMPS
R1
MCU
Option
VSS
C1 C2 C3
1. The C1 capacitor is to flatten out the voltage of the SMPS power, VCC.
√ Recommended C1: 470uF/25V more.
2. The R1 and C2 are the RC filter for VDD and suppress the ripple of VCC.
√ Recommended R1: 10Ω - 20Ω
√ Recommended C2: 47uF/25V more
√ The R1 and C2 should be as close by the C3 as possible.
√ The R1 is optional so it may not apply.
3. The C3 capacitor is used for temperature compensation because an electrolytic capacitor
becomes worse characteristics at low temperature.
√ Recommended C3: ceramic capacitor 2.2uF more
√ The C3 should be within 1cm from VDD pin of MCU on the PCB layout.
4. The above circuit is recommended to improve noise immunity (EFT, Surge, ESD, etc) when the
SMPS supplies the VDD of MCU.
Figure 7.18 Recommended Circuit and Layout with SMPS Power
January 15, 2020 Ver. 1.13 47

MC97F2664
7.23 Typical Characteristics
These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed.
In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only
for information and devices are guaranteed to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a
period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and
(mean - 3σ) respectively where σ is standard deviation.
mA
6.00
5.00
16MHz -40℃
4.00 16MHz +25℃
16MHz +85℃
3.00
IRC 16MHz -40℃
2.00 IRC 16MHz +25℃

IRC 16MHz +85℃
1.00
0.00
2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V
Figure 7.19 RUN (IDD1) Current
mA
2.50
2.00
16MHz -40℃
16MHz +25℃
1.50
16MHz +85℃
IRC 16MHz -40℃
1.00
IRC 16MHz +25℃
0.50 IRC 16MHz +85℃
0.00
2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V
`
Figure 7.20 IDLE (IDD2) Current
48 January 15, 2020 Ver. 1.13

MC97F2664
uA
120.0
100.0
80.0
-40℃
60.0
+25℃
40.0 +85℃
20.0
0.0
2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V
` `
Figure 7.21 SUB RUN (IDD3) Current
uA
35.0
30.0
25.0
20.0 -40℃
15.0 +25℃
+85℃
10.0
5.0
0.0
2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V
`
Figure 7.22 SUB IDLE (IDD4) Current
January 15, 2020 Ver. 1.13 49

MC97F2664
uA
5.00
4.00
3.00
-40℃
+25℃
2.00
+85℃
1.00
0.00
2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V
`
Figure 7.23 STOP (IDD5) Current
50 January 15, 2020 Ver. 1.13

DS MC97F2x64 Eng

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MC97F2664

ABOV SEMICONDUCTOR Co., Ltd.

Data Sheet (Ver. 1.12)

January 15, 2020 Ver. 1.13 1

2 January 15, 2020 Ver. 1.13

VERSION 1.7 (April 13, 2015)

January 15, 2020 Ver. 1.13 3

Figure 3.3 MC97F2664UB 64QFN Pin Assignment ................................................................................ 18

January 15, 2020 Ver. 1.13 5

Table 7-7 Internal WDTRC Oscillator Characteristics ............................................................................. 34

6 January 15, 2020 Ver. 1.13

Device Name FLASH XRAM IRAM ADC I/O PORT Package

MC97F2664L 15 channel 61 64 LQFP-1010

January 15, 2020 Ver. 1.13 7

• CPU • Low Voltage Indicator

• 256 Bytes IRAM - BIT (1)

• 4,096 Bytes XRAM - WT (1)

8 January 15, 2020 Ver. 1.13

1.3 Ordering Information

Table 1-1 Ordering Information of MC97F2664

Device name ROM size IRAM size XRAM size Package

MC97F2x64 Family Name

Package Body Size

Figure 1.1 Device Nomenclature

January 15, 2020 Ver. 1.13 9

1.4 Development Tools

We do not provide the compiler. Please contact the third parties.

1.4.2 OCD2 emulator and debugger

Figure 1.2 Debugger(OCD2) and Pin description

10 January 15, 2020 Ver. 1.13

Figure 1.3 E-PGM+(Single writer)

January 15, 2020 Ver. 1.13 11

Gang programmer : E-GANG4 and E-GANG6

Figure 1.4 E-GANG4 and E-GANG6 (for Mass Production)

12 January 15, 2020 Ver. 1.13

1.5 MTP programming

Main chip During programming

1.5.2 On-Board programming

January 15, 2020 Ver. 1.13 13

1.5.3 Circuit Design Guide

Figure 1.5 PCB design guide for on board programming

14 January 15, 2020 Ver. 1.13

DSDA DSCL RUNFLAG

AN0-AN7/P10-P17 Low Voltage

T0O/PWM0O/P50 On-Chip Debug

Figure 2.1 Block Diagram

January 15, 2020 Ver. 1.13 15

Figure 3.1 MC97F2664L 64LQFP-1010 Pin Assignment

16 January 15, 2020 Ver. 1.13

Figure 3.2 MC97F2664L14 64LQFP-1414 Pin Assignment

January 15, 2020 Ver. 1.13 17

Figure 3.3 MC97F2664UB 64QFN Pin Assignment

18 January 15, 2020 Ver. 1.13

Figure 3.4 MC97F2464 44MQFP-1010 Pin Assignment

January 15, 2020 Ver. 1.13 19

Figure 4.1 64-Pin LQFP-1010 Package

20 January 15, 2020 Ver. 1.13

Figure 4.2 64-Pin LQFP-1414 Package

January 15, 2020 Ver. 1.13 21

Figure 4.3 64-Pin QFN Package

22 January 15, 2020 Ver. 1.13

Figure 4.4 44-Pin MQFP-1010 Package

January 15, 2020 Ver. 1.13 23