LD Lab Manual[21EC381]

LD (LOGIC DESIGN) LAB MANUAL USING

MULTISIM
[21EC381]

PREPARED BY MAMATHA MALLESH, ASST. PROFESSOR, DEPT. OF ECE, JVIT, BIDADI 1

 LD Lab Manual[21EC381]

LIST OF EXPERIMENTS
1. Implementation of De Morgan’s theorem and SOP/POS expressions using
Pspice/Multisim.
2. Implementation of Half Adder, Full Adder, Half Subtractor and Full Subtractor using
Pspice/Multisim.
3. Design and implementation of 4-bit Parallel Adder/ Subtractor using IC 7483 and BCD
to Excess-3 code conversion and vice-versa using Pspice/Multisim.
4. Design and implement of IC 7485 5-bit magnitude comparator using Pspice/Multisim.
5. To Realize Adder & Subtractor using IC 74153 (4:1 MUX) and 4-variable function
using IC74151 (8:1MUX) using Pspice/Multisim.
6. To realize Adder and Subtractor using IC 74139/ 74155N (Demux/Decoder) and Binary
to Gray code conversion & vice versa using 74139/ 74155N using Pspice/Multisim.
7. SR, Master-Slave JK, D & T flip-flops using NAND Gates using Pspice/Multisim.
8. Design and realize the Synchronous counters (up/down decade/binary) using
Pspice/Multisim.
9. Realize the shift registers and their modes (SISO, PISO, PIPO, SIPO) using 7474/7495
using Pspice/Multisim.
10. Design Pseudo Random Sequence generator using 7495 using Pspice/Multisim.
11. Design Serial Adder with Accumulator and simulate using Pspice/Multisim.
12. Design using Pspice/Multisim Mod-N Counters.

PREPARED BY MAMATHA MALLESH, ASST. PROFESSOR, DEPT. OF ECE, JVIT, BIDADI 2

 LD Lab Manual[21EC381]

BASIC GATES
1. NOT GATE

SYMBOL and PIN DIAGRAM

NOT GATE using MULTISIM

2. AND GATE

SYMBOL and PIN DIAGRAM

PREPARED BY MAMATHA MALLESH, ASST. PROFESSOR, DEPT. OF ECE, JVIT, BIDADI 3

 LD Lab Manual[21EC381]

AND GATE using MULTISIM

3. 2-INPUT NAND GATE

SYMBOL and PIN DIAGRAM

NAND GATE using MULTISIM

PREPARED BY MAMATHA MALLESH, ASST. PROFESSOR, DEPT. OF ECE, JVIT, BIDADI 4

 LD Lab Manual[21EC381]

4. OR GATE

SYMBOL and PIN DIAGRAM

OR GATE using MULTISIM

5. NOR GATE

SYMBOL and PIN DIAGRAM

PREPARED BY MAMATHA MALLESH, ASST. PROFESSOR, DEPT. OF ECE, JVIT, BIDADI 5

 LD Lab Manual[21EC381]

NOR GATE using MULTISIM

6. X-OR GATE

SYMBOL and PIN DIAGRAM

X-OR GATE using MULTISIM

PREPARED BY MAMATHA MALLESH, ASST. PROFESSOR, DEPT. OF ECE, JVIT, BIDADI 6

 LD Lab Manual[21EC381]
7. 3-INPUT NAND GATE

SYMBOL and PIN DIAGRAM

3-INPUT NAND GATE using MULTISIM

PREPARED BY MAMATHA MALLESH, ASST. PROFESSOR, DEPT. OF ECE, JVIT, BIDADI 7

 LD Lab Manual[21EC381]

EXPERIMENT NO. 1
DE-MORGAN’S THEOREM
AIM: To implement De Morgan’s theorem and SOP / POS expressions using Multisim.

DEMORGAN’S 1ST THEOREM STATEMENT:

“The compliment of product of 2 or more variables is equal to the sum of compliment of 2 or
more variables”

[A.B]' = A' + B'

CIRCUIT DIAGRAM

Truth Table:
Inputs Outputs
A B X = [A.B]' Y= A' + B'
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

DEMORGAN’S 1ST THEOREM using MULTISIM

PREPARED BY MAMATHA MALLESH, ASST. PROFESSOR, DEPT. OF ECE, JVIT, BIDADI 8

 LD Lab Manual[21EC381]
DEMORGAN’S 2ND THEOREM STATEMENT:
“The compliment of sum of 2 or more variables is equal to the product of compliment of 2 or
more variables”
[A + B]' = A' . B'
CIRCUIT DIAGRAM

Truth Table:

Inputs Outputs
A B X = [A + B]' Y= A' . B'
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0

DEMORGAN’S 2ND THEOREM using MULTISIM

PREPARED BY MAMATHA MALLESH, ASST. PROFESSOR, DEPT. OF ECE, JVIT, BIDADI 9

 LD Lab Manual[21EC381]

VERIFICATION OF SOP AND POS EXPRESSIONS

a) SOP expression

Theory: SOP: - It is the Sum of product form in which the terms are taken as 1. It is denoted in the K-map
expression by sigma (∑)
Y= A.B + A'B'

CIRCUIT DIAGRAM

Truth Table:
Inputs Outputs
A B A' B' A.B A'B' Y= A.B + A'B'
0 0 1 1 0 1 1
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 1 0 0 1 0 1

SOP EXPRESSION using MULTISIM

PREPARED BY MAMATHA MALLESH, ASST. PROFESSOR, DEPT. OF ECE, JVIT, BIDADI 10

 LD Lab Manual[21EC381]
b) POS expression

Theory: POS: - It is the product of the sums form in which the terms are taken as 0. It is denoted in the K-
Map expression by the Sign pie (π)
Y= (A+B) (B+ C) (A + C')
CIRCUIT DIAGRAM

Truth Table:
Inputs Outputs
A B C C' A+B B+ C A + C' Y= (A+B) (B+ C) (A + C')
0 0 0 1 0 0 1 0
0 0 1 0 0 1 0 0
0 1 0 1 1 1 1 1
0 1 1 0 1 1 0 0
1 0 0 1 1 0 1 0
1 0 1 0 1 1 1 1
1 1 0 1 1 1 1 1
1 1 1 0 1 1 1 1

POS EXPRESSION using MULTISIM

RESULT: De Morgan’s theorem is verified and SOP / POS expressions has been realized using Multisim.

PREPARED BY MAMATHA MALLESH, ASST. PROFESSOR, DEPT. OF ECE, JVIT, BIDADI 11