Lecture-24

ARITHMETIC GROUP:
The instructions of this group perform the arithmetic operations on the
operands. Normally two operands are necessary for any arithmetic
operation. One of the operand is always assumed to be available in
accumulator. The other operand can be made available in one of the
three locations:
(a) In an internal general purpose register (r).
(b) In a memory location pointed by M-pointer i.e., (H, L) pair.
(c) Immediately in the instruction itself as a 2nd byte.
All the flags of Flag register are affected as per standard rule. There
are 20 basic instructions in this group. The format of the operation
code is shown in fig5.15.
D7 D5D4 D2D1
0 1 D3 00 01 11 10 D0 00 01 11 10
D6
I/O
0 DAD A 0 ADD SUB 0 INR
DAA

SBB INX
1 AI 1 ADC 1 DAD DAA DCR
DCX

(DDD) (SSS)

Fig.5.15 Format of Arithmetic Group Instructions

1. ADD r: This is a single byte instruction. The meaning of the

instruction is “Add the content of register (r) to the content of
accumulator and store the result back into the accumulator”. The
macro RTL implemented is
(A) (A) + (r)
The opcode of the instruction is,
 1 0 0 0 0 S S S N

It has 7 variations for 7 internal general purpose registers.

The micro RTL flow is given below:

Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. ADD r = 1.

Machine Cycle- 2 or (Machine Cycle-1 of next instruction):

OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
FEO [(Temp) (r)]
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(A) (Temp) + (A)]
It requires single machine cycle OFMC and 4 states. The addressing
mode is register addressing mode.

2. ADD M: This is a single byte instruction. The meaning of the

instruction is “Add the content of memory location whose address is
in (H,L) pair to the content of accumulator and store the result back
into the accumulator”. The macro RTL implemented is
(A) (A) + M(H,L)
The opcode of the instruction is,

1 0 0 0 0 1 1 0 N
It has no variations. Register indirect addressing mode is used in this
instruction. The micro RTL flow is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. ADD M = 1.

Machine Cycle- 2:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (H), AD7-AD0 (L), ALE =
T2: RD = 0, AD7-AD0 M(AB)
T3: RD = 1, , (Temp) AD7-AD0

Machine Cycle- 3 or (Machine Cycle-1 of next instruction):

OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(A) (Temp) + (A)]

It requires two machine cycles OFMC & MRMC and 7 states.

3. ADI DATA: It is a two byte instruction. The meaning of the
instruction is “Add the content available as the second byte of the
instruction to the content of accumulation and store the result back
into the accumulator”.
The opcode of the instruction is,

1 1 0 0 0 1 1 0 N
<B2> N+1
It has no variations. The macro RTL implemented is
(A) (A) + <B2>
It has immediate addressing mode. The micro RTL flow is given
below:

Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. ADI data = 1.

Machine Cycle- 2:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (Temp) AD7-AD0
Machine Cycle- 3 or (Machine Cycle-1 of next instruction):
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(A) (Temp) + (A)]
It requires two machine cycles OFMC & MRMC and 7 states.

4. ADC r: It is a single byte instruction. The meaning of the

instruction is “Add the content of register (r) to the content of
accumulator with carry and store the result back into accumulator”.
The macro RTL implemented is
(A) (A) + (r) + (CY)
The opcode of the instruction is,

1 0 0 0 1 S S S N

It has 7 variations for 7 internal general purpose registers.

The micro RTL flow is given below:

Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. ADC r = 1.
Machine Cycle- 2 or (Machine Cycle-1 of next instruction):
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
FEO [(Temp) (r)]
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(A) (Temp) + (A) + (CY)]
It requires single machine cycle OFMC and 4 states. The addressing
mode is register addressing mode.

5. ADC M: It is a single byte instruction. The meaning of the

instruction is “Add the contents of memory location whose address is
available in (H, L) pair to the contents of accumulator with carry and
store the result back into accumulator”. The macro RTL implemented
is
(A) (A) + M(H,L) + (CY)
The opcode of the instruction is,

1 0 0 0 1 1 1 0 N

It has no variations. The addressing mode is register indirect

addressing mode. The micro RTL flow is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. ADC M = 1.
Machine Cycle- 2:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (H), AD7-AD0 (L), ALE =
T2: RD = 0, AD7-AD0 M(AB)
T3: RD = 1, , (Temp) AD7-AD0

Machine Cycle- 3 or (Machine Cycle-1 of next instruction):

OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(A) (Temp) + (A) + (CY)]
It requires two machine cycles OFMC & MRMC and 7 states.

6. ACI DATA: It is a two byte instruction. The meaning of the

instruction is “Add the content available as the second byte of
instruction itself to the content to accumulator with carry and store the
result back into the accumulator”. The opcode of the instruction is

1 1 0 0 1 1 1 0 N
<B2> N+1

The macro RTL implemented is

(A) (A) + <B2> + (CY)
It has no variations. It has immediate addressing mode. The micro
RTL flow is
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. ACI data = 1.

Machine Cycle- 2:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (Temp) AD7-AD0

Machine Cycle- 3 or (Machine Cycle-1 of next instruction):

OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(A) (Temp) + (A) + (CY)]
It requires two machine cycles OFMC & MRMC and 7 states.

Note: In all these above instruction all the flags are affected as per
rule.