Lecture-28

10. CMP r: (Compare register with ACC) It is a single byte instruction.

The meaning of the instruction “Compare the content of accumulator
with the content of register (r).” In this instruction, the content of
register (r) is subtracted from the content of accumulator (A) but the
result of the subtraction operation is not stored back into the Acc.
Thus the contents of Acc & register (r) are not destroyed but as result
of this operation the flags are affected as per standard rule as given
below:
If (A) > (r) CY = 0, Z=0
(A) = (r) CY = 0, Z=1
(A) < (r) CY = 1, Z=0

The operation code of the instruction is,

1 0 1 1 1 S S S N

It has seven variations. The addressing mode is register addressing

mode. The micro RTL flow implemented is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. CMP r = 1.
Machine Cycle- 2 or (Machine Cycle-1 of next instruction):
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
FEO [(Temp) (r)]
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(A) - (Temp) operation takes place and flags are affected]
The instruction needs one machine cycle OFMC of 4 states.

11. CMP M: (Compare memory with accumulator) It is a single byte

instruction. The meaning of the instruction is “Compare the content of
accumulator with the content of memory location whose address is
available in (H, L) register pair”. In this instruction, the content of
memory location pointed to by (H, L) register pair is subtracted from
the content of accumulator (A) but the result of the subtraction
operation is not stored back into the Acc. Thus the contents of Acc &
memory are not destroyed but as result of this operation the flags are
affected as per standard rule as given below:
If (A) > M(H, L) CY = 0, Z=0
(A) = M(H, L) CY = 0, Z=1
(A) < M(H, L) CY = 1, Z=0
The operation code is,
The operation code of the instruction is,

1 0 1 1 1 1 1 0 N
It has no variations. The addressing mode is register indirect
addressing mode. The micro RTL flow implemented is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. CMP M = 1.

Machine Cycle- 2:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (H), AD7-AD0 (L), ALE =
T2: RD = 0, AD7-AD0 M(AB)
T3: RD = 1, , (Temp) AD7-AD0

Machine Cycle- 3 or (Machine Cycle-1 of next instruction):

OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(A) - (Temp) operation takes place and flags are affected]
The instruction requires two machine cycles OFMC & MRMC and a
total of 7 states.

12. CPI data: (Compare accumulator with immediate data) This is an

ALP statement. The meaning of the instruction is “Compare the
content of accumulator with the 8-bit data available in the instruction
as immediate data byte”. In this instruction, the 8-bit data available in
the instruction as 2nd byte is subtracted from the content of
accumulator (A) but the result of the subtraction operation is not
stored back into the Acc. Thus the contents of Acc is not destroyed
but as result of this operation the flags are affected as per standard
rule as given below:
If (A) > <B2> CY = 0, Z = 0
(A) = <B2> CY = 0, Z = 1
(A) < <B2> CY = 1, Z = 0
The operation code of the instruction is,

1 0 1 1 0 1 1 0 N
<B2> N+1
It has no variations. The addressing mode is immediate addressing
mode. The micro RTL flow implemented is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. CPI data = 1.

Machine Cycle- 2:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (Temp) AD7-AD0
Machine Cycle- 3 or (Machine Cycle-1 of next instruction):
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(A) - (Temp) operation takes place and flags are affected]
The instruction requires two machine cycles OFMC & MRMC and a
total of 7 states.

13. RLC: This is an ALP statement. The meaning of the instruction is

“Rotate left the content of the accumulator by one bit without carry
flag. The lower order bit & the CY flag are both set to the value
shifted out the high order bit position”. In this instruction it is assumed
that the operand is available in accumulator. The macro RTL
implemented is,
(Ai+1) (Ai) i = 0 to 6
(A0) (A7)
(CY) (A7)
Or,

CY A7 A6 A5 A4 A3 A2 A1 A0
The operation code of the instruction is,

0 0 0 0 0 1 1 1 N

It has no variations. The addressing mode is implied addressing

mode. The micro RTL flow implemented is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. RLC = 1.

Machine Cycle- 3 or (Machine Cycle-1 of next instruction):

OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [RLC operation takes place and flags are affected]
The instruction requires one machine cycle OFMC and a total of 4
states. This instruction is used to check accumulator bits one by one.
Only the CY flag is affected in this operation.

14. RRC: This is an ALP statement. The meaning of the instruction is

“Rotate right the content of the accumulator by one bit without carry
flag. The higher order bit & the CY flag are both set to the value
shifted out the lower order bit position”. In this instruction also it is
assumed that the operand is available in accumulator. The macro
RTL implemented is,
(Ai) (Ai+1) i = 0 to 6
(A7) (A0)
(CY) (A0)
Or,
 CY A7 A6 A5 A4 A3 A2 A1 A0

The operation code of the instruction is,

0 0 0 0 1 1 1 1 N

It has no variations. The addressing mode is implied addressing

mode. The micro RTL flow implemented is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. RRC = 1.

Machine Cycle- 3 or (Machine Cycle-1 of next instruction):

OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [RRC operation takes place and flags are affected]
The instruction requires one machine cycle OFMC and a total of 4
states. This instruction is used to check accumulator bits one by one.
Only the CY flag is affected in this operation.
15. RAL: (Rotate left through carry) This is an ALP statement. The
meaning of the instruction is “Rotate left the content of the
accumulator by one bit through the carry flag. The lower order bit set
equal to the CY flag and CY flag is set to the value shifted out of the
A7 bit.”. In this instruction it is assumed that the operand is available
in accumulator. The macro RTL implemented is,
(Ai+1) (Ai) i = 0 to 6
(CY) (A7)
(A0) (CY)
Or,

CY A7 A6 A5 A4 A3 A2 A1 A0

The operation code of the instruction is,

0 0 0 1 0 1 1 1 N

It has no variations. The addressing mode is implied addressing

mode. The micro RTL flow implemented is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. RAL = 1.

Machine Cycle- 2 or (Machine Cycle-1 of next instruction):

OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [RAL operation takes place and flags are affected]
The instruction requires one machine cycle OFMC and a total of 4
states. This instruction is used to check accumulator bits one by one.
Only the CY flag is affected in this operation.

16. RAR: (Rotate accumulator right through carry) This is an ALP

statement. The meaning of the instruction is “Rotate right the content
of the accumulator by one bit through carry flag. The higher order bit
is set equal to the CY flag and the CY flag is set to the value shifted
out the lower order bit position”. The operand is assumed to be
available in accumulator. The macro RTL implemented is,
(Ai) (Ai+1) i = 0 to 6
(CY) (A0)
(A7) (CY)
Or,

CY A7 A6 A5 A4 A3 A2 A1 A0

The operation code of the instruction is,

0 0 0 1 1 1 1 1 N
It has no variations. The addressing mode is implied addressing
mode. The micro RTL flow implemented is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. RAR = 1.

Machine Cycle- 2 or (Machine Cycle-1 of next instruction):

OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [RAR operation takes place and flags are affected]
The instruction requires one machine cycle OFMC and a total of 4
states. This instruction is used to check accumulator bits one by one.
Only the CY flag is affected in this operation.