Chapter 10

Boundary Scan and

Core-Based Testing

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Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 1
 Outline

Introduction

Digital
Boundary Scan (1149.1)

Boundary Scan for Advanced Networks
(1149.6)

Embedded Core Test Standard (1500)

Comparison between 1149.1 and 1500

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 Boundary Scan

Original
objective: board-level digital testing

Now also apply to:
 MCM and FPGA
 Analog circuits and high-speed networks
 Verification, debugging, clock control, power
management, chip reconfiguration, etc.

History:
 Mid-1980: JETAG
 1988: JTAG
 1990: First boundary scan standard – 1149.1
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 Boundary Scan Family
No. Main target Status
1149.1 Digital chips and interconnects Std. 1149.1-2001
among chips
1149.2 Extended digital serial interface Discontinue
1149.3 Direct access testability interface Discontinue
1149.4 Mixed-signal test bus Std. 1149.4-1999
1149.5 Standard module test and Std. 1149.5-1995
maintenance (MTM) bus (not endorsed by
IEEE since 2003)
1149.6 High-speed network interface Std. 1149.6-2003
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 Core-Based SOC Design
ADC ROM GLUE LOGIC
RAM RAM
PLL
ASIC 1
IP 1
BUS &
DAC INTERCONNECT

ASIC IP 2
DSP CPU 2

RAM DSP ALU

ASIC
ROM ASIC

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 Digital Boundary Scan – 1149.1

Basic concepts

Overall test architecture & operations

Hardware components

Instruction register & instruction set

Boundary scan description language

On-chip test support

Board/system-level control architectures

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 Basic Idea of Boundary Scan
Boundary-scan cell

Internal
Logic

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 A Board Containing 4 IC’s with
Boundary Scan
Boundary-scan cell Boundary-scan chain

Serial
Data in

Internal Internal
Logic Logic

Internal Internal
Serial Logic Logic
Data out

System interconnect
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 1149.1 Boundary-Scan Architecture

Internal
Boundary-Scan Register
(consists of boundary Logic
Scan cells)
1
Internal Registers

Test Data In (TDI) Test Data Out (TDO)

Bypass Register
Miscellaneous Register
1
Instruction Register

Test Mode Select (TMS) TAP

Test Clock (TCK) Controller
1
Test Reset (TRST*) (optional) 9
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 Hardware Components of 1149.1

A test access port (TAP) consisting of :
 4 mandatory pins: Test data in (TDI), Test data out (TDO),
Test mode select (TMS), Test clock (TCK), and
 1 optional pin: Test reset (TRST)

A test access port controller (TAPC)

An instruction register (IR)

Several test data registers
 A boundary scan register (BSR) consisting of boundary
scan cells (BSCs)
 A bypass register (BR)
 Some optional registers (Device-ID register, design-
specified registers such as scan registers, LFSRs for BIST,
etc.)
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 Basic Operations
1. Instruction sent (serially) through TDI into
instruction register.
2. Selected test circuitry configured to respond to
the instruction.
3. Test pattern shifted into selected data register
and applied to logic to be tested
4. Test response captured into some data register
5. Captured response shifted out; new test pattern
shifted in simultaneously
6. Steps 3-5 repeated until all test patterns are
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 Boundary-Scan Circuitry in A Chip
Data Register

Design-Spec. Reg.
Device-ID Reg. M
U 0M
TDO Boundary Scan Reg. X U 1D
T 1 X
TDI
Bypass Reg. (1-bit) EN
TRST* A
TMS P 3
TCK T ClockDR, ShiftDR, UpdateDR
A Reset*
P ClockIR, ShiftIR, UpdateIR IR decode
C 3
Instruction Register
TCK Enable
Select

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 Data registers

Boundary scan register: consists of boundary
scan cells

Bypass register: a one-bit register used to pass
test signal from a chip when it is not involved in
current test operation

Device-ID register: for the loading of product
information (manufacturer, part number, version
number, etc.)

Other user-specified data registers (scan chains,
LFSR for BIST, etc.)

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 A Typical Boundary-Scan Cell (BSC)

Operation modes
 Normal: IN → OUT (Mode = 0)
 Shift: TDI → ... → IN → OUT → ... → TDO (ShiftDR = 1, ClockDR)
 Capture: IN → R1, OUT driven by IN or R2 (ShiftDR = 0, ClcokDR)
 Update: R1 → OUT (Mode_Control = 1, UpdateDR)

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 TAP Controller

A finite state machine with 16 states

Input: TCK, TMS

Output: 9 or 10 signals included ClockDR,
UpdateDR, ShiftDR, ClockIR, UpdateIR,
ShiftIR, Select, Enable, TCK and TRST*
(optional).

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 State Diagram of TAP Controller

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 Main functions of TAP controller

Providing control signals to
 Reset BS circuitry
 Load instructions into instruction register
 Perform test capture operation
 Perform test update operation
 Shift test data in and out

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 States of TAP Controller

Test-Logic-Reset: normal mode

Run-Test/Idle: wait for internal test such as BIST

Select-DR-Scan: initiate a data-scan sequence

Capture-DR: load test data in parallel

Shift-DR: load test data in series

Exit1-DR: finish phase-1 shifting of data

Pause-DR: temporarily hold the scan operation (e.g.,
allow the bus master to reload data)

Exit2-DR: finish phase-2 shifting of data

Update-DR: parallel load from associated shift registers
Note: Controls for IR are similar to those for DR.
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 Instruction Set

BYPASS
 Bypass data through a chip

SAMPLE
 Sample (capture) test data into BSR

PRELOAD
 Shift-in test data and update BSR

EXTEST
 Test interconnection between chips of board

Optional
 INTEST, RUNBIST, CLAMP, IDCODE, USERCODE,
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 Execution of BYPASS Instruction

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 Execution of SAMPLE Instruction

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 Execution of PRELOAD Instruction

Input
M Internal M Output
PRELOAD U Logic U
X X
R1 R2 R1 R2

TDI TDO

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 Execution of EXTEST Instruction (1/3)

Shift-DR (Chip1)

Internal Internal
Logic Logic

TDI Registers TDO TDI Registers TDO

TAP controller TAP controller

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 Execution of EXTEST Instruction (2/3)

Update-DR (Chip1)

Capture-DR (Chip2)

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 Execution of EXTEST Instruction (3/3)

Shift-DR (Chip2)

Internal Internal
Logic Logic

TDI Registers TDO TDI Registers TDO

TAP controller TAP controller

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Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 25
 Execution of INTEST Instruction (1/4)

Shift-DR

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 Execution of INTEST Instruction (2/4)

Update-DR

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 Execution of INTEST Instruction (3/4)

Capture-DR

Internal
Logic

TDI Registers TDO

TAP controller

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 Execution of INTEST Instruction (4/4)

Shift-DR

Internal
Logic

TDI Registers TDO

TAP controller

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 Boundary Scan Description
Language (BSDL)

Now a part of IEEE 1149.1-2001

Purposes:
 Provide standard description language for BS devices.
 Simplify design work for BS – automated synthesis is possible.
 Promote consistency throughout ASIC designers, device
manufacturers, foundries, test developers and ATE
manufacturers.
 Make it easy to incorporation BS into software tools for test
generation, analysis and failure diagnosis.
 Reduce possibility of human error when employing boundary
scan in a design.
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 Features of BSDL

Describes the testability features of BS
devices that are compatible with 1149.1.

S subset of VHDL.

System-logic and the 1149.1 elements that
are absolutely mandatory need not be
specified.
 Examples: BYPASS register, TAP controller, etc.

Commercial tools to synthesize BSDL exist.

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 Scan and BIST Support with
Boundary Scan

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 Bus Master for Chips with
Boundary Scan (1/5)

Ring architecture with shared TMS
Application chips
TDI
TCK #1
TMS
TDO

TDI
Bus master TCK #2
TMS
TDI
TDO
TDO
TMS
TCK

TDI
TCK #N
TMS
TDO
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 Bus Master for Chips with
Boundary Scan (2/5)

Ring architecture with separate TMS
Application chips

TDI
TCK #1
TMS
Bus master TDO

TDI
TDO TDI
TMS1 TCK #2
TMS2 TMS
TDO
TMSN
TCK

TDI
TCK #N
TMS
TDO
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 Bus Master for Chips with
Boundary Scan (3/5)

Star architecture

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 Bus Master for Chips with
Boundary Scan (4/5)

Multi-drop architecture

Multi-Drop Multi-Drop Multi-Drop

Device Device Device

Bus master

TDI
TMS
TCK
TDO
Test Bus
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 Bus Master for Chips with
Boundary Scan (5/5)

Hierarchical architecture

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 Boundary scan for advanced networks –
1149.6

Rationale

Analog test receiver

Digital driver logic

Digital receiver logic

Test access port for 1149.6

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 Rationale

Advanced signaling techniques are required
for multiple-mega-per-second I/O.
 Differential or AC-coupling networks

Coupling capacitor in AC-coupled networks
blocks DC signals.

DC-level applied during EXTEST may
decay to undefined logic level.

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 Capturing AC-Coupled Signal with 1149.1

C U C U

TX RX
VT
Update-DR
VH
TX
VL
VH
RX
VL
Capture-DR 40
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 1149.1 Configuration for Differential
Signaling

C U C U

TX RX

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 Analog Test Receiver Response to AC
and DC-Coupled Signals

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 Digital Driver Logic
Mission
0 Data
Shift out 1
0
0
1
1 C U Mode
AC Mode AC Test Signal
Shift in Insertion, per driver
ShiftDR UpdateDR Mode AC Mode Train/Pulse
ClockDR
1149.1 Bypass 0 X X

Train/Pulse 1149.1 Extest 1 0 X

Extest_Pulse 1 1 0
Extest_Train 1 1 1
RTI State D Q
AC Test Signal
(distributed to all AC
TCK drivers) AC Test Signal Generator
(near TAP Controller)

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 Digital Receiver Logic
Optional, Required for Observe-and-Control Capabilty on Single-Ended Inputs Only
0

Shift Out 1
EXTEST:
Boundary Shift In 1 TCK
Register 0 TAP State Capture-DR Shift_DR
Capture Update
Cell Init_Memory
ShiftDR FF FF
Clock_DR

ClockDR UpdateDR
EXTEST_PULSE EXTEST_PULSE, EXTEST_TRAIN:
or TCK
EXTEST_TRAIN
TAP State Exit*-DR Update_DR
Selected
VHyst TMS
Latch Q
RF Init_Memory
Pad
AC
DC Set
D Hyst
Test CF May be located near
Mem
Receiver TAP controller
Clear
Capture-DR
VT EXTEST
VHyst EXTEST_TRAIN
EXTEST_PULSE
Init_Memory QQ
SET
D
D TMS
(common to all Exit1-DR
Q LG
test receivers) CLR
Exit2-DR
TCK
NOTE: The generated clock (Init_Memory) shown is suitable for rising edge-sensitive behavior only.
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 Example of Modification on 1149.1 TAP –
Driver Behavior During EXTEST_PULSE
Pulse Width

TCK

(TAP State)

Test-Logic Reset Update-xR Run-Test/Idle Select-DR Capture-DR

AC Test Signal

Update Point
Capture Point

AC Pin Driver Data Inverted Data Data

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 Embedded Core Test Standard - 1500

SOC test problems

Overall architecture

Wrapper components and functions

Instruction set

Core test language

Core test supporting and system test
configurations

Hierarchical test control and plug & play

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 SOC Test Problems/Requirements (1/2)

Mixing technologies: logic, processor, memory, analog
 Need various DFT/BIST/other techniques

Deeply embedded cores
 Need Test Access Mechanism

Hierarchical core reuse
 Need hierarchical test management

Different core providers and SOC test developers
 Need standard for test integration

IP protection/test reuse
 Need core test standard/documentation

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 SOC Test Problems/Requirements (2/2)

Higher-performance core pins than SOC pins
 Need on-chip, at-speed testing

External ATE inefficiency
 Need “on-chip ATE”

Long test application time
 Need parallel testing or test scheduling

Test power must be considered
 Need lower power design or test scheduling

Testable design automation
 Need new testable design tools and flow

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 A System Overview of IEEE 1500
Standard

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 Test Interface of A Core Wrapper
W rapper Optional W rapper
Parallel Control Parallel Port (W PP)
W PC
W rapper W rapper
Parallel Input Parallel Output
W PI W PO

Core

W SI W rapper W SO
W rapper W rapper
Serial Input Serial Output
W SC
Required W rapper W rapper
Serial Port (W SP) Serial Control

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 Serial Test Circuitry of 1500 for a Core

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 Wrapper Components

Wrapper series port (WSP)
 Wrapper series input (WSI), Wrapper series output
(WSO), Wrapper series control (WSC)

Wrapper parallel port (WPP) (optional)
 Wrapper parallel input (WPI), Wrapper parallel output
(WPO), wrapper parallel control (WPC)

Wrapper instruction register (WIR)

Wrapper bypass regiester (WBY)

Wrapper data register (WBR)
 Consists of wrapper boundary cells (WBC’s)

Core data register (CDR) (optional) 52
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 Wrapper Series Control (WSC) signals

WRCK: wrapper clock terminal

AUXCKn: Optional auxiliary clocks, where n is
the number of the clocks.

WRSTN: wrapper reset

SelectWIR: determine whether WIR is selected

CaptureWR: enable Capture operation

ShiftWR: enable Shift operation

UpdateWR: enable Update operation

TransferDR: enable Transfer operation
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 Wrapper Instruction Register

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 Wrapper Boundary Register (WBR)

Consists of Wrapper boundary cells (WBC’s)

WBC
 Terminals: Cell functional input (CFI), cell
functional output (CFO), cell test input (CTI), cell
test output (CTO)
 Functional modes: Normal, inward facing, outward
facing, nonhazardous (safe).
 Operation events: Shift, capture, update, transfer,
apply.
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 Events of WBR (WBC)

Shift: data advance one-bit forward on WBR’s
shift path

Capture: data on CFI or CFO are captured and
stored in WBC

Update: data stored in WBC’s shift path storage
are loaded into an off-shift-path storage of the
WBC

Transfer: move data to the storage closest to CTI
or one bit closer to CTO

Apply: a derivative event inferred from other
events to apply data to functional inputs of cores
or functional outputs of WBR
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 Four Symbols Used in Bubble Diagrams for
WBC’s

Storage Data Decision Data paths

element path point from a source

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 Some Typical WBC’s Represented by
Bubble Diagrams

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 Example 10.1 - WIR Interface of WBY,
WBR WDR(s) and CDR(s)
SelectWIR

WIR_WSO
{SelectWIR,
WBR WSO
WRCK,
WRSTN,
CaptureWR, CDR k
ShiftWR, Core_Cntrl
WIR Circuitry

UpdateWR} WDR_Cntrl
CDR_Cntrl DR_Select[n:0]

DR_Select[n:0]
WBR_Cntrl WDR k
WBY_Cntrl
DR_WSO
WSI WBY

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 Example 10.2 - Schematic Diagram of
WBC WC_SD2_CIO
CTI
SHIFT WRCK
D1
XFER

MODE

CFI

CAPT CFO

CTO
D2

IO_FACE WRCK

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 WS_BYPASS Instruction

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 WS_EXTEST Instruction

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 WP_EXTEXT Instruction

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 WS_SAFE Instruction

Disabled

FI Core FO Safe
States
W W
Safe B B
States FO FI
R R

Bypass
WSI WSO
WIR

WSC

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 WS_PRELOAD Instruction

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 WP_PRELOAD Instruction

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 WS_CLAMP Instruction

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 WS_INTEST Instruction

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 WS_INTEST_SCAN Instruction

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 General Parallel TAM Structure

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 Multiplexed TAM Architectures

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 Daisy chained TAM Architecture

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 Direct Access TAM Architectures

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 Local Controller TAM Architectures

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 Core Access Switch (CAS) Architecture

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 Different Functional Modes of CAS

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 Various Types of Test Supporting
Using CAS Structure

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 A Hierarchical Test Architecture
Supporting Plug & Play Feature

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 Detailed I/O and CTC of The
Hierarchical Test Architecture

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 A Hierarchical Test Architecture with I/Os
Compatible to 1149.1

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 Comparison between 1149.1 and 1500
1149.1 1500
Purpose Board-level Core-based
Parallel Mode No Yes
Extra Data/Control Mandatory: TDI, TDO, Mandatory: WSI, WSO, 6 WSC
I/Os TMS, TCK Optional: TransferDR, WPP,
Optional: TRST AUXCKn(s)
FSM Yes No
Transfer Mode No Yes
Latency between Yes No
operations
Mandatory EXTEST, BYPASS, WS_EXTEST, WS_BYPASS,
Instructions SAMPLE, PRELOAD one Wx_INTEST,
WS_PRELOAD (cond. required)
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